TW200805612A - Semiconductor device with a distributed plating pattern and method of reducing stress thereon - Google Patents

Abstract

A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.

Description

200805612 IX. Description of the Invention: [Technical Field] The present invention relates to a substrate, and a semiconductor die package formed therefrom, including a distributed plating pattern so as to be capable of being applied to the semiconductor die Reduce mechanical stress. [Prior Art]: The surge in demand for portable consumer electronic devices has driven the need for high-capacity storage devices. Non-volatile semiconductor memory devices (e.g., Hidden Memory Cards) are increasingly used to meet the continuing rise in demand for digital information storage and exchange. Its portability, versatility and durable design, along with its high reliability and high capacity, make this stencil suit suitable for a wide range of electronic devices, including digital cameras, for example. Digital music player, TV game, buckle eight and honeycomb phone. 2 There are a variety of package configurations known, however, flash memory library storage = Wei can be manufactured as a system package (SiP) or multi-chip module (MCM), in which ^ die attach to the substrate on. The prior art diagram is a top view of a substrate 2〇 having a contour of a plurality of conductor crystals 22, and a cross-section of the substrate and the die of the prior art. The substrate 2A can generally include a conductive pattern (4) in the presence of a line 26, an electrical via 24 defined in or on both sides. The through hole (or channel) 28 is formed by penetrating the substrate, and the conductive pattern on the surface is conductive (4) η μ and the bottom surface are soldered to other electronic components and/or the surface is adhered to the conductive pattern. .. in the extra boundary I21029.doc 200805612 fixed contact 3 0. The steel of the conductive pattern provides a poorly bonded surface to connect the die and the other electronic components to the contact 塾3Q. Therefore, it is known that the electrode should be properly soldered to the die and the component. Contact 具有 with, for example, gold or gold/gold (Ni/Au) keys. A common electric clock technology provides an electric clock bus and an electric clock tail that shortens all of the contacts 30 of the desired key to the area. An electric-clock program can then be performed wherein the substrate is immersed in an aqueous solution containing ions of the money material. The slant provides a current to all of the shortened contact pads that attract the metal ions to electrify the contact pads to the desired thickness. Although electroplating is an effective method for electroplating on a substrate, the keys are still defective. Hundreds of first, the contact is often not interrupted before the package is divided. It is impossible to electrically test the circuit diagram in the substrate before connecting the die. The ice-plated tails of the large area of the ice will occupy valuable space on the substrate and may also generate noise due to the antenna effect. ^ 6 Knowing that the program to be electroplated by other unused bus bars (referred to as the bus-free process) is suitable for the dual-image processing of the popular bus-free program. The dual image processing begins with a substrate having a core and an optional (unpatterned) conductive layer formed on the core. On the surface of the conductive layer by the known imaging procedure of the quilt, the surface of the conductive layer is etched, and then the part of the conductive layer is etched away. ) such as "the first: known imaging procedures (four) and other conductive layers defined in the conductive circuit 円 円 円 円 于 a a a a a a a a a a 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该 对该121029.doc 200805612 The photoresist or the area covered by the Ni/Au plating is etched away. The resulting patterned substrate is then typically laminated in a solder mask 32 (as shown by the wiper) to cover the weld line. All areas of contact with the surface-adhesive component. The die 22 and other components can then be attached to the substrate and electrically connected. Once the electrical connection is made between the die and the substrate, the <RTI ID=0.0>>>>> During the transfer molding process, the molding machine can take up about 0.8 towns of jet force to drive the molding compound into the cavity and surround the surface mount components. A problem with a conventional substrate formed by double image processing is that the surface of the substrate is not flat. Specifically, as described above, both line % and channel 28 are subjected to an electric clock. As shown in the cross-sectional view of Fig. 2, the area of the electric clock has a wheel that is higher than the area of the surrounding electric clock. Therefore, once the substrate is laminated with a solder mask, peaks are formed at the shovel regions and are formed between the 4 plating regions. Due to the high-sales of the transfer molding process, it is. The molding compound on the granules 22 produces a large force on the top of the dies (indicated by arrow A). The downward force on the top of the die 22 for a die package having a footprint of about 4.5 mm by 2.5 faces may be of the order of about 1.2 kgf/mm2. Because of the peaks in the anti-bar mask and ^ under the die -! Gap, these forces will cause a lot of stress in the crystal (4). In the past, the grain was more able to withstand the stresses generated during the transfer molding process. Faces continue to trend toward smaller form factor packages that require extremely thin crystal pulls. Meghe is known to use wafer grinding during the semiconductor process to allow the die to be in the range of about 2 mils to 13 mils. At these thicknesses, the grain may not be able to withstand the stress generated by the 槿掣 _ up sequence (4) and may break: seal,! : The rupture of the grain under the force will generally lead to the necessity of discarding the second coat. "This occurs at the end of semiconductor manufacturing and sealing, so this system is particularly costly and particularly troublesome."

The specific embodiment relates to a substrate, and a +¥ body die package formed therefrom, which includes a distributed electric power meter to reduce mechanical stress on the semiconductor die. In accordance with a particular embodiment of the present invention, the soil panel can be included in the line and contact pads of the electrical clock in the dual image key sequence. Additionally, the substrate can be included in the area referred to herein as a dummy electric ore region, which also includes electroplating. The substrate in a particular embodiment of the invention can be fabricated in a dual image process including channels, plated electrical circuitry, plated contact pads, plated contact fingers, dummy patterns, and dummy plating regions. The plating material in the dummy regions can increase the amount of plating on the surface of the substrate, thereby reducing the space between adjacent plating channels or the leads existing in the conventional substrate. The plating channels and/or lines and plating in the dummy plating regions provide a plating pattern that is evenly distributed across the surface of the substrate. Evenly distributing the electric ore pattern avoids peaks and valleys in the finished substrate. Once the dual image process is completed, a solder mask can be laminated on the top and bottom surfaces of the substrate. Thereafter, one or more germanium grains can be adhered to the substrate. The one or more dies may be soldered to the galvanic contact pad by means of a known wire bonding and/or bonding process to the substrate 121029.doc 200805612 0 The dummy plating pattern can be applied to the surface of the substrate receiving the die from the surface of the substrate, including the remote plating channel/line and the distributed plating pattern of the plating material. The substrate is provided with a flat surface to which the substrate of the die can be attached. At least the adjacent surface of the one or more die 〃々 substrates can then be encapsulated in a molding compound to form a finished semiconductor package. The dummy plating areas can include a variety of configurations of plating. In a specific embodiment, the plating material is fused and separated in a shape such as, for example, a ceramic deposited on the substrate, or a plurality of shaped or otherwise shaped blocks. In the alternative embodiment, the attention is paid: the virtual clock material in the area of the electric vessel can be applied, and the top of the dummy metal pattern formed on the second surface is applied in a straight, curved or irregular shape. length. [Embodiment] The type of ΓΓ is described with reference to Figs. 3 to 17, and relates to the -82 H-shaped casting f package, which includes a distributed electric ore diagram, and, you, six. The reduction of the mechanical response on the semiconductor die is performed in a different form, and should not be construed as being limited to the embodiment of the present invention. Rather, the provision of such / / body shell % examples, so that the disclosure of Gentleman 1 Valley is good and complete, and can be fully understood by the skilled person, and hope that the present invention can be: :: Alternatives, modifications, and equivalents, within the scope and spirit of the invention as defined by the scope of 2:7. In the course of the detailed description of the invention, numerous specific details are set forth. 121029.doc 10 200805612 A specific embodiment of the present invention will now be described with reference to the flow chart of Figure 3 and the cross-sectional side and top views of Figures 4 through 5. Figure 4 shows a cross-sectional side view (before processing) of a substrate 1 on which one half of the conductor package can be formed. Substrate 100 can be part of a substrate panel to simultaneously process a plurality of semiconductor packages. Substrate 100 can be, for example, a printed circuit, board, however, it should be understood that in alternative embodiments, substrate 100 can be a variety of other substrates. The substrate 1A may be formed by a core 102 having a top conductive layer 丨〇4 formed on a top surface of one of the cores 1 〇 2 and formed on a bottom surface of one of the cores 1 〇 2 One of the bottom conductive layers i〇6. The core i 〇 2 may be formed of various dielectric materials such as, for example, a polyimide layer, an epoxy resin including ruthenium and fr5, bismaleimide _triazabenzene (BT), and the like. Although not critical to the invention, core 1〇2 may have a thickness between decibels (μηι) to 200 μηι, although in alternative embodiments the thickness of the core may vary outside of this range. In an alternative embodiment, the core 102 can be ceramic or organic. The conductive layers 104 and 1 can be formed of steel or copper alloy, electroplated copper or electroplated copper alloy, alloy 42 (42Fe/58Ni), copper plated steel or other metals and materials known for use on substrates. The thicknesses of the layers 1〇4 and 1〇6 may be from about 1 μm to 24 mm, but in alternative embodiments the thickness of the layers 1〇4 and 1〇6 may be varied within the range. Outside. Referring now to the flow chart of FIG. 3, the substrate 1 can be drilled through the substrate through a through hole (or channel) 1G8 (FIG. 1()), and electroplated in step 202. Channel 108 is made to allow the conduction, electrical layer [(10) and 丨 (10) to communicate with electricity 121029.doc 200805612. The channels 10S may be formed across the substrate i (10), including at locations below the semiconductor die on the substrate 100, as will be explained below.

The area of the substrate can then be electroplated with a dual image process. The plated region or the electrical circuit for carrying signals throughout the edge substrate, the contact pads of the solderable surface mount component leads, and for establishing electrical power with a host device in which the semiconductor package including the substrate 100 is employed Contact Contacts In addition, as will be explained below, a dummy plating region can be applied to the surface of the substrate 100 to provide a distributed pattern of electricity money on the substrate and evenly distributed over the surface of the substrate 100. The substrate 100 can be plated in a busless, dual image process, typically including one for the substrate! The _image forming program 21G of 00 and - the second imaging procedure for defining the line and the conductive pattern in the substrate 1GG are thin. The first imaging sequence 210 includes a parent step 212 in which the conductive layer forms a mask pattern on the first 6 as shown in FIG. 5. The mask pattern ι2 can be formed in the layer by a known program. 1〇4 and 1〇6, for example, in a micro (four), in this private sequence, a solid photoresist layer is laminated to the layers 1〇4 and 6, and then placed on the photoresist film. Containing the outline of the plating pattern, a = (each layer 104 and 106 a mask). The photoresist film can then be subjected to exposure and development 'to remove the photoresist from the area on the conductive layer to be plated. The pattern m is a negative layer of the plating pattern to be deposited on the conductive layer and the 1G6, and is formed in the step 214, and a plating material Π 4 (for example, Ni/, for example, other materials). Au, then the exposed surface of 1〇4 and 106 (circle 6). The 121029.doc 200805612

The Ni/Au plating layer 114 can be plated by a known procedure such as, for example, any of various thin film deposition processes. In step 216, the mask pattern layer 112 can be stripped (e.g., in a known photoresist stripping step) as shown in FIG. Produce , , . The core 1 〇 2, the solid conductive layer 丨〇 4 and 〇 6 , and the plating material 114 are included. As will be explained in greater detail below, the plating material 114 is electroplated to an electrical circuit for carrying electrical signals and to the surface, the contact pads of the adhesive assembly, however, the plating material 114 is also plated in a distributed pattern. Base

In other areas of the board to help define a flat, uniform surface 0 of the substrate 100, the second imaging process 220 can etch the layers 1〇4 and 1〇6 to form a boundary between layers 4 and/or 106 A conductive pattern comprising an electrical circuit and a helium contact. A procedure for forming the conductive pattern on the D-plane 1 includes a step 222 of forming a mask pattern 12 on the conductive layers 104 and ,6, as shown in FIG. The mask pattern 120 may be formed only on the exposed areas of the conductive layers 1〇4, 1〇6 (ie, the areas of the unclocked clocks), or the mask pattern 12 may be in the exposure The electric (four) domain is cut into. The mask (four) case 12 can be - a known program (such as, for example, a lithography program) forms a zero on the surface of the substrate. In this program, a 訾1,,,,,,,,,,,,,,, The layer is laminated to the surface of the substrate 100. Subsequently, a photomask containing a pattern to be defined in the individual conductive layers 104, 106 may be placed on the photoresist film (each layer of a mask is intended to include a pattern of conductive patterns in the layers (10) and (10), An electrical circuit having a contact 塾 and a signal for carrying signals throughout the substrate (10) is further known to be defined in a region of the layers (10) and (10) where the conductive pattern is not formed. The substrate is reduced in warpage after encapsulation at 121029.doc • 13-200805612. The dummy pattern can be, for example, one of the metal mesh patterns defined in the conductive layers ι 4 and 106 (as shown, for example, in FIG. The 11 hex and w patterns can have many other configurations, such as, for example, U.S. Patent Application Serial No. 11/171,095 entitled "Meth 〇d 〇f

Reducing Warpage In An Ove, Molded IC Package" (Case No. SDK0696.000US), and US Patent Application Serial No. 11 / 171, 819, entitled "Substmte Galactic 〇 c〇尬 (4)

The configuration shown in the Conti face us Electncal Enhancement" (case number SDK0716.000US), both of which are incorporated herein by reference. After the reticle is applied, the mask pattern 12 〇 can then be exposed and developed to shift the mask pattern from the area on the conductive layers 1 〇 4, 1 〇 6 to be etched away.

except. It will be appreciated that the resulting mask pattern 12 can cover all of the plated regions HA, portions of the plated regions 14 or do not cover any portion of the plated regions 114. The exposed areas of the conductive layers 104, 106 (i.e., the areas not covered by the mask pattern 12 or the plating 114) are then etched away in the step using an etchant to define the conductive pattern on the core 102. This dummy pattern is as shown in FIG. The plating area 114 is covered by the mask pattern 12〇, and the etchant removes all areas that do not cover the mask 12 〇. Where the plating region 114 is not or only partially covered by the mask pattern 12, the etchant removes all regions that do not cover the mask pattern 12 or the plating regions 114. If there is a plating region 114 that is not covered by the mask pattern 12, the etchant does not remove the plating regions. The results are all in 121029.doc -14- 200805612. The mask pattern 120 or the areas under the electro-minening area 114 are intact in the conductive layer (10) and 1G6, and the intact areas include electroplated electric lines and Contact pad. Next, the photoresist is moved in step 230. The result is a top view of Fig. 1 . The pattern shown in the cross-sectional side view of the schematic 11 . Just like the picture! ! To make this apparent, the above procedure will result in the substrate 1 having a plating channel ι8, an electric clock line 122, a plated contact pad 124, a plated contact finger 126, a dummy pattern spring 128, and a dummy shovel area 13A. As used herein, the term "electrical connector" can be used to refer to channels, lines, and/or contact pads (all or one or more of them) with or without the plating. The electrical connectors define at least a portion of a circuit on the substrate (and through the substrate). Although the dummy pattern is formed in the conductive layer i 〇 4 and/or 丨〇 6, it does not define a portion of the circuit by the electrical connectors. As indicated in the Background of the Invention, conventional dual image processes result in peaks at the plating lines and channels, and valleys between the plating lines and the pass channels. These peaks and valleys create an uneven surface in the finished substrate that creates mechanical stress in the grains attached to the substrate. However, in accordance with the present invention, the plating material 114 is applied to the channels 1 〇 8 and the lines 122 and applied to the dummy plating in the dummy patterns 128 between the channels 1 〇 8 and the lines 122. Within area 130. The plating 114 in the dummy regions 130 t can enhance the electrical forging on the surface(s) of the substrate 100 such that the space between adjacent plating regions existing in the conventional substrate is reduced, as in the prior art FIG. Shown. The plating channels and/or lines and the electric clocks in the dummy plating regions provide a plating pattern 1 uniformly distributed across the surface of the substrate 1121 (10), 121029.doc -15-200805612. The plating pattern is uniformly distributed in the finished substrate. Peaks and valleys appear. Once the dual image process as described above is completed, the top and bottom surfaces of the substrate 1 can be laminated with a solder mask 132 in a known step 234 to provide the structure contemplated in the figure. The solder mask 132 can cover all areas except the contact pads 124 and the finger 126. Similarly, since the electric money pattern is distributed across the surface of the substrate, the solder mask 132 can provide a flat or flat surface without the presence of peaks and valleys in the prior art. In step 236, one or more of the dies 14 〇 can be adhered to the surface 142 of the substrate 1 as shown in Figures 13 and 14 (the dies 14 are shown in outline in Figure 14). The die 140 can be electrically connected to the substrate 10 by soldering the leads (wire or bow frame fingers - not shown) of the die to a contact pad 124 by a known wire bond and/or SMT bonding process. Hey. The die 14 can be any of a variety of semiconductor wafers such as, for example, a flash memory chip (NOR/NAND), SRAM or DDT, and/or a controller wafer such as an ASIC. However, the configuration of the die 140 is not critical to the invention and other semiconductor wafers are also contemplated. In addition to the lead frame-based die 14'', other electronic components may be surface-bonded to the substrate 10θ in step 236 in a particular embodiment of the invention. The dummy plating pattern 130 can be applied to the surface 142 of the substrate 100 that receives the die 14". Similarly, as shown in the cross-sectional view of Fig. 4, uniformly distributing the plating pattern across the substrate 100 produces a flat or flat surface of the substrate. Thus, the one or more crystals, granules, 14 squats, are placed flat against the base 121029.doc -16 - 200805612 plate (10), thereby reducing or removing the granules produced in prior art structures. Mechanical stress. In step 238, the adjacent surface of the die 14 〇 and at least the substrate ι can be encapsulated in a molding compound 144 as shown in FIG. 15 to form a finished semiconductor package 15G. The package 15() can be used in a variety of SiP packages, including, for example, a flash memory device manufactured by the company of California. The flash memory device can be, for example, a system-SD card, a Compact Flash, a Sman test _ mini milk card, an MMC, an xD card, a combination sd-usb card, and a

TranSflash or - Memory Stick. It should be understood that the seals are used in a variety of other semiconductor device applications. The dummy electric ore region 13 上 shown in Figures 10 and n t includes plating applied in discrete and separate rings! 14. However, in an alternative embodiment, the dummy plated regions 13 include various patterns of (4) (4) (4) (1). For example, the electric clock material 114 can be applied in discrete and discrete shapes, although in alternate embodiments there can be various curved, straight and irregular shapes. Such shapes may range in size from 5G microns to about one millimeter, although the size of such shapes may still be smaller or larger in alternative embodiments. The shape of the shovel 114 in the dummy plating area 13 can be filled and solid as shown, or the center of the shapes can be opened and free of any plating material 1 一 一 one of the plating 114 in the dummy plating area m Still further embodiments are shown in Figures 16 and 17. As seen in the top view of Fig. 16, it can be seen that the plating in the dummy plating region 13〇 can be applied to the surface 121029.doc 37 200805612, which has a straight, curved or irregular shape length. Fragment of. In this male embodiment, the plating material 114 in the dummy electric field 130 can be applied along the outline of the dummy pattern i28. Alternatively or in addition, the plating material 114 in the dummy plating region may be applied to the inner metal portion of the dummy pattern 128, e.g., in Fig. 16, the dummy pattern 128 has a mesh pattern. • Accordingly, the plating material can be applied to the metal portions as a mesh pattern. The mesh pattern of the plating material 114 can match the mesh pattern of the dummy pattern Φ 128. Alternatively, the plating 114 may be applied only to a portion of the gold lip in the dummy pattern 128 (as shown in Figure 16). The configuration of the plating material 114 described above with respect to FIG. 16 can provide a distributed plating as described above and as shown in the cross-sectional side view of FIG. 17, across the substrate 100, as shown in FIG. pattern. </ br> <br><br><br><br><br><br><br><br><br><br><br><br><br><br><br> It is not intended to be exhaustive or to limit the invention to the particular form disclosed. Many modifications and variations are possible in light of the above teachings. The specific embodiments described above are chosen to be illustrative of the principles of the invention and the invention may be practiced insofar as the invention can be practiced in various embodiments. The invention is utilized. It is intended that the scope of the invention be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a conventional substrate showing a profile of a die. Figure 2 is a cross-sectional side view taken through line 2-2 of Figure i. Figure 3 is a flow diagram of the steps of fabricating a substrate and semiconductor package in accordance with an embodiment of the present invention. I21029.doc -18- 200805612 Figure 4 is a cross-sectional side view of one of the substrates at the beginning of the process of fabricating a substrate in accordance with an embodiment of the present invention. Figure 5 is a cross-sectional side view of a substrate having one of the mask patterns bounded on the substrate in accordance with an embodiment of the present invention. Figure 6 is a cross-sectional side view of a substrate having a mask pattern defined on the substrate and a distributed ionization pattern in a space between the mask patterns in accordance with an embodiment of the present invention. Figure 7 is a cross-sectional side view of a substrate having a distributed plating pattern defined on a 'Heil substrate' after the mask has been removed obliquely in accordance with an embodiment of the present invention. 1 is a cross-sectional side view of a substrate having a plating pattern and applied to a substrate in accordance with an embodiment of the present invention to enable patterning of one of the first mask patterns of the electrical lines in the conductive layer. Figure 9 is a cross-sectional side view of a substrate after etching the exposed portion of the conductive layer in accordance with an embodiment of the present invention. _ ^ 1 is a top view of a substrate comprising a distributed electroplating pattern in accordance with one embodiment of the present invention. Fig. η is a cross-sectional side view of a substrate obtained by passing through line 1K11 of Fig. 10. Figure 12 is a cross-sectional side view of a distributed electroplated pattern substrate after lamination of a solder mask according to an embodiment of the present invention. Figure 13 is a top plan view of a substrate including a distributed electroplating pattern according to an embodiment of the present invention, including a profile of a semiconductor die to which it is attached. 121D29.doc -19- 200805612 Fig. 14 is a cross-sectional side view of the substrate obtained through the line 14 of Fig. 13 and Fig. 15 includes a side view having a plating pattern according to the present invention and a semiconductor die. DETAILED DESCRIPTION OF THE INVENTION One of the examples of a distributed electrical-substrate semiconductor package is a cross-sectional view of a semiconductor device according to the present invention - an alternative embodiment - a distributed plating pattern and including a semiconductor to which it is attached One of the contours of the grain

Top view of the substrate. Figure 17 is a cross-sectional side view of a substrate obtained through the line 17-17 of Figure 16 [Major component symbol description] 20 substrate 22 die 24 dielectric core 26 electrical circuit 28 through hole (or channel) 30 contact pad 32 Solder mask 50 substrate 102 core 104 top conductive layer 106 bottom conductive layer 108 through hole (or channel) 112 mask pattern 121029.doc -20, 200805612

114 120 122 124 126 128 130 132 140 142 144 150 Plating Material Mask Pattern Electrical Wiring Contact Pad Contact Fingers Faux Patterns Dummy Plating Area Solder Masks Die Surfaces Molding Compounds Semiconductor Packaging

121029.doc -21 -

Claims (1)

200805612 X. Patent application scope: L A substrate comprising: / connection H, which is formed on the county board - at least part of the circuit, the electrical connector including - a metal layer and a plating layer on the first layer a second metal layer; and a dummy plating region, the adjacent: near 兮笪 φ, 击 gun _ factory ^ 崎 ° ° 荨 荨 electrical connector, the virtual electrical domain includes an unused one in the circuit The cage uses a metal layer and a second metal layer on the layer of the brother. 2. The substrate of claim 1, which is in the form of an anti-knowledge mask, which covers the special electrical connector and the dummy electroplating area pile. Cry 4 Wang Hao/knife, the same time, the second metal layer and the The first all-in-one of the dummy plating regions together provide the solder resist-flat surface.../-to the genus layer 3. The substrate of claim 1, wherein the first metal layer and the electric (four) domain of the electrical connector The first metal layer is bound to the conductive material layer on the substrate. 4. The substrate of claim 1, wherein the first imaginary day of the first dummy plating region of the electrical connector is an electric clock. The genus layer is the same as the substrate of the substrate 1 in the same procedure, wherein the second yoke layer of the dummy electric ore region is provided to fill the space electrically connected to the substrate. A substrate adjacent to a layer of U. 6. According to the substrate of claim 1, the second metal of the virtual metal plate is formed of nickel and gold. Substrate 7. The substrate of claim 1, wherein the dummy key region 〆, _ ._* 丨 I21029.doc 200805612 is a layer of moxibustion on the substrate that is not deposited by the electricity - and is connected to the benefit The occupied area accumulates a consistently uniform distribution pattern. 8. The substrate of claim 1, wherein the dummy layer is deposited on the substrate in a plurality of discrete rings = 〆, 9. The substrate of the request, wherein the dummy plating region The first-disc metal layer is deposited on the conductive layer to form a plurality of segments having a regular length of "straight" 。., or a curve or not 〇·such as the substrate of the item 9 wherein the plurality of regions - The contour. The dummy key 11. The substrate of the ninth item, wherein the plurality of fragments cover at least one part of the pattern of the area &lt;U virtual no key... the substrate of the month east item 1 a solder mask on at least a portion of the electrical connector and the dummy plating regions. 13. A substrate of the present invention, wherein the dummy (four) domains provide at least one substantially flat surface 14. The substrate of claim 1, wherein the second metal layer of the electrical connector is deposited on the conductive layer by the same layer of the dummy electrode region. The substrate of claim 1, wherein the second metal layer of the reed connectors The second metal layer with the dummy plating region is formed of nickel and/or gold. 16. A method of reducing stress attached to a die of a substrate, the substrate comprising a conductive layer, the method comprising the following Step: (a) depositing a plating material on a portion of the 'electric layer corresponding to an electrical connector to be bounded in the conductive layer; 121029.doc 200805612 (b) in the portion of the conductive layer The plating material shall be deposited at a location other than the location of the electrical connectors; (c) at least part of the plating material of the step (4) and the "r", = anti-solder, "steps and (8) The deposited electric clock material defines at least one substantially flat surface of the solder mask; and () attaches the germanium die to the flat surface of the anti-scratch mask: . The step (8) of electroplating the material comprises the step of depositing the electroplated material into a plurality of discrete distributed patterns. In the method of claim 16, the step (8) of depositing the electroplated material comprises depositing the electroplated material into a plurality of discrete loops. Steps. 19. Item 16 The method of seeking, step (b) comprises the deposition of plated material deposited plating material to have a straight, double step profile or an irregular shape of several longitudinal segments. 121029.doc