TW200802696A - Method and semiconductor material for forming silicon device - Google Patents

Method and semiconductor material for forming silicon device

Info

Publication number
TW200802696A
TW200802696A TW096116067A TW96116067A TW200802696A TW 200802696 A TW200802696 A TW 200802696A TW 096116067 A TW096116067 A TW 096116067A TW 96116067 A TW96116067 A TW 96116067A TW 200802696 A TW200802696 A TW 200802696A
Authority
TW
Taiwan
Prior art keywords
semiconductor material
silicon device
forming silicon
wafer
handle
Prior art date
Application number
TW096116067A
Other languages
English (en)
Inventor
Gayle W Miller
Thomas S Moss Iii
Mark A Good
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of TW200802696A publication Critical patent/TW200802696A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
TW096116067A 2006-05-09 2007-05-07 Method and semiconductor material for forming silicon device TW200802696A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/382,455 US7629649B2 (en) 2006-05-09 2006-05-09 Method and materials to control doping profile in integrated circuit substrate material

Publications (1)

Publication Number Publication Date
TW200802696A true TW200802696A (en) 2008-01-01

Family

ID=38685658

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096116067A TW200802696A (en) 2006-05-09 2007-05-07 Method and semiconductor material for forming silicon device

Country Status (3)

Country Link
US (1) US7629649B2 (zh)
TW (1) TW200802696A (zh)
WO (1) WO2007133935A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI419328B (zh) * 2009-06-12 2013-12-11 Ind Tech Res Inst 主動層堆疊結構及其製造方法及其應用

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7629649B2 (en) 2006-05-09 2009-12-08 Atmel Corporation Method and materials to control doping profile in integrated circuit substrate material
US8035196B2 (en) * 2008-04-02 2011-10-11 Zarlink Semiconductor (Us) Inc. Methods of counter-doping collector regions in bipolar transistors
US7955940B2 (en) 2009-09-01 2011-06-07 International Business Machines Corporation Silicon-on-insulator substrate with built-in substrate junction
US8471340B2 (en) 2009-11-30 2013-06-25 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
US8698244B2 (en) * 2009-11-30 2014-04-15 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method
US8618554B2 (en) 2010-11-08 2013-12-31 International Business Machines Corporation Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide
CN106165095B (zh) 2014-02-14 2018-10-19 Abb 瑞士有限公司 具有两个辅助发射极导体路径的半导体模块
WO2016041852A1 (en) * 2014-09-15 2016-03-24 Abb Technology Ag Method for manufacturing a semiconductor device comprising a thin semiconductor wafer
US10446644B2 (en) 2015-06-22 2019-10-15 Globalfoundries Inc. Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008110A (en) * 1994-07-21 1999-12-28 Kabushiki Kaisha Toshiba Semiconductor substrate and method of manufacturing same
US6479373B2 (en) 1997-02-20 2002-11-12 Infineon Technologies Ag Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases
US6229177B1 (en) 1998-03-30 2001-05-08 Advanced Micro Devices, Inc. Semiconductor with laterally non-uniform channel doping profile
US6232636B1 (en) 1998-11-25 2001-05-15 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region
US6362075B1 (en) * 1999-06-30 2002-03-26 Harris Corporation Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide
US6313489B1 (en) 1999-11-16 2001-11-06 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device
US6633066B1 (en) 2000-01-07 2003-10-14 Samsung Electronics Co., Ltd. CMOS integrated circuit devices and substrates having unstrained silicon active layers
US6503783B1 (en) * 2000-08-31 2003-01-07 Micron Technology, Inc. SOI CMOS device with reduced DIBL
JP2002184960A (ja) * 2000-12-18 2002-06-28 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
US6780686B2 (en) 2002-03-21 2004-08-24 Advanced Micro Devices, Inc. Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions
US7629649B2 (en) 2006-05-09 2009-12-08 Atmel Corporation Method and materials to control doping profile in integrated circuit substrate material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI419328B (zh) * 2009-06-12 2013-12-11 Ind Tech Res Inst 主動層堆疊結構及其製造方法及其應用

Also Published As

Publication number Publication date
US20070264795A1 (en) 2007-11-15
US7629649B2 (en) 2009-12-08
WO2007133935A3 (en) 2008-09-18
WO2007133935A2 (en) 2007-11-22

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