TW200741858A - Plasma etching method and computer-readable storage medium - Google Patents

Plasma etching method and computer-readable storage medium

Info

Publication number
TW200741858A
TW200741858A TW096108980A TW96108980A TW200741858A TW 200741858 A TW200741858 A TW 200741858A TW 096108980 A TW096108980 A TW 096108980A TW 96108980 A TW96108980 A TW 96108980A TW 200741858 A TW200741858 A TW 200741858A
Authority
TW
Taiwan
Prior art keywords
computer
plasma
etching method
substrate
plasma etching
Prior art date
Application number
TW096108980A
Other languages
Chinese (zh)
Other versions
TWI405259B (en
Inventor
Ryoichi Yoshida
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200741858A publication Critical patent/TW200741858A/en
Application granted granted Critical
Publication of TWI405259B publication Critical patent/TWI405259B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A plasma etching method for forming a trench on a substrate or on a film formed on the substrate, includes an substrate arranging step of arranging the substrate on which the trench is to be formed in a processing chamber having therein a first and a second electrode disposed to face each other vertically; a processing gas introducing step of introducing a processing gas for etching into the processing chamber; a plasma generating step of generating a plasma by applying a high frequency electric power to either of the first and the second electrode; and a DC voltage applying step of applying a DC voltage to said either of the electrodes. Further, a computer-readable storage medium stores therein a computer-executable control program, wherein, when the control program is being executed, a computer is made to control a plasma processing apparatus to perform the plasma etching method.
TW096108980A 2006-03-16 2007-03-15 A plasma etch method and a computer readable memory medium TWI405259B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006072826A JP4754374B2 (en) 2006-03-16 2006-03-16 Plasma etching method and computer-readable storage medium

Publications (2)

Publication Number Publication Date
TW200741858A true TW200741858A (en) 2007-11-01
TWI405259B TWI405259B (en) 2013-08-11

Family

ID=38594840

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096108980A TWI405259B (en) 2006-03-16 2007-03-15 A plasma etch method and a computer readable memory medium

Country Status (4)

Country Link
JP (1) JP4754374B2 (en)
KR (1) KR100876010B1 (en)
CN (1) CN101038861A (en)
TW (1) TWI405259B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI478231B (en) * 2007-12-27 2015-03-21 Tokyo Electron Ltd Plasma etching method, plasma etching device, control program and computer memory media
TWI496210B (en) * 2008-02-07 2015-08-11 Tokyo Electron Ltd A plasma etch method and a plasma etch apparatus and a memory medium
TWI630848B (en) * 2010-08-11 2018-07-21 東京威力科創股份有限公司 Plasma processing device and plasma control method

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5192209B2 (en) 2006-10-06 2013-05-08 東京エレクトロン株式会社 Plasma etching apparatus, plasma etching method, and computer-readable storage medium
KR101240818B1 (en) * 2007-09-28 2013-03-11 도쿄엘렉트론가부시키가이샤 Method of plasma treatment and plasma treatment apparatus
JP5371238B2 (en) * 2007-12-20 2013-12-18 東京エレクトロン株式会社 Plasma processing apparatus and plasma processing method
JP5319150B2 (en) 2008-03-31 2013-10-16 東京エレクトロン株式会社 Plasma processing apparatus, plasma processing method, and computer-readable storage medium
JP5213496B2 (en) * 2008-03-31 2013-06-19 東京エレクトロン株式会社 Plasma etching method and computer-readable storage medium
KR101124770B1 (en) * 2008-03-31 2012-03-23 도쿄엘렉트론가부시키가이샤 Plasma processing apparatus, plasma processing method and computer readable storage medium
JP2011176161A (en) * 2010-02-25 2011-09-08 Hitachi High-Technologies Corp Plasma processing apparatus and processing method
KR101913891B1 (en) 2011-09-27 2018-10-31 도쿄엘렉트론가부시키가이샤 Plasma etching method and method for manufacturing semiconductor device
WO2014049915A1 (en) * 2012-09-26 2014-04-03 シャープ株式会社 Substrate treatment device, substrate treatment method, and production method for semiconductor device
CN111304655A (en) * 2020-03-16 2020-06-19 福建华佳彩有限公司 Etching equipment

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02109328A (en) * 1988-10-18 1990-04-23 Nec Corp Dry etching method and device therefor
JP4831853B2 (en) * 1999-05-11 2011-12-07 東京エレクトロン株式会社 Capacitively coupled parallel plate plasma etching apparatus and plasma etching method using the same
JP4681217B2 (en) * 2003-08-28 2011-05-11 株式会社アルバック Interlayer dielectric film dry etching method
US7740737B2 (en) * 2004-06-21 2010-06-22 Tokyo Electron Limited Plasma processing apparatus and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI478231B (en) * 2007-12-27 2015-03-21 Tokyo Electron Ltd Plasma etching method, plasma etching device, control program and computer memory media
TWI496210B (en) * 2008-02-07 2015-08-11 Tokyo Electron Ltd A plasma etch method and a plasma etch apparatus and a memory medium
TWI630848B (en) * 2010-08-11 2018-07-21 東京威力科創股份有限公司 Plasma processing device and plasma control method

Also Published As

Publication number Publication date
TWI405259B (en) 2013-08-11
CN101038861A (en) 2007-09-19
KR20070094476A (en) 2007-09-20
KR100876010B1 (en) 2008-12-24
JP4754374B2 (en) 2011-08-24
JP2007250874A (en) 2007-09-27

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees