TW200741481A - Data transfer in multiprocessor system - Google Patents

Data transfer in multiprocessor system

Info

Publication number
TW200741481A
TW200741481A TW096100320A TW96100320A TW200741481A TW 200741481 A TW200741481 A TW 200741481A TW 096100320 A TW096100320 A TW 096100320A TW 96100320 A TW96100320 A TW 96100320A TW 200741481 A TW200741481 A TW 200741481A
Authority
TW
Taiwan
Prior art keywords
type
multiprocessor system
slave
data transfer
arbitrator
Prior art date
Application number
TW096100320A
Other languages
English (en)
Inventor
Nak-Hee Seong
Young-Duk Kim
Jae-Hong Park
Young-Jun Kwon
Jong-Min Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200741481A publication Critical patent/TW200741481A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
    • E04G11/00—Forms, shutterings, or falsework for making walls, floors, ceilings, or roofs
    • E04G11/36—Forms, shutterings, or falsework for making walls, floors, ceilings, or roofs for floors, ceilings, or roofs of plane or curved surfaces end formpanels for floor shutterings
    • E04G11/48—Supporting structures for shutterings or frames for floors or roofs
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
    • E04G11/00—Forms, shutterings, or falsework for making walls, floors, ceilings, or roofs
    • E04G11/36—Forms, shutterings, or falsework for making walls, floors, ceilings, or roofs for floors, ceilings, or roofs of plane or curved surfaces end formpanels for floor shutterings
    • E04G11/40—Forms, shutterings, or falsework for making walls, floors, ceilings, or roofs for floors, ceilings, or roofs of plane or curved surfaces end formpanels for floor shutterings for coffered or ribbed ceilings
    • E04G11/46—Forms, shutterings, or falsework for making walls, floors, ceilings, or roofs for floors, ceilings, or roofs of plane or curved surfaces end formpanels for floor shutterings for coffered or ribbed ceilings of hat-like or trough-like shape encasing a rib or the section between two ribs or encasing one rib and its adjacent flat floor or ceiling section

Landscapes

  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Theoretical Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Civil Engineering (AREA)
  • Structural Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
TW096100320A 2006-01-04 2007-01-04 Data transfer in multiprocessor system TW200741481A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060001041A KR100706801B1 (ko) 2006-01-04 2006-01-04 멀티 프로세서 시스템 및 그것의 데이터 전송 방법
US11/480,707 US20070156937A1 (en) 2006-01-04 2006-07-03 Data transfer in multiprocessor system

Publications (1)

Publication Number Publication Date
TW200741481A true TW200741481A (en) 2007-11-01

Family

ID=38161681

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096100320A TW200741481A (en) 2006-01-04 2007-01-04 Data transfer in multiprocessor system

Country Status (4)

Country Link
US (1) US20070156937A1 (zh)
KR (1) KR100706801B1 (zh)
CN (1) CN1996276A (zh)
TW (1) TW200741481A (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4233373B2 (ja) * 2003-04-14 2009-03-04 株式会社ルネサステクノロジ データ転送制御装置
CN101464845B (zh) * 2009-01-09 2012-09-05 威盛电子股份有限公司 用于总线系统的预取装置、预取系统及预取数据方法
JP5267218B2 (ja) * 2009-03-05 2013-08-21 富士通株式会社 クロック供給方法及び情報処理装置
CN101533381B (zh) * 2009-03-27 2015-11-25 北京中星微电子有限公司 一种类ahb总线及其实现方法
JP2011150397A (ja) * 2010-01-19 2011-08-04 Panasonic Corp バス調停装置
JP2013122713A (ja) * 2011-12-12 2013-06-20 Toshiba Corp 半導体装置
KR101468677B1 (ko) * 2013-12-27 2014-12-05 (주)실리콘화일 아비터를 이용한 메모리의 억세스 제어회로
CN114168522B (zh) * 2022-02-14 2022-04-29 北京微核芯科技有限公司 一种数据传输方法、装置及传输部件

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KR0181471B1 (ko) * 1990-07-27 1999-05-15 윌리암 피.브레이든 컴퓨터 데이타 경로배정 시스템
US5717875A (en) * 1995-09-22 1998-02-10 Vlsi Technology, Inc. Computing device having semi-dedicated high speed bus
JPH1078934A (ja) * 1996-07-01 1998-03-24 Sun Microsyst Inc パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム
US5911053A (en) * 1996-09-30 1999-06-08 Intel Corporation Method and apparatus for changing data transfer widths in a computer system
US6014720A (en) * 1997-05-05 2000-01-11 Intel Corporation Dynamically sizing a bus transaction for dual bus size interoperability based on bus transaction signals
US6556589B2 (en) * 1998-04-17 2003-04-29 Advanced Micro Devices, Inc. Network transceiver for steering network data to selected paths based on determined link speeds
US6430637B1 (en) * 1999-02-04 2002-08-06 Micron Technology, Inc. Method for multiplexing bus interfaces on a computer expansion bus
US6587905B1 (en) * 2000-06-29 2003-07-01 International Business Machines Corporation Dynamic data bus allocation
KR20030056567A (ko) * 2001-12-28 2003-07-04 한국전자통신연구원 다중 프로세서와 주변 블록을 갖는 시스템 칩을 위한 버스구조
JP4198376B2 (ja) * 2002-04-02 2008-12-17 Ｎｅｃエレクトロニクス株式会社 バスシステム及びバスシステムを含む情報処理システム
KR100626362B1 (ko) * 2003-05-23 2006-09-20 삼성전자주식회사 고속 대역폭의 시스템 버스를 중재하기 위한 중재기, 중재기를 포함하는 버스 시스템 및 버스 중재 방법
JP4489454B2 (ja) * 2004-02-16 2010-06-23 富士通マイクロエレクトロニクス株式会社 半導体集積回路
US8478921B2 (en) * 2004-03-31 2013-07-02 Silicon Laboratories, Inc. Communication apparatus implementing time domain isolation with restricted bus access
JP4260720B2 (ja) * 2004-10-27 2009-04-30 日本テキサス・インスツルメンツ株式会社 バス制御装置
US7219177B2 (en) * 2004-11-23 2007-05-15 Winbond Electronics Corp. Method and apparatus for connecting buses with different clock frequencies by masking or lengthening a clock cycle of a request signal in accordance with the different clock frequencies of the buses
US7174411B1 (en) * 2004-12-02 2007-02-06 Pericom Semiconductor Corp. Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host

Also Published As

Publication number Publication date
US20070156937A1 (en) 2007-07-05
CN1996276A (zh) 2007-07-11
KR100706801B1 (ko) 2007-04-12

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