TW200739596A - Memory controller for supporting double data rate memory and related method - Google Patents

Memory controller for supporting double data rate memory and related method

Info

Publication number
TW200739596A
TW200739596A TW095127525A TW95127525A TW200739596A TW 200739596 A TW200739596 A TW 200739596A TW 095127525 A TW095127525 A TW 095127525A TW 95127525 A TW95127525 A TW 95127525A TW 200739596 A TW200739596 A TW 200739596A
Authority
TW
Taiwan
Prior art keywords
data
memory
data rate
double data
related method
Prior art date
Application number
TW095127525A
Other languages
English (en)
Inventor
Hsiang-I Huang
Ta-Lun Huang
Original Assignee
Mediatek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mediatek Inc filed Critical Mediatek Inc
Publication of TW200739596A publication Critical patent/TW200739596A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)
TW095127525A 2006-04-13 2006-07-27 Memory controller for supporting double data rate memory and related method TW200739596A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/279,750 US20070242530A1 (en) 2006-04-13 2006-04-13 Memory controller for supporting double data rate memory and related method

Publications (1)

Publication Number Publication Date
TW200739596A true TW200739596A (en) 2007-10-16

Family

ID=38604702

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095127525A TW200739596A (en) 2006-04-13 2006-07-27 Memory controller for supporting double data rate memory and related method

Country Status (3)

Country Link
US (1) US20070242530A1 (zh)
CN (1) CN101055756A (zh)
TW (1) TW200739596A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI654523B (zh) 2016-06-28 2019-03-21 聯發科技股份有限公司 積體電路晶片、電子裝置與記憶體存取方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9009362B2 (en) * 2012-12-20 2015-04-14 Intel Corporation Variable-width command/address bus

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450208A (en) * 1992-11-30 1995-09-12 Matsushita Electric Industrial Co., Ltd. Image processing method and image processing apparatus
US5659635A (en) * 1994-04-26 1997-08-19 Konica Corporation Image processing apparatus for compressing and decompressing image data
JP3665423B2 (ja) * 1995-08-28 2005-06-29 セイコーエプソン株式会社 高速フーリエ変換演算器及び高速フーリエ変換演算装置
JP3359270B2 (ja) * 1997-10-24 2002-12-24 キヤノン株式会社 メモリー制御装置と液晶表示装置
US6233294B1 (en) * 1999-08-17 2001-05-15 Richard Bowers Method and apparatus for accomplishing high bandwidth serial communication between semiconductor devices
JP3937086B2 (ja) * 2000-12-28 2007-06-27 富士ゼロックス株式会社 データ列変換回路及びそれを用いたプリンタ
TW507128B (en) * 2001-07-12 2002-10-21 Via Tech Inc Data memory controller supporting the data bus invert
US7319706B2 (en) * 2002-08-12 2008-01-15 Broadcom Corporation Symmetrical clock distribution in multi-stage high speed data conversion circuits
US6779069B1 (en) * 2002-09-04 2004-08-17 Nvidia Corporation Computer system with source-synchronous digital link
US7064685B1 (en) * 2004-10-20 2006-06-20 Altera Corporation Data converter with reduced component count for padded-protocol interface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI654523B (zh) 2016-06-28 2019-03-21 聯發科技股份有限公司 積體電路晶片、電子裝置與記憶體存取方法
US10241942B2 (en) 2016-06-28 2019-03-26 Mediatek Inc. Method and apparatus for memory access

Also Published As

Publication number Publication date
CN101055756A (zh) 2007-10-17
US20070242530A1 (en) 2007-10-18

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