TW200725830A - Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates - Google Patents

Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates

Info

Publication number
TW200725830A
TW200725830A TW095147535A TW95147535A TW200725830A TW 200725830 A TW200725830 A TW 200725830A TW 095147535 A TW095147535 A TW 095147535A TW 95147535 A TW95147535 A TW 95147535A TW 200725830 A TW200725830 A TW 200725830A
Authority
TW
Taiwan
Prior art keywords
bottom packaging
packaging modules
prearranged
electrical contacts
modules
Prior art date
Application number
TW095147535A
Other languages
Chinese (zh)
Other versions
TWI459512B (en
Inventor
Ming Sun
Yueh-Se Ho
Original Assignee
Alpha & Omega Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/318,300 external-priority patent/US7829989B2/en
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW200725830A publication Critical patent/TW200725830A/en
Application granted granted Critical
Publication of TWI459512B publication Critical patent/TWI459512B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

An electronic package for containing at least a top packaging modules vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts. The laminated board of the bottom packaging modules further has a thermal expansion coefficient substantially the same as a printed circuit board (PCB) whereby a surface mount onto the PCB is less impacted by a temperature change.
TW095147535A 2005-12-22 2006-12-18 Vertically packaged mosfet and ic power devices as integrated module using 3d interconnected laminates TWI459512B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/318,300 US7829989B2 (en) 2005-09-07 2005-12-22 Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside

Publications (2)

Publication Number Publication Date
TW200725830A true TW200725830A (en) 2007-07-01
TWI459512B TWI459512B (en) 2014-11-01

Family

ID=38704084

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095147535A TWI459512B (en) 2005-12-22 2006-12-18 Vertically packaged mosfet and ic power devices as integrated module using 3d interconnected laminates

Country Status (2)

Country Link
CN (1) CN101005062B (en)
TW (1) TWI459512B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI721995B (en) * 2014-12-29 2021-03-21 新加坡商星科金朋有限公司 Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5473388B2 (en) * 2009-04-24 2014-04-16 ローム株式会社 Semiconductor device and manufacturing method of semiconductor device
WO2015142321A1 (en) * 2014-03-18 2015-09-24 Hewlett Packard Development Company, L.P. Secure element
US9960146B1 (en) * 2017-03-19 2018-05-01 Nanya Technology Corporation Semiconductor structure and method for forming the same
CN112640110A (en) * 2018-08-31 2021-04-09 富士胶片株式会社 Imaging unit and imaging device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3917946B2 (en) * 2003-03-11 2007-05-23 富士通株式会社 Multilayer semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI721995B (en) * 2014-12-29 2021-03-21 新加坡商星科金朋有限公司 Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof

Also Published As

Publication number Publication date
CN101005062A (en) 2007-07-25
CN101005062B (en) 2011-12-21
TWI459512B (en) 2014-11-01

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