KR101364088B1 - Interposer, and method for manufacturing the same - Google Patents

Interposer, and method for manufacturing the same Download PDF

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KR101364088B1
KR101364088B1 KR1020120101034A KR20120101034A KR101364088B1 KR 101364088 B1 KR101364088 B1 KR 101364088B1 KR 1020120101034 A KR1020120101034 A KR 1020120101034A KR 20120101034 A KR20120101034 A KR 20120101034A KR 101364088 B1 KR101364088 B1 KR 101364088B1
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integrated circuit
semiconductor substrate
interposer
thin film
hole
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Korean (ko)
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박종철
김준철
김동수
박세훈
유종인
육종민
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전자부품연구원
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/46—Manufacturing multilayer circuits
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    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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Abstract

A method for manufacturing an interposer includes a step of forming one or more through-vias on a semiconductor substrate; a step of electrically connecting one or more through-vias to a thin-film circuit formed on one side of the semiconductor substrate; and a step of electrically connecting one or more through-vias to an integrated circuit chip formed on the other side of the semiconductor substrate.

Description

인터포저, 그리고 이의 제조 방법{INTERPOSER, AND METHOD FOR MANUFACTURING THE SAME}INTERPOSER, AND METHOD FOR MANUFACTURING THE SAME}

본 발명은 인터포저, 그리고 이의 제조 방법에 관한 것이다.The present invention relates to an interposer and a method of manufacturing the same.

고집적 모듈(Multi-chip Module, MCM)은 주로 인쇄회로기판(Printed Circuit Board, PCB) 또는 저온 동시 소성 세라믹(Low Temperature Co-fired Ceramic, LTCC)와 같은 적층(laminate) 기판을 이용한다. 그러나 PCB와 LTCC는 미세 배선 공정이 어렵고, 박막 수동소자의 집적이 불가능해 고집적 초소형 모듈을 구현하는데 기술적 한계가 있다. 또한 고집적 소형화를 위해 사용되는 SoC(System on Chip)와 MMIC(Monolithic Microwave Integrated Circuit) 기술은 고집적 구현은 가능하지만, 가격이 비싸고 모든 시스템과 소자를 구현하는데 어려움이 있다.Multi-chip modules (MCMs) mainly use laminated substrates such as printed circuit boards (PCBs) or low temperature co-fired ceramics (LTCC). However, the PCB and LTCC have a technical limitation in implementing a highly integrated miniature module because the micro wiring process is difficult and the thin film passive device cannot be integrated. In addition, the SoC (System on Chip) and MMIC (Monolithic Microwave Integrated Circuit) technologies used for high-density miniaturization are highly integrated, but expensive and difficult to implement all systems and devices.

최근에는 실리콘 인터포저(silicon interposer) 기술을 활용한 연구가 진행되고 있다. 그러나 지금까지의 인터포저는 수동 소자를 실리콘 기판 위에 실장(mounting)하기 때문에, 모듈의 두께를 줄이는데 한계가 있다.Recently, researches using silicon interposer technology have been conducted. However, interposers up to now have a limitation in reducing the thickness of the module because the passive element is mounted on a silicon substrate.

본 발명이 해결하고자 하는 과제는 기판의 일면에 박막 회로를 형성하고, 다른 일면에 형성된 구멍(cavity)에 집적회로 칩을 삽입하는 인터포저, 그리고 이의 제조 방법을 제공하는 것이다.SUMMARY An object of the present invention is to provide an interposer for forming a thin film circuit on one surface of a substrate, inserting an integrated circuit chip into a cavity formed on the other surface, and a manufacturing method thereof.

본 발명의 한 실시예에 따른 인터포저 제조 방법으로서, 반도체 기판에 적어도 하나의 관통 비아를 형성하는 단계, 상기 적어도 하나의 관통 비아와 상기 반도체 기판의 한 면에 형성된 박막 회로를 전기적으로 연결하는 단계, 그리고 상기 적어도 하나의 관통 비아와 상기 반도체 기판의 다른 한 면에 형성된 집적회로 칩을 전기적으로 연결하는 단계를 포함한다.An interposer manufacturing method according to an embodiment of the present invention, comprising: forming at least one through via on a semiconductor substrate, and electrically connecting the at least one through via and a thin film circuit formed on one surface of the semiconductor substrate. And electrically connecting the at least one through via and an integrated circuit chip formed on the other side of the semiconductor substrate.

상기 적어도 하나의 관통 비아를 형성하는 단계는 상기 집적회로 칩 삽입을 위한 구멍의 깊이, 그리고 상기 집적회로 칩 삽입을 위한 구멍에서의 기판 두께를 기초로 상기 관통 비아의 길이를 결정할 수 있다.The forming of the at least one through via may determine the length of the through via based on a depth of a hole for inserting the integrated circuit chip and a thickness of a substrate in the hole for inserting the integrated circuit chip.

상기 집적회로 칩을 전기적으로 연결하는 단계는 상기 반도체 기판의 다른 한 면에 적어도 하나의 집적회로 구멍을 형성하는 단계, 상기 적어도 하나의 집적회로 구멍에 집적회로 칩을 삽입하는 단계, 그리고 상기 적어도 하나의 관통 비아와 상기 집적회로 칩을 전기적으로 연결하는 단계를 포함할 수 있다.Electrically connecting the integrated circuit chip comprises forming at least one integrated circuit hole in the other side of the semiconductor substrate, inserting an integrated circuit chip in the at least one integrated circuit hole, and the at least one And electrically connecting the through via of the integrated circuit chip.

상기 집적회로 구멍을 형성하는 단계는 상기 관통 비아가 드러날 때까지 상기 반도체 기판의 다른 한 면을 깎는 단계, 그리고 상기 관통 비아가 노출된 상기 반도체 기판의 다른 한 면에서 집적회로 칩이 삽입될 구멍을 형성하는 단계를 포함할 수 있다.The forming of the integrated circuit hole may include shaving the other side of the semiconductor substrate until the through via is exposed, and forming a hole into which the integrated circuit chip is to be inserted in the other side of the semiconductor substrate where the through via is exposed. It may comprise the step of forming.

본 발명의 다른 실시예에 따른 인터포저로서, 적어도 하나의 관통 비아가 형성된 반도체 기판, 상기 반도체 기판의 한 면에 형성된 제1 회로, 그리고 상기 반도체 기판의 다른 한 면에 형성된 제2 회로를 포함하고, 상기 제1 회로와 상기 제2 회로는 상기 적어도 하나의 관통 비아와 전기적으로 연결되고, 상기 제1 회로와 상기 제2 회로 중 적어도 하나는 적어도 하나의 집적회로 칩을 포함한다.An interposer according to another embodiment of the present invention, comprising: a semiconductor substrate having at least one through via formed therein, a first circuit formed on one side of the semiconductor substrate, and a second circuit formed on the other side of the semiconductor substrate; The first circuit and the second circuit are electrically connected to the at least one through via, and at least one of the first circuit and the second circuit includes at least one integrated circuit chip.

상기 집적회로 칩은 상기 반도체 기판에 형성된 구멍에 삽입될 수 있다.The integrated circuit chip may be inserted into a hole formed in the semiconductor substrate.

본 발명의 실시예에 따르면 인터포저 내부에 집적회로 칩이 삽입되므로, 집적회로 칩을 표면에 실장하는 다른 인터포저에 비해 현저히 두께를 줄일 수 있다. 본 발명의 실시예에 따르면 반도체 기판의 양면에 박막 회로 또는 집적회로가 형성되므로, 반도체 기판의 한면에만 박막 회로 또는 집적회로를 형성하는 다른 인터포저에 비해 우수한 집적도를 갖는다. 따라서, 본 발명의 실시예에 따르면 지금까지의 인터포저에 비해 고집적 초박형 반도체 패키지를 구현할 수 있다. According to the embodiment of the present invention, since the integrated circuit chip is inserted into the interposer, the thickness of the integrated circuit chip may be significantly reduced compared to other interposers for mounting the integrated circuit chip on the surface. According to the exemplary embodiment of the present invention, since a thin film circuit or an integrated circuit is formed on both sides of the semiconductor substrate, it has an excellent degree of integration as compared to other interposers forming the thin film circuit or the integrated circuit only on one surface of the semiconductor substrate. Therefore, according to the exemplary embodiment of the present invention, a highly integrated ultra-thin semiconductor package can be implemented as compared to the interposers.

본 발명의 실시예에 따르면 다양한 이종 소자 집적회로 칩을 이용한 초박형 초소형 모듈 설계가 가능하다. 또한, 본 발명의 실시예에 따르면 관통 비아를 이용하여 플립칩(flip-chip) 적층이 가능한 반도체 패키지를 구현할 수 있다. According to an embodiment of the present invention, it is possible to design an ultra-thin micro module using various heterogeneous integrated circuit chips. In addition, according to an exemplary embodiment of the present invention, a semiconductor package capable of flip-chip stacking may be implemented using through vias.

도 1은 본 발명의 한 실시예에 따른 인터포저의 단면도이다.
도 2부터 도 11은 본 발명의 한 실시예에 따른 인터포저 제조 방법을 나타내는 단면도이다.
도 12는 본 발명의 다른 실시예에 따른 인터포저의 단면도이다.
도 13은 본 발명의 한 실시예에 따른 적층 인터포저의 도면이다.
도 14는 본 발명의 한 실시예에 따른 인터포저 제작 방법의 흐름도이다.
도 15는 본 발명의 다른 실시예에 따른 인터포저 제작 방법의 흐름도이다.1 is a cross-sectional view of an interposer according to an embodiment of the present invention.
2 to 11 are cross-sectional views showing a method for manufacturing an interposer according to an embodiment of the present invention.
12 is a cross-sectional view of an interposer according to another embodiment of the present invention.
13 is a diagram of a stacked interposer according to one embodiment of the present invention.
14 is a flowchart of an interposer fabrication method according to an embodiment of the present invention.
15 is a flowchart of a method for manufacturing an interposer according to another embodiment of the present invention.

아래에서는 첨부한 도면을 참고로 하여 본 발명의 실시예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다. 그리고 도면에서 본 발명을 명확하게 설명하기 위해서 설명과 관계없는 부분은 생략하였으며, 명세서 전체를 통하여 유사한 부분에 대해서는 유사한 도면 부호를 붙였다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

명세서 전체에서, 어떤 부분이 어떤 구성요소를 "포함"한다고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성요소를 더 포함할 수 있는 것을 의미한다.Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

이제 도면을 참고하여 본 발명의 실시예에 따른 인터포저, 그리고 이의 제조 방법에 대해 설명한다.Hereinafter, an interposer according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described with reference to the accompanying drawings.

도 1은 본 발명의 한 실시예에 따른 인터포저의 단면도이다.1 is a cross-sectional view of an interposer according to an embodiment of the present invention.

도 1을 참고하면, 인터포저(100)는 반도체 기판(wafer)(110)의 한 면, 예를 들면 윗면에 적어도 하나의 박막 회로(120, 130, 140)를 포함하고, 반도체 기판(110)의 다른 면, 예를 들면 아랫면에 적어도 하나의 집적회로(Integrated Circuit, IC) 칩(200a, 200b)을 포함한다. 이때, 집적회로 칩(200a, 200b)은 반도체 기판(110)의 아랫면에 형성된 구멍(cavity)에 삽입(embedded)된다. Referring to FIG. 1, the interposer 100 includes at least one thin film circuit 120, 130, and 140 on one side, for example, a top surface of the semiconductor substrate 110, and the semiconductor substrate 110. At least one integrated circuit (IC) chip 200a, 200b on the other side of the substrate, for example, the bottom surface thereof. In this case, the integrated circuit chips 200a and 200b are embedded in a cavity formed in the bottom surface of the semiconductor substrate 110.

박막 회로(120, 130, 140)와 집적회로 칩(200a, 200b)은 배선 공정을 통해 반도체 기판(110)을 관통하는 관통 비아(Via)(300a, 300b)에 연결된다. 관통 비아(300a, 300b)는 비아 퍼스트(Via First) 공정 또는 비아 라스트(Via Last) 공정으로 형성될 수 있다.The thin film circuits 120, 130, and 140 and the integrated circuit chips 200a and 200b are connected to through vias 300a and 300b that penetrate the semiconductor substrate 110 through a wiring process. The through vias 300a and 300b may be formed by a via first process or a via last process.

다음에서 인터포저(100)의 제조 방법을 예시적으로 설명한다.Next, a method of manufacturing the interposer 100 will be described.

도 2부터 도 11은 본 발명의 한 실시예에 따른 인터포저 제조 방법을 나타내는 단면도이다.2 to 11 are cross-sectional views showing a method for manufacturing an interposer according to an embodiment of the present invention.

먼저, 도 2를 참고하면, 반도체 기판(110)의 윗면에 적어도 하나의 박막 회로(120, 130, 140)를 형성한다. 반도체 기판(110)은 실리콘(silicon) 기판이나 유리(glass) 기판일 수 있다. 박막 회로는 반도체 공정을 통해 기판에 구현 가능한 전기적 기능을 하는 소자 및 집적 회로를 의미한다. 예를 들면, 박막 회로는 박막 레지스터(resistor), 박막 캐패시터(capacitor), 박막 인덕터(inductor)와 같은 집적 수동 소자(integrated passive device, IPD)일 수 있다. 또한 박막 회로는 트랜지스터(transistor)(미도시)를 포함할 수 있다. 예를 들면, 박막 회로(120)는 박막 레지스터이고, 박막 회로(130)는 박막 캐패시터이며, 박막 회로(140)은 나선형 인덕터일 수 있다.First, referring to FIG. 2, at least one thin film circuit 120, 130, 140 is formed on an upper surface of the semiconductor substrate 110. The semiconductor substrate 110 may be a silicon substrate or a glass substrate. Thin film circuits refer to devices and integrated circuits that have electrical functions that can be implemented on a substrate through a semiconductor process. For example, the thin film circuit may be an integrated passive device (IPD) such as a thin film resistor, thin film capacitor, thin film inductor. Thin film circuits may also include transistors (not shown). For example, the thin film circuit 120 may be a thin film resistor, the thin film circuit 130 may be a thin film capacitor, and the thin film circuit 140 may be a spiral inductor.

반도체 기판(110)의 윗면에서 관통 비아(Through Silicon Via, TSV/Through Glass Via, TGV)(300a, 300b)를 위한 일정 깊이의 구멍(111a, 111b)을 만든다. 구멍은 플라즈마 에칭 또는 레이저 식각으로 형성될 수 있다.Holes 111a and 111b of a predetermined depth are formed on the top surface of the semiconductor substrate 110 for through vias (TSV / Through Glass Via, TGV) 300a and 300b. The hole may be formed by plasma etching or laser etching.

이때, 구멍(111a, 111b)의 깊이, 즉 관통 비아(300a, 300b)의 길이는 집적회로 칩(200a, 200b)이 삽입될 구멍의 깊이, 그리고 집적회로 칩(200a, 200b)이 삽입될 구멍에서의 기판 두께를 고려하여 결정된다. 여기서, 기판 두께는 반도체 기판(110)의 윗면에서 집적회로 칩(200a, 200b)이 삽입될 구멍 바닥까지의 길이이다.In this case, the depths of the holes 111a and 111b, that is, the lengths of the through vias 300a and 300b are the depths of the holes into which the integrated circuit chips 200a and 200b are to be inserted, and the holes into which the integrated circuit chips 200a and 200b are to be inserted. It is determined in consideration of the substrate thickness at. Here, the substrate thickness is the length from the top surface of the semiconductor substrate 110 to the bottom of the hole into which the integrated circuit chips 200a and 200b are to be inserted.

도 3을 참고하면, 박막 회로(120-140)와 구멍(111a, 111b)이 형성된 반도체 기판(110)의 윗면을 유기(organic) 물질로 덮는다. 유기 물질은 절연층인 유기물질층(160)을 형성한다.Referring to FIG. 3, an upper surface of the semiconductor substrate 110 on which the thin film circuits 120-140 and the holes 111a and 111b are formed is covered with an organic material. The organic material forms the organic material layer 160 which is an insulating layer.

유기 물질로 채워진 구멍(111a, 111b)보다 작은 크기의 비아 구멍(111c, 111d)을 형성한다. Via holes 111c and 111d having a smaller size than the holes 111a and 111b filled with the organic material are formed.

유기물질층(160)에, 박막 회로(120-140) 각각과 관통 비아(300a, 300b)를 연결하기 위한 전극 구멍(111e, 111f, 111g, 111h, 111i, 111j)을 형성한다.In the organic material layer 160, electrode holes 111e, 111f, 111g, 111h, 111i, and 111j for connecting each of the thin film circuits 120-140 and the through vias 300a and 300b are formed.

도 4를 참고하면, 비아 구멍(111c-111d)을 금속으로 채워 관통 비아(300a, 300b)를 형성한다. 전극 구멍(111e-111j)을 금속으로 채워 전극 접촉 플러그(161e-161j)를 형성한다.Referring to FIG. 4, through vias 300a and 300b are formed by filling the via holes 111c to 111d with metal. Electrode holes 111e-111j are filled with metal to form electrode contact plugs 161e-161j.

도 5를 참고하면, 관통 비아(300a, 300b) 그리고 전극 접촉 플러그(161e-161j)를 연결하는 상부 전극(150)을 형성한다. 이를 통해 관통 비아(300a, 300b)와 박막 회로(120-140)는 전기적으로 연결된다.Referring to FIG. 5, upper electrodes 150 are formed to connect the through vias 300a and 300b and the electrode contact plugs 161e to 161j. Through this, the through vias 300a and 300b and the thin film circuits 120 to 140 are electrically connected to each other.

도 6을 참고하면, 관통 비아(300a, 300b)가 드러날 때까지 반도체 기판(110)의 아랫면을 깎아낸다. Referring to FIG. 6, the bottom surface of the semiconductor substrate 110 is scraped off until the through vias 300a and 300b are exposed.

도 7을 참고하면, 관통 비아(300a, 300b)가 노출된 반도체 기판(110)의 아랫면에 집적회로 칩(200a, 200b)을 삽입하기 위한 집적회로 구멍(210a, 210b)을 형성한다. 집적회로 구멍(210a, 210b)의 깊이는 집적회로 칩의 두께에 따라 달라질 수 있다.Referring to FIG. 7, integrated circuit holes 210a and 210b for inserting integrated circuit chips 200a and 200b are formed in the lower surface of the semiconductor substrate 110 where the through vias 300a and 300b are exposed. The depth of the integrated circuit holes 210a and 210b may vary depending on the thickness of the integrated circuit chip.

이때, 관통 비아(300a, 300b)의 길이는 반도체 기판(110)에서 집적회로 구멍(210a, 210b)을 충분히 만들 수 있도록 집적회로 구멍(210a, 210b)의 깊이에 따라 달라질 수 있다. In this case, the lengths of the through vias 300a and 300b may vary depending on the depths of the integrated circuit holes 210a and 210b to sufficiently make the integrated circuit holes 210a and 210b in the semiconductor substrate 110.

도 8을 참고하면, 집적회로 구멍(210a, 210b)에 집적회로 칩(200a, 200b)을 삽입한다. 이때, 집적회로 칩(200a, 200b)을 고정하기 위한 에폭시(epoxy)(220a, 220b)를 사용할 수 있다. 이때, 에폭시(220a, 220b)는 전도성 에폭시 또는 비전도성 에폭시일 수 있다.Referring to FIG. 8, the integrated circuit chips 200a and 200b are inserted into the integrated circuit holes 210a and 210b. In this case, epoxy 220a and 220b for fixing the integrated circuit chips 200a and 200b may be used. At this time, the epoxy (220a, 220b) may be a conductive epoxy or a non-conductive epoxy.

도 9를 참고하면, 집적회로 칩(200a, 200b)이 삽입된 반도체 기판(110)의 아랫면을 유기 물질로 덮는다. 유기 물질은 집적회로 칩(200a, 200b)과 반도체 기판(110)의 틈을 메운다. 유기 물질은 유기물질층(230)을 형성한다. Referring to FIG. 9, the bottom surface of the semiconductor substrate 110 into which the integrated circuit chips 200a and 200b are inserted is covered with an organic material. The organic material fills the gap between the integrated circuit chips 200a and 200b and the semiconductor substrate 110. The organic material forms the organic material layer 230.

이때, 유기 적층(organic lamination) 공정으로 아랫면과 함께 윗면도 유기 물질을 덮을 수 있다. 윗면의 유기 물질은 유기물질층(170)을 형성한다.In this case, the upper surface may also cover the organic material along with the lower surface by an organic lamination process. The organic material on the top surface forms the organic material layer 170.

도 10을 참고하면, 유기물질층(230)에 집적회로 칩(200a, 200b)과 관통 비아(300a, 300b)를 연결하기 위한 구멍들, 예를 들면 전극 구멍(240a, 240b, 240c, 240d, 240e, 240f)을 형성한다. Referring to FIG. 10, holes for connecting the integrated circuit chips 200a and 200b and the through vias 300a and 300b to the organic material layer 230, for example, electrode holes 240a, 240b, 240c, 240d, 240e, 240f) are formed.

도 11을 참고하면, 전극 구멍(240a-240f)을 금속으로 채우고 하부 전극(250)을 연결한다. 이를 통해, 관통 비아(300a, 300b)와 집적회로 칩(200a, 200b)은 전기적으로 연결된다.Referring to FIG. 11, the electrode holes 240a-240f are filled with metal and the lower electrode 250 is connected. Through this, the through vias 300a and 300b and the integrated circuit chips 200a and 200b are electrically connected to each other.

상부 전극(150)과 하부 전극(250) 중 적어도 하나에 범프(260)가 형성될 수 있다. 범프(260)는 플립 칩(Filp-Chip)을 위한 BGA(ball grid array) 구조로 제작될 수 있다. 인터포저(100)는 범프(260)를 통해 다른 인터포저 또는 반도체 회로와 전기적으로 연결된다.Bumps 260 may be formed on at least one of the upper electrode 150 and the lower electrode 250. The bump 260 may be manufactured in a ball grid array (BGA) structure for flip-chip. Interposer 100 is electrically connected to another interposer or semiconductor circuit through bump 260.

도 12는 본 발명의 다른 실시예에 따른 인터포저의 단면도이다.12 is a cross-sectional view of an interposer according to another embodiment of the present invention.

도 12를 참고하면, 인터포저(100')는 반도체 기판(110)의 양면 각각에 형성된 적어도 하나의 집적회로 칩(200a, 200b, 200c)을 포함할 수 있다. 이때, 집적회로 칩(200a, 200b, 200c) 각각은 반도체 기판(110)의 양면에 형성된 구멍들에 삽입된다. Referring to FIG. 12, the interposer 100 ′ may include at least one integrated circuit chip 200a, 200b, or 200c formed on each of both surfaces of the semiconductor substrate 110. In this case, each of the integrated circuit chips 200a, 200b, and 200c is inserted into holes formed in both surfaces of the semiconductor substrate 110.

인터포저(100')는 반도체 기판(110)의 적어도 한 면, 예를 들면 윗면에 적어도 하나의 박막 회로를 더 포함할 수 있다.The interposer 100 ′ may further include at least one thin film circuit on at least one surface, for example, an upper surface of the semiconductor substrate 110.

집적회로 칩(200a, 200b, 200c)과 박막 회로는 배선 공정을 통해 반도체 기판(110)을 관통하는 관통 비아(300a, 300b)에 연결된다. 관통 비아(300a, 300b)의 길이는 양면 각각에 형성된 집적회로 칩 구멍의 깊이, 그리고 집적회로 칩 구멍에서의 기판 두께를 고려하여 결정된다. 이때, 집적회로 칩 구멍에서의 기판 두께는 양면의 집적회로 칩이 겹치는 경우에는 양면 각각에 형성된 집적회로 칩 구멍 사이의 거리이고, 양면의 집적회로 칩이 겹치지 않는 경우에는 집적회로 칩 구멍 바닥에서의 기판 두께일 수 있다.The integrated circuit chips 200a, 200b and 200c and the thin film circuit are connected to the through vias 300a and 300b penetrating the semiconductor substrate 110 through a wiring process. The length of the through vias 300a and 300b is determined in consideration of the depth of the integrated circuit chip hole formed in each of both surfaces, and the thickness of the substrate in the integrated circuit chip hole. At this time, the substrate thickness in the integrated circuit chip holes is the distance between the integrated circuit chip holes formed on both sides when the integrated circuit chips of both sides overlap, and when the integrated circuit chips of both sides do not overlap, Substrate thickness.

여기서 인터포저(100')는 앞서 설명한 인터포저(100)와 유사한 방법으로 제작될 수 있다.The interposer 100 ′ may be manufactured by a method similar to the interposer 100 described above.

도 13은 본 발명의 한 실시예에 따른 적층 인터포저의 도면이다.13 is a diagram of a stacked interposer according to one embodiment of the present invention.

도 13을 참고하면, 적층 인터포저(400)는 복수의 인터포저, 예를 들면 인터포저(100)가 적층된 3차원 반도체 패키지이다. 복수의 인터포저(100)는 관통 비아(300a, 300b)를 통해 전기적으로 연결된다.Referring to FIG. 13, the stacked interposer 400 is a three-dimensional semiconductor package in which a plurality of interposers, for example, the interposers 100 are stacked. The plurality of interposers 100 are electrically connected through the through vias 300a and 300b.

도 13의 적층 인터포저(400)는 동일한 인터포저(100)를 적층한 것으로 도시하였으나, 각 인터포저는 구조가 상이할 수 있다. 예를 들면, 각 인터포저는 이종의 집적회로 칩이 실장되거나, 크기가 다른 집적회로 칩이 실장될 수 있다. 또는 각 인터포저는 서로 다른 박막 회로가 형성되어 있을 수 있다.Although the stacked interposers 400 of FIG. 13 are illustrated by stacking the same interposers 100, each interposer may have a different structure. For example, each interposer may be mounted with heterogeneous integrated circuit chips or integrated circuit chips of different sizes. Alternatively, each interposer may have a different thin film circuit.

도 14는 본 발명의 한 실시예에 따른 인터포저 제작 방법의 흐름도이다.14 is a flowchart of an interposer fabrication method according to an embodiment of the present invention.

도 14를 참고하면, 반도체 기판(110)에 관통 비아(300a, 300b)를 형성한다(S110). 관통 비아의 깊이는 집적회로 칩 삽입을 위한 집적회로 구멍의 깊이를 기초로 결정되며, 집적회로 구멍의 깊이보다 길다.Referring to FIG. 14, through vias 300a and 300b are formed in the semiconductor substrate 110 (S110). The depth of the through via is determined based on the depth of the integrated circuit hole for insertion of the integrated circuit chip and is longer than the depth of the integrated circuit hole.

관통 비아(300a, 300b)와 반도체 기판(110)의 한 면에 형성된 박막 회로(120-140)를 전기적으로 연결한다(S120).The through vias 300a and 300b are electrically connected to the thin film circuits 120 to 140 formed on one surface of the semiconductor substrate 110 (S120).

반도체 기판(110)의 다른 한 면에 집적회로 칩 삽입을 위한 적어도 하나의 집적회로 구멍(210a, 210b)을 형성한다(S130).At least one integrated circuit hole 210a and 210b for inserting an integrated circuit chip is formed in the other surface of the semiconductor substrate 110 (S130).

적어도 하나의 집적회로 구멍(210a, 210b)에 집적회로 칩(200a, 200b)을 삽입한다(S140).Integrated circuit chips 200a and 200b are inserted into at least one integrated circuit hole 210a and 210b (S140).

관통 비아(300a, 300b)와 집적회로 칩(200a, 200b)을 전기적으로 연결한다(S150).The through vias 300a and 300b are electrically connected to the integrated circuit chips 200a and 200b (S150).

도 15는 본 발명의 다른 실시예에 따른 인터포저 제작 방법의 흐름도이다.15 is a flowchart of a method for manufacturing an interposer according to another embodiment of the present invention.

도 15를 참고하면, 반도체 기판(110)에 관통 비아(300a, 300b)를 형성한다(S210). 관통 비아의 깊이는 반도체 기판(110)의 양 면에 형성된 집적회로 구멍의 깊이를 기초로 결정된다.Referring to FIG. 15, through vias 300a and 300b are formed in the semiconductor substrate 110 (S210). The depth of the through via is determined based on the depth of the integrated circuit holes formed on both sides of the semiconductor substrate 110.

반도체 기판(110)의 한 면에 집적회로 칩 삽입을 위한 적어도 하나의 집적회로 구멍을 형성한다(S220).At least one integrated circuit hole for inserting an integrated circuit chip is formed in one surface of the semiconductor substrate 110 (S220).

반도체 기판(110)의 다른 한 면을 관통 비아(300a, 300b)가 노출될 때까지 깎는다(S230).The other surface of the semiconductor substrate 110 is cut until the through vias 300a and 300b are exposed (S230).

관통 비아(300a, 300b)가 노출된 반도체 기판(110)의 다른 한 면에 집적회로 칩 삽입을 위한 적어도 하나의 집적회로 구멍을 형성한다(S240).At least one integrated circuit hole for inserting an integrated circuit chip is formed in the other surface of the semiconductor substrate 110 where the through vias 300a and 300b are exposed (S240).

반도체 기판(110)의 양 면에 형성된 집적회로 구멍 각각에 집적회로 칩을 삽입한다(S250).Integrated circuit chips are inserted into respective integrated circuit holes formed on both surfaces of the semiconductor substrate 110 (S250).

관통 비아(300a, 300b)와 집적회로 칩을 전기적으로 연결한다(S260). 이때, 반도체 기판(110)의 적어도 한 면에 박막 회로를 더 형성할 수 있다. 그리고 박막 회로는 관통 비아(300a, 300b)와 전기적으로 연결된다.The through vias 300a and 300b are electrically connected to the integrated circuit chip (S260). In this case, a thin film circuit may be further formed on at least one surface of the semiconductor substrate 110. The thin film circuit is electrically connected to the through vias 300a and 300b.

이와 같이, 인터포저(100)는 내부에 집적회로 칩이 삽입되므로, 집적회로 칩을 표면에 실장하는 다른 인터포저에 비해 현저히 두께를 줄일 수 있다. 또한, 인터포저(100)는 반도체 기판(110)의 양면에 박막 회로 또는 집적회로가 형성되므로, 반도체 기판(110)의 한면에만 박막 회로 또는 집적회로를 형성하는 다른 인터포저에 비해 현저히 길이를 줄일 수 있다. 따라서, 인터포저(100)는 지금까지의 인터포저에 비해 고집적 초박형 반도체 패키지를 구현할 수 있다. 특히, 인터포저(100)는 다양한 이종 소자 집적회로 칩을 이용한 초박형 초소형 모듈 설계가 가능하다. 그리고, 인터포저(100)는 플립칩(flip-chip) 적층이 가능한 3차원 반도체 패키지를 구현할 수 있다. As such, since the interposer 100 has an integrated circuit chip inserted therein, the interposer 100 can be significantly reduced in thickness compared to other interposers for mounting the integrated circuit chip on the surface. In addition, since the interposer 100 has thin film circuits or integrated circuits formed on both surfaces of the semiconductor substrate 110, the interposer 100 may be significantly shorter than other interposers that form thin film circuits or integrated circuits only on one surface of the semiconductor substrate 110. Can be. Therefore, the interposer 100 may implement a highly integrated ultra-thin semiconductor package as compared to the interposers up to now. In particular, the interposer 100 can design an ultra-thin ultra-small module using various heterogeneous integrated circuit chips. The interposer 100 may implement a 3D semiconductor package capable of flip-chip stacking.

이상에서 설명한 본 발명의 실시예는 장치 및 방법을 통해서만 구현이 되는 것은 아니며, 본 발명의 실시예의 구성에 대응하는 기능을 실현하는 프로그램 또는 그 프로그램이 기록된 기록 매체를 통해 구현될 수도 있다.The embodiments of the present invention described above are not implemented only by the apparatus and method, but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded.

이상에서 본 발명의 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (6)

반도체 기판의 제1면에 박막 회로를 형성하는 단계,
상기 제1면에서 적어도 하나의 관통 비아를 형성하는 단계,
상기 적어도 하나의 관통 비아와 상기 제1면에 형성된 박막 회로를 전기적으로 연결하는 단계, 그리고
상기 적어도 하나의 관통 비아와 상기 반도체 기판의 제2면에 형성된 집적회로 칩을 전기적으로 연결하는 단계
를 포함하고,
상기 적어도 하나의 관통 비아와 상기 집적회로 칩은 상기 제2면에서 전기적으로 연결되는 인터포저 제조 방법.Forming a thin film circuit on the first surface of the semiconductor substrate,
Forming at least one through via in the first surface,
Electrically connecting the at least one through via and the thin film circuit formed on the first surface, and
Electrically connecting the at least one through via and an integrated circuit chip formed on a second surface of the semiconductor substrate.
Lt; / RTI >
And the at least one through via and the integrated circuit chip are electrically connected at the second surface. 제1항에서,
상기 적어도 하나의 관통 비아를 형성하는 단계는
상기 집적회로 칩 삽입을 위한 구멍의 깊이, 그리고 상기 집적회로 칩 삽입을 위한 구멍에서의 기판 두께를 기초로 상기 관통 비아의 길이를 결정하는 인터포저 제조 방법.In claim 1,
Forming the at least one through via
And determining the length of the through via based on the depth of the hole for inserting the integrated circuit chip and the thickness of the substrate in the hole for inserting the integrated circuit chip. 제1항에서,
상기 집적회로 칩을 전기적으로 연결하는 단계는
상기 제2면에 적어도 하나의 집적회로 구멍을 형성하는 단계,
상기 적어도 하나의 집적회로 구멍에 집적회로 칩을 삽입하는 단계, 그리고
상기 적어도 하나의 관통 비아와 상기 집적회로 칩을 전기적으로 연결하는 단계
를 포함하는 인터포저 제조 방법.In claim 1,
Electrically connecting the integrated circuit chip
Forming at least one integrated circuit hole in the second surface;
Inserting an integrated circuit chip into the at least one integrated circuit hole, and
Electrically connecting the at least one through via and the integrated circuit chip
Interposer manufacturing method comprising a. 제3항에서,
상기 집적회로 구멍을 형성하는 단계는
상기 관통 비아가 드러날 때까지 상기 제2면을 깎는 단계, 그리고
상기 관통 비아가 노출된 상기 제2면에서 집적회로 칩이 삽입될 구멍을 형성하는 단계
를 포함하는 인터포저 제조 방법.4. The method of claim 3,
Forming the integrated circuit hole
Shaving the second surface until the through via is exposed; and
Forming a hole into which an integrated circuit chip is to be inserted in the second surface where the through via is exposed;
Interposer manufacturing method comprising a. 적어도 하나의 관통 비아가 형성된 반도체 기판,
상기 반도체 기판의 한 면에 형성된 제1 회로, 그리고
상기 반도체 기판의 다른 한 면에 형성된 제2 회로를 포함하고,
상기 제1 회로와 상기 제2 회로 각각은 형성된 면에서 상기 적어도 하나의 관통 비아와 전기적으로 연결되고, 상기 제1 회로와 상기 제2 회로 중 적어도 하나는 해당 면에 형성된 구멍에 삽입되는 집적회로 칩을 포함하는 인터포저.A semiconductor substrate having at least one through via formed therein,
A first circuit formed on one surface of the semiconductor substrate, and
A second circuit formed on the other side of the semiconductor substrate,
Each of the first circuit and the second circuit is electrically connected to the at least one through via in a formed surface, and at least one of the first circuit and the second circuit is inserted into a hole formed in the corresponding surface Interposer comprising a. 삭제delete
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