KR20090080701A - Semiconductor package and stack package using the same - Google Patents

Semiconductor package and stack package using the same Download PDF

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KR20090080701A
KR20090080701A KR1020080006606A KR20080006606A KR20090080701A KR 20090080701 A KR20090080701 A KR 20090080701A KR 1020080006606 A KR1020080006606 A KR 1020080006606A KR 20080006606 A KR20080006606 A KR 20080006606A KR 20090080701 A KR20090080701 A KR 20090080701A
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chip
package
interposer
semiconductor package
substrate
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KR1020080006606A
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Korean (ko)
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황찬기
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

A semiconductor package and a laminated package using the same are provided to easily control a height of a whole laminated package although packages in which chips of various kinds such as a functional device and an interposer chip are arranged are laminated. A semiconductor package includes a substrate, a memory chip, an interposer chip, and an encapsulating agent(116a,116b). The memory chip is arranged on the substrate. The interposer chip is arranged on the substrate of both sides of the memory chip. The encapsulating agent encapsulates a top surface of the substrate including the memory chip and a rest part except for a part of the interposer chip. The laminated package includes a semiconductor package, connecting parts(121a,121b), and an external contact terminal(128). The connecting parts are arranged on the interposer chip exposed of a bottom semiconductor package in the laminated semiconductor package. The connecting parts electrically and mechanically connect the laminated semiconductor packages. The external contact terminal is attached on a bottom surface of the substrate of the bottom semiconductor package.

Description

반도체 패키지 및 이를 이용한 적층 패키지{SEMICONDUCTOR PACKAGE AND STACK PACKAGE USING THE SAME}Semiconductor package and laminated package using same {SEMICONDUCTOR PACKAGE AND STACK PACKAGE USING THE SAME}

본 발명은 반도체 패키지 및 이를 이용한 적층 패키지에 관한 것으로, 보다 자세하게는, 솔더가 도금된 구리로 이루어진 연결부 및 인터포저(Interposer) 칩을 이용하여 반도체 패키지들 간을 적층한 반도체 패키지 및 이를 이용한 적층 패키지에 관한 것이다. The present invention relates to a semiconductor package and a laminated package using the same, and more particularly, to a semiconductor package laminated between semiconductor packages using an interconnection chip made of solder-plated copper and an interposer chip, and a laminated package using the same. It is about.

노트북컴퓨터, 휴대전화, PDA(Personal Digital Assistant)등과 같은 전자제품의 경박단소화는 관련 부품들, 즉, 인쇄회로 기판(Printed Circuit Board : 이하 "PCB"라고 함)에 실장되는 반도체 패키지의 소형화가 요구되고 있다. The miniaturization of electronic products such as notebook computers, cellular phones, PDAs (Personal Digital Assistants), etc., has led to miniaturization of semiconductor packages mounted on related components, namely, printed circuit boards (hereinafter referred to as "PCBs"). It is required.

통상의 반도체 패키지는 적어도 하나 이상의 반도체 칩이 탑재된 형태를 가지며, 상기 반도체 패키지를 이용하여 특정의 전자 회로 세트를 구현하기 위해서는 상기 반도체 패키지뿐만 아니라 특성 열화가 없는 신호의 전달에 필수적인 여러 가지 수동소자(Passives)들을 장착시켜야 한다. 수동소자로는 저항(Resistor, R), 인덕터(Inductor, L), 축전기(Capacitor, C)등이 있고, 이들은 통상 반도체 패키지가 장착되는 PCB 상에 장착된다.A conventional semiconductor package has a form in which at least one semiconductor chip is mounted, and in order to implement a specific set of electronic circuits using the semiconductor package, not only the semiconductor package but also various passive devices essential for transmitting signals without deterioration of characteristics. (Passives) should be equipped. Passive devices include resistors (R), inductors (L), capacitors (C), and the like, which are typically mounted on a PCB on which a semiconductor package is mounted.

그러나, 상기 신호 특성의 열화 방지 등에 필수적인 수동소자들이 PCB 상에 장착되기 때문에 PCB의 면적이 불필요하게 커지게 되는 문제가 있으며, 이러한 문제가 제품의 소형화를 저해시키는 요인으로 작용하게 된다. 또한, PCB 상에 수동소자를 직접 장착하기 때문에 신호선의 길이가 길어져 신호 전달의 지연이 발생하거나, 또는, 신호 전달 과정에서 노이즈가 삽입되는 문제가 있으며, 이러한 문제들로 인해 신호 특성의 근본적인 열화를 방지하는데 한계를 가질 수밖에 없다. 그리고, 일반적으로 회로에서 수동소자들이 차지하는 비중은 80%정도이며, 수동소자들이 인쇄회로기판에서 차지하는 면적은 50% 정도가 된다. However, since passive elements, which are essential for preventing degradation of signal characteristics, are mounted on the PCB, there is a problem that the area of the PCB becomes unnecessarily large, and this problem acts as a factor that hinders miniaturization of the product. In addition, since passive elements are directly mounted on the PCB, signal lines are lengthened to cause delays in signal transmission, or noise may be inserted in the signal transmission process, thereby causing fundamental degradation of signal characteristics. There is no limit to the prevention. In general, the passive components occupy about 80% of the circuit, and the passive components occupy about 50% of the printed circuit board.

따라서, 수동 소자는 전자기기의 가격, 크기, 신뢰성에 중대한 영향을 미친다. Thus, passive components have a significant impact on the cost, size and reliability of electronic devices.

이에 따라, 각각의 부품을 개별적으로 소형화시키는 방법 이외에 여러 가지 부품들을 집적시켜 하나의 모듈(Module)로 만들거나 또는 실장밀도를 향상시키기 위하여 수동 소자들을 다층인쇄회로 기판(Multi-Layered Printed Circuit Board)에 내장시키는 내장형 수동 소자(Embedded Passives) 기술이 연구되고 있다. Accordingly, in addition to the method of miniaturizing each component individually, in order to integrate several components into a single module or to improve mounting density, passive components may be multi-layered printed circuit boards. Embedded Passives technology is being researched.

내장형 수동 소자를 구현하기 위한 기술로는 수동 소자가 메모리 칩에 일체로 형성되는 SOC(System On Chip)와 능동 소자와 같은 기능성 소자가 패키지 형태로 내장되는 SIP(System In Package)가 있다. Techniques for implementing embedded passive devices include a system on chip (SOC) in which passive devices are integrally formed in a memory chip and a system in package (SIP) in which functional devices such as active devices are packaged.

한편, 상기와 같은 능동 소자와 같은 기능성 소자가 패키지 형태로 내장되는 SIP 타입 반도체 패키지를 적어도 둘 이상 적층하여 구성하는 적층 패키지에서는, 상기 능동 소자와 같은 기능성 소자 뿐만 아니라, 인터포저 칩과 같은 여러 다른 종류의 칩들이 패키지 내에 동시에 배치되기 때문에, 각 SIP 타입 반도체 패키지들을 적층 시, 적층된 전체 패키지의 높이를 용이하게 조절하기가 어려워, SIP 타입 반도체 패키지들 간을 적층하여 적층 패키지 구현시에는 전체 패키지의 높이에 따른 한계가 발생하게 된다.On the other hand, in a multilayer package formed by stacking at least two SIP type semiconductor packages in which functional elements such as the active elements are embedded in a package form, not only functional elements such as the active elements, but also various other elements such as an interposer chip. Since different types of chips are placed in the package at the same time, it is difficult to easily adjust the height of the entire stacked package when stacking each SIP type semiconductor package. There is a limit depending on the height of.

본 발명은 반도체 패키지 및 이를 이용한 반도체 패키지들 간을 적층하여 적층 패키지 형성시, 적층된 전체 패키지의 높이를 용이하게 조절하여 형성할 수 있는 반도체 패키지 및 이를 이용한 적층 패키지를 제공한다.The present invention provides a semiconductor package and a laminate package using the same, which can be formed by easily adjusting the height of the entire stacked package when stacking the semiconductor package and the semiconductor packages using the same.

본 발명에 따른 반도체 패키지는, 기판; 상기 기판 상에 배치된 메모리 칩; 상기 메모리 칩 양측의 기판 상에 배치된 인터포저(Interposer) 칩; 및 상기 인터포저 칩의 일부를 제외한 나머지 부분과 메모리 칩을 포함한 기판의 상면을 밀봉하는 봉지제;를 포함한다.The semiconductor package according to the present invention, the substrate; A memory chip disposed on the substrate; An interposer chip disposed on substrates on both sides of the memory chip; And an encapsulant for sealing an upper portion of the substrate including the memory chip and the remaining portion except a portion of the interposer chip.

상기 인터포저 칩은 플립 칩 본딩된 것을 특징으로 한다.The interposer chip is flip chip bonded.

상기 인터포저 칩은 베어(Bare) 웨이퍼 상에 수동소자 또는 능동소자가 플립 칩 본딩된 것을 특징으로 한다.The interposer chip is characterized in that a passive chip or an active device is flip chip bonded on a bare wafer.

또한, 본 발명에 따른 적층 패키지는, 기판과, 상기 기판 상에 배치된 메모리 칩과, 상기 메모리 칩 양측의 기판 상에 배치된 인터포저(Interposer) 칩과, 상기 인터포저 칩의 일부를 제외한 나머지 부분과 메모리 칩을 포함한 기판의 상면을 밀봉하는 봉지제를 포함하며, 적어도 둘 이상이 스택된 반도체 패키지; 상기 스택된 반도체 패키지 중 하측 반도체 패키지의 노출된 인터포저 칩 상에 배치되어 상기 스택된 반도체 패키지 간을 전기적 및 기계적으로 연결하는 연결부; 및 상기 하측 반도체 패키지의 기판 하면에 부착된 외부 접속 단자;를 포함한다.In addition, the stacked package according to the present invention includes a substrate, a memory chip disposed on the substrate, an interposer chip disposed on substrates on both sides of the memory chip, and a part of the interposer chip. A semiconductor package comprising an encapsulant sealing an upper surface of the substrate including a portion and a memory chip, wherein at least two semiconductor packages are stacked; A connection part disposed on an exposed interposer chip of a lower semiconductor package among the stacked semiconductor packages to electrically and mechanically connect the stacked semiconductor packages; And an external connection terminal attached to a lower surface of the substrate of the lower semiconductor package.

상기 연결부는 솔더가 도금된 구리를 포함한다.The connection comprises copper plated with solder.

상기 스택된 반도체 패키지 중, 상측 반도체 패키지 상에 부착된 열 인터페이스 물질(TIM : Thermal Interface Material) 및 히트 스프레더를 더 포함한다.The stacked semiconductor package further includes a thermal interface material (TIM) and a heat spreader attached on the upper semiconductor package.

상기 인터포저 칩은 플립 칩 본딩된 것을 특징으로 한다.The interposer chip is flip chip bonded.

상기 인터포저 칩은 베어(Bare) 웨이퍼 상에 수동 소자 또는 능동 소자가 플립 칩 본딩된 것을 특징으로 한다.The interposer chip may be a flip chip bonded passive device or an active device on a bare wafer.

본 발명은 반도체 패키지 및 이를 이용한 적어도 둘 이상의 반도체 패키지 간을 적층하여 적층 패키지 형성시, 인터포저(Interposer) 칩의 일측 단부가 노출되도록 패키지를 밀봉하고, 상기 노출된 인터포저 칩 상에 솔더가 도금된 구리 연결부를 이용하여 각 패키지 간을 적층함으로써, 능동 소자와 같은 기능성 소자뿐만 아니라, 인터포저 칩과 같은 여러 다른 종류의 칩들이 패키지 내에 배치되는 패키지들 간을 적층 시에도 전체 적층 패키지의 높이를 용이하게 조절할 수 있다.According to the present invention, a semiconductor package and at least two or more semiconductor packages using the same are stacked to seal the package so that one end of the interposer chip is exposed when the stacked package is formed, and solder is plated on the exposed interposer chip. By stacking each package using copper connections, the height of the entire stacked package can be increased not only for functional devices such as active devices, but also for packages where different types of chips such as interposer chips are placed in the package. It can be adjusted easily.

본 발명은, 반도체 패키지 및 이를 이용한 적어도 둘 이상의 반도체 패키지 간을 적층하여 적층 패키지 형성시, 상기 각 반도체 패키지의 기판 상에 배치된 인 터포저(Interposer) 칩을 상기 인터포저 칩의 일측 단부가 노출되도록 패키지를 밀봉하고, 상기 노출된 인터포저 칩 상에 솔더가 도금된 구리 연결부를 이용하여 각 반도체 패키지 간을 적층한다.According to an embodiment of the present invention, one end of an interposer chip is exposed to an interposer chip disposed on a substrate of each semiconductor package when a semiconductor package and at least two semiconductor packages using the same are stacked. The package is sealed as much as possible, and the semiconductor packages are stacked between the exposed interposer chips using solder-plated copper connections.

이렇게 하면, 상기 일측 단부가 노출되도록 인터포저 칩을 형성하고, 상기 인터포저 칩 상에 솔더가 도금된 구리 연결부를 이용해 각 반도체 패키지들 간을 적층함으로써, 능동 소자와 같은 기능성 소자뿐만 아니라, 인터포저 칩과 같은 여러 다른 종류의 칩들이 패키지 내에 동시에 배치되는 반도체 패키지들 간을 적층 시에도, 상기 연결부 및 일측 단부가 노출되도록 형성된 인터포저 칩에 의해 전체 적층 패키지의 높이를 용이하게 조절할 수 있다.In this case, an interposer chip is formed to expose the one end portion, and the interposer is stacked between the respective semiconductor packages using solder-plated copper connections on the interposer chip, thereby not only an interposer but also a functional device such as an active element. When stacking semiconductor packages in which several different types of chips, such as chips, are simultaneously disposed in a package, the height of the entire stacked package can be easily adjusted by an interposer chip formed such that the connection portion and one end thereof are exposed.

이하에서는, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

자세하게, 도 1은 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도시된 바와 같이 본 발명의 실시예에 따른 반도체 패키지(100)는, 상면 및 하면에 각각 전극단자(103) 및 볼 랜드(122)를 갖는 기판(102)의 상기 상면의 중앙 부분에 접착제(도시안됨)를 매개로 메모리 칩(104)이 부착되고, 상기 메모리 칩(104)과 기판의 전극단자(103) 간은 본딩와이어(106)에 의해 전기적으로 연결된다. As illustrated, the semiconductor package 100 according to the embodiment of the present invention may have an adhesive (shown) on a central portion of the upper surface of the substrate 102 having the electrode terminals 103 and the ball lands 122 on the upper and lower surfaces, respectively. Memory chip 104 is attached, and the memory chip 104 and the electrode terminal 103 of the substrate are electrically connected by a bonding wire 106.

또한, 상기 기판(102) 상면의 가장자리에 회로배선(107)을 갖는 인터포저(Interposer) 칩(108)이 부착되며, 상기 인터포저 칩(108) 및 메모리 칩(104)을 포함하는 기판(102)의 일면이 상기 메모리 칩(104)을 외부의 스트레스로부터 보호하기 위해 상기 인터포저 칩(108)의 일측 단부는 외측으로 노출되도록 EMC(Epoxy Molding Compound)와 같은 봉지제(116)로 밀봉되고, 상기 기판(102)의 하면 볼 랜드(122)에는 솔더 볼과 같은 외부 접속 단자(128)가 부착된다.In addition, an interposer chip 108 having a circuit wiring 107 is attached to an edge of an upper surface of the substrate 102, and the substrate 102 including the interposer chip 108 and the memory chip 104. One end of the interposer chip 108 is sealed with an encapsulant 116 such as an epoxy molding compound (EMC) so that one side of the interposer chip 108 is exposed to the outside to protect the memory chip 104 from external stress. An external connection terminal 128 such as solder balls is attached to the lower surface ball land 122 of the substrate 102.

여기서, 상기 인터포저 칩(108)은 범프(110)를 매개로 플립 칩 본딩되며, 이때, 상기 인터포저 칩(108)은 베어(Bare) 웨이퍼 상에 수동 또는 능동 소자(114)가 범프(110)를 매개로 플립 칩 본딩된 구조로 이루어진다.Here, the interposer chip 108 is flip chip bonded via the bump 110, wherein the interposer chip 108 is a passive 110 or active element 114 on the bare wafer. ) Is a flip chip bonded structure.

또한, 상기 인터포저 칩(108)과 기판(102) 사이의 공간에는 언더-필과 같은 충진제(112)가 매립된다.In addition, a filler 112 such as an under-fill is filled in the space between the interposer chip 108 and the substrate 102.

자세하게, 도 2는 본 발명의 실시예에 따른 반도체 패키지를 이용한 적층 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, FIG. 2 is a cross-sectional view illustrating a laminated package using a semiconductor package according to an embodiment of the present invention.

도시된 바와 같이, 본 발명의 실시예에 따른 적층 패키지(150)는, 상면 및 하면에 각각 전극단자(103a, 103b) 및 볼 랜드(122a, 122b)를 갖는 기판(102a, 102b)의 상기 상면의 중앙 부분에 접착제(도시안됨)를 매개로 메모리 칩(104a, 104b)이 부착된다.As shown, the laminated package 150 according to the embodiment of the present invention, the upper surface and the lower surface of the substrate (102a, 102b) having electrode terminals 103a, 103b and ball land (122a, 122b), respectively Memory chips 104a and 104b are attached to the central portion of the substrate via an adhesive (not shown).

또한, 상기 기판(102a, 102b) 상면의 가장자리에 회로배선(107a, 107b)을 갖는 인터포저 칩(Interposer : 108a, 108b)이 부착되며, 상기 인터포저 칩(108a, 108b) 및 메모리 칩(104a, 104b)을 포함하는 기판(102a, 102b)의 일면이 상기 메모리 칩(104a, 104b)을 외부의 스트레스로부터 보호하기 위해 상기 인터포저 칩(108a, 108b)의 일측 단부는 외측으로 노출되도록 EMC(Epoxy Molding Compound) 와 같은 봉지제(116a, 116b)로 밀봉된 구조를 갖는 반도체 패키지(A, B)가 적어도 둘 이상 적층된 구조를 갖는다.In addition, interposer chips 108a and 108b having circuit wirings 107a and 107b are attached to edges of upper surfaces of the substrates 102a and 102b, and the interposer chips 108a and 108b and the memory chip 104a are attached. One end of the interposer chips 108a and 108b may be exposed to the outside so that one surface of the substrates 102a and 102b including the 104b may protect the memory chips 104a and 104b from external stress. At least two semiconductor packages A and B having a structure sealed with encapsulants 116a and 116b, such as epoxy molding compound, are stacked.

이때, 상기 메모리 칩(104a, 104b)과 기판(102a, 102b)의 전극단자(103a, 103b) 간은 본딩와이어(106a, 106b)에 의해 전기적으로 연결되며, 상기 인터포저 칩(108a, 108b)은 상기 기판(102a, 102b) 상에 범프(110a, 110b)를 이용한 플립 칩 방식으로 부착되고, 이때, 상기 인터포저 칩(108a, 108b)와 상기 기판(102a, 102b) 사이에는 언더-필(Under-Fill)과 같은 충진제(112a, 112b)가 매립된다.In this case, the memory chips 104a and 104b and the electrode terminals 103a and 103b of the substrates 102a and 102b are electrically connected by bonding wires 106a and 106b, and the interposer chips 108a and 108b are connected to each other. Is attached to the substrates 102a and 102b in a flip-chip manner using bumps 110a and 110b, wherein an under-fill (between the interposer chips 108a and 108b and the substrates 102a and 102b) is attached to the substrates 102a and 102b. Fillers 112a and 112b, such as under-fill, are embedded.

그리고, 상기 인터포저 칩(108a, 108b) 상에는 능동 또는 수동 소자(114a, 114b)가 범프(110a, 110b)를 이용한 플립 칩 방식으로 부착된다.The active or passive elements 114a and 114b are attached to the interposer chips 108a and 108b in a flip chip manner using the bumps 110a and 110b.

또한, 상기 봉지제(116a, 116b) 외측으로 노출된 인터포저 칩(108a, 108b) 일측 단부의 본딩패드(107a, 107b) 상에는, 솔더(120a, 120b)로 도금되며 구리(118a, 118b)로 이루어진 연결부(121a, 121b)가 형성되며, 상측 패키지(A) 기판(102b) 하면의 볼 랜드(122b)와 부착되어 적층된 각 상측 패키지(A) 및 하측 패키지(B)를 전기적으로 연결시킨다.In addition, on the bonding pads 107a and 107b at one end of the interposer chips 108a and 108b exposed to the outside of the encapsulant 116a and 116b, they are plated with solders 120a and 120b and made of copper 118a and 118b. The connection portions 121a and 121b may be formed, and the upper packages A and the lower packages B may be electrically connected to the ball lands 122b on the lower surface of the upper package A and the substrate 102b.

게다가, 상기 적층된 반도체 패키지들(A, B) 중, 상측 반도체 패키지(A)의 봉지제(116b) 및 연결부(121b) 상에는 열 인터페이스 물질(TIM : Thermal Interface Material : 124) 및 히트 스프레더(126)가 부착된다.In addition, among the stacked semiconductor packages A and B, a thermal interface material (TIM) 124 and a heat spreader 126 are formed on the encapsulant 116b and the connection portion 121b of the upper semiconductor package A. ) Is attached.

아울러, 상기 스택된 반도체 패키지들(A, B) 중, 하측 반도체 패키지(A) 기판(102a)의 볼 랜드(122a)에는 실장 수단으로서 솔더 볼과 같은 외부 접속 단자(128)가 다수 개 부착된다.In addition, a plurality of external connection terminals 128 such as solder balls are attached to the ball lands 122a of the lower semiconductor package A substrate 102a among the stacked semiconductor packages A and B. .

전술한 바와 같이 본 발명은, 반도체 패키지 및 이를 이요한 적어도 둘 이상의 반도체 패키지 간을 적층하여 적층 패키지 형성시, 상기 각 반도체 패키지의 기판 상에 배치된 인터포저(Interposer) 칩을 상기 인터포저 칩의 일측 단부가 노출되도록 패키지를 밀봉하고, 상기 노출된 인터포저 칩 상에 솔더가 도금된 구리 연결부를 이용하여 각 반도체 패키지 간을 적층함으로써, 능동 소자와 같은 기능성 소자뿐만 아니라, 인터포저 칩과 같은 여러 다른 종류의 칩들이 패키지 내에 배치되는 반도체 패키지들 간을 적층 시에도 상기 연결부 및 일측 단부가 노출되도록 형성된 인터포저 칩에 의해 전체 적층 패키지의 높이를 용이하게 조절할 수 있다.As described above, the present invention, when forming a stack package by stacking a semiconductor package and at least two or more semiconductor packages required by the same, the interposer chip disposed on the substrate of each semiconductor package of the interposer chip The package is sealed so that one end is exposed, and the semiconductor package is laminated between the semiconductor packages using solder-plated copper connections on the exposed interposer chip, thereby providing various functions such as interposer chips as well as functional devices such as active devices. The height of the entire stacked package can be easily adjusted by an interposer chip formed so that the connection portion and one end thereof are exposed even when stacked between semiconductor packages in which different types of chips are disposed in the package.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도.1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도 2는 본 발명의 실시예에 따른 반도체 패키지를 이용한 적층 패키지를 설명하기 위해 도시한 단면도.2 is a cross-sectional view illustrating a laminated package using a semiconductor package according to an embodiment of the present invention.

Claims (8)

기판;Board; 상기 기판 상에 배치된 메모리 칩;A memory chip disposed on the substrate; 상기 메모리 칩 양측의 기판 상에 배치된 인터포저(Interposer) 칩; 및An interposer chip disposed on substrates on both sides of the memory chip; And 상기 인터포저 칩의 일부를 제외한 나머지 부분과 메모리 칩을 포함한 기판의 상면을 밀봉하는 봉지제;An encapsulant sealing an upper portion of a substrate including a memory chip and a remaining portion except a portion of the interposer chip; 를 포함하는 것을 특징으로 하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 인터포저 칩은 플립 칩 본딩된 것을 특징으로 하는 반도체 패키지.And the interposer chip is flip chip bonded. 제 1 항에 있어서,The method of claim 1, 상기 인터포저 칩은 베어(Bare) 웨이퍼 상에 수동소자 또는 능동소자가 플립 칩 본딩된 것을 특징으로 하는 반도체 패키지.The interposer chip is a semiconductor package, characterized in that the passive chip or active device flip chip bonding on a bare wafer. 기판과, 상기 기판 상에 배치된 메모리 칩과, 상기 메모리 칩 양측의 기판 상에 배치된 인터포저(Interposer) 칩과, 상기 인터포저 칩의 일부를 제외한 나머지 부분과 메모리 칩을 포함한 기판의 상면을 밀봉하는 봉지제를 포함하며, 적어도 둘 이상이 스택된 반도체 패키지;A top surface of a substrate including a substrate, a memory chip disposed on the substrate, an interposer chip disposed on substrates on both sides of the memory chip, a portion other than a portion of the interposer chip, and a memory chip. A semiconductor package comprising an encapsulant for sealing, wherein at least two or more are stacked; 상기 스택된 반도체 패키지 중 하측 반도체 패키지의 노출된 인터포저 칩 상에 배치되어 상기 스택된 반도체 패키지 간을 전기적 및 기계적으로 연결하는 연결부; 및A connection part disposed on an exposed interposer chip of a lower semiconductor package among the stacked semiconductor packages to electrically and mechanically connect the stacked semiconductor packages; And 상기 하측 반도체 패키지의 기판 하면에 부착된 외부 접속 단자;An external connection terminal attached to a lower surface of the substrate of the lower semiconductor package; 를 포함하는 것을 특징으로 하는 적층 패키지.Laminated package comprising a. 제 4 항에 있어서,The method of claim 4, wherein 상기 연결부는 솔더가 도금된 구리를 포함하는 것을 특징으로 하는 적층 패키지.And the connection part comprises copper plated with solder. 제 4 항에 있어서,The method of claim 4, wherein 상기 스택된 반도체 패키지 중, 상측 반도체 패키지 상에 부착된 열 인터페이스 물질(TIM : Thermal Interface Material) 및 히트 스프레더를 더 포함하는 것을 특징으로 하는 적층 패키지.Among the stacked semiconductor packages, the stacked package further comprises a thermal interface material (TIM) and a heat spreader attached on the upper semiconductor package. 제 4 항에 있어서,The method of claim 4, wherein 상기 인터포저 칩은 플립 칩 본딩된 것을 특징으로 하는 적층 패키지.And the interposer chip is flip chip bonded. 제 4 항에 있어서,The method of claim 4, wherein 상기 인터포저 칩은 베어(Bare) 웨이퍼 상에 수동 소자 또는 능동 소자가 플 립 칩 본딩된 것을 특징으로 하는 적층 패키지.The interposer chip is a laminated package, characterized in that the passive chip or active device is flip chip bonded on the bare wafer.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381512B (en) * 2009-11-12 2013-01-01 Powertech Technology Inc Multi-chip stack structure
KR20150057788A (en) * 2013-11-20 2015-05-28 삼성전기주식회사 Semi-conductor Package and Method for Manufacturing The same
KR20170008958A (en) * 2015-07-15 2017-01-25 주식회사 에스에프에이반도체 Stacked semiconductor package and method for manufacturing the same
US11121067B2 (en) 2019-02-14 2021-09-14 Samsung Electronics Co., Ltd Interposer and electronic device including the same
US11224117B1 (en) 2018-07-05 2022-01-11 Flex Ltd. Heat transfer in the printed circuit board of an SMPS by an integrated heat exchanger

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381512B (en) * 2009-11-12 2013-01-01 Powertech Technology Inc Multi-chip stack structure
KR20150057788A (en) * 2013-11-20 2015-05-28 삼성전기주식회사 Semi-conductor Package and Method for Manufacturing The same
KR20170008958A (en) * 2015-07-15 2017-01-25 주식회사 에스에프에이반도체 Stacked semiconductor package and method for manufacturing the same
US11224117B1 (en) 2018-07-05 2022-01-11 Flex Ltd. Heat transfer in the printed circuit board of an SMPS by an integrated heat exchanger
US11121067B2 (en) 2019-02-14 2021-09-14 Samsung Electronics Co., Ltd Interposer and electronic device including the same

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