TW200723709A - Deinterleaver and dual-viterbi decoder architecture - Google Patents

Deinterleaver and dual-viterbi decoder architecture

Info

Publication number
TW200723709A
TW200723709A TW095126766A TW95126766A TW200723709A TW 200723709 A TW200723709 A TW 200723709A TW 095126766 A TW095126766 A TW 095126766A TW 95126766 A TW95126766 A TW 95126766A TW 200723709 A TW200723709 A TW 200723709A
Authority
TW
Taiwan
Prior art keywords
decoder
data
input
decoders
deinterleaver
Prior art date
Application number
TW095126766A
Other languages
English (en)
Inventor
Mustafa Altintas
Turgut Aytur
Ravishankar H Mahadevappa
Feng Shi
Stephan Ten Brink
Ran Yan
Original Assignee
Wionics Research
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wionics Research filed Critical Wionics Research
Publication of TW200723709A publication Critical patent/TW200723709A/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Error Detection And Correction (AREA)
TW095126766A 2005-07-21 2006-07-21 Deinterleaver and dual-viterbi decoder architecture TW200723709A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70168005P 2005-07-21 2005-07-21

Publications (1)

Publication Number Publication Date
TW200723709A true TW200723709A (en) 2007-06-16

Family

ID=37683830

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095126766A TW200723709A (en) 2005-07-21 2006-07-21 Deinterleaver and dual-viterbi decoder architecture

Country Status (4)

Country Link
US (1) US7779338B2 (zh)
CN (1) CN101268452A (zh)
TW (1) TW200723709A (zh)
WO (1) WO2007014043A2 (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8179954B2 (en) 2007-10-30 2012-05-15 Sony Corporation Odd interleaving only of an odd-even interleaver when half or less data subcarriers are active in a digital video broadcasting (DVB) standard
JP4809099B2 (ja) * 2006-03-30 2011-11-02 ルネサスエレクトロニクス株式会社 受信回路及び受信方法
US8645793B2 (en) 2008-06-03 2014-02-04 Marvell International Ltd. Statistical tracking for flash memory
US20080063105A1 (en) * 2006-09-13 2008-03-13 Via Telecom, Inc. System and method for implementing preamble channel in wireless communication system
US8316206B2 (en) 2007-02-12 2012-11-20 Marvell World Trade Ltd. Pilot placement for non-volatile memory
US7827450B1 (en) 2006-11-28 2010-11-02 Marvell International Ltd. Defect detection and handling for memory based on pilot cells
US8055207B2 (en) * 2006-12-06 2011-11-08 Broadcom Corporation RF receiver with fast baseband switching
US7808834B1 (en) 2007-04-13 2010-10-05 Marvell International Ltd. Incremental memory refresh
KR101433620B1 (ko) * 2007-08-17 2014-08-25 삼성전자주식회사 처리량을 높이기 위하여 더블 버퍼링 구조와 파이프라이닝기법을 이용하는 디코더 및 그 디코딩 방법
US8031526B1 (en) 2007-08-23 2011-10-04 Marvell International Ltd. Write pre-compensation for nonvolatile memory
US8189381B1 (en) 2007-08-28 2012-05-29 Marvell International Ltd. System and method for reading flash memory cells
US8085605B2 (en) * 2007-08-29 2011-12-27 Marvell World Trade Ltd. Sequence detection for flash memory with inter-cell interference
KR101437517B1 (ko) * 2007-10-23 2014-09-05 삼성전자주식회사 인터리빙 기법을 이용한 메모리 시스템, 및 그 방법
KR100888508B1 (ko) * 2007-12-13 2009-03-12 한국전자통신연구원 비터비 복호 장치 및 방법
US8804049B2 (en) 2008-01-31 2014-08-12 Mediatek Inc. Wireless communication receiver, a wireless communication receiving method and a television receiver
US8179719B1 (en) 2008-03-10 2012-05-15 Marvell International Ltd. Systems and methods for improving error distributions in multi-level cell memory systems
US8576955B2 (en) * 2008-03-28 2013-11-05 Qualcomm Incorporated Architecture to handle concurrent multiple channels
CN102007747B (zh) * 2008-04-18 2014-12-03 皇家飞利浦电子股份有限公司 改进的双载波调制预编码
US8233529B2 (en) * 2008-08-14 2012-07-31 Mediatek Inc. Video decoder
JP5287521B2 (ja) * 2009-06-04 2013-09-11 株式会社リコー 通信装置
US8638886B2 (en) * 2009-09-24 2014-01-28 Credo Semiconductor (Hong Kong) Limited Parallel viterbi decoder with end-state information passing
US20110119567A1 (en) * 2009-11-16 2011-05-19 Ralink Technology Corporation Signal processing method and communication system using the same
JP2012049776A (ja) * 2010-08-26 2012-03-08 Fujitsu Ltd アンテナ装置、通信システム、基地局装置及び通信方法
US9942580B2 (en) 2011-11-18 2018-04-10 At&T Intellecutal Property I, L.P. System and method for automatically selecting encoding/decoding for streaming media
US9798622B2 (en) * 2014-12-01 2017-10-24 Intel Corporation Apparatus and method for increasing resilience to raw bit error rate
KR101800415B1 (ko) * 2015-03-02 2017-11-23 삼성전자주식회사 송신 장치 및 그의 패리티 퍼뮤테이션 방법
US10201026B1 (en) 2016-06-30 2019-02-05 Acacia Communications, Inc. Forward error correction systems and methods
CN109691043B (zh) * 2016-09-06 2021-02-23 联发科技股份有限公司 无线通信系统中有效编码切换方法、用户设备及相关存储器
US9935800B1 (en) 2016-10-04 2018-04-03 Credo Technology Group Limited Reduced complexity precomputation for decision feedback equalizer
US10505676B1 (en) * 2018-08-10 2019-12-10 Acacia Communications, Inc. System, method, and apparatus for interleaving data
US10728059B1 (en) 2019-07-01 2020-07-28 Credo Technology Group Limited Parallel mixed-signal equalization for high-speed serial link

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3721884A1 (de) 1987-07-02 1989-01-12 Meyr Heinrich Prof Dr Verfahren zur ausfuehrung des viterbi-algorithmus mit hilfe parallelverarbeitender strukturen
FI100565B (fi) * 1996-01-12 1997-12-31 Nokia Mobile Phones Ltd Tiedonsiirtomenetelmä ja laitteisto signaalin koodaamiseksi
US6333922B1 (en) * 1996-11-05 2001-12-25 Worldspace, Inc. Satellite payload processing system for switching uplink signals to time division multiplexed downlink signals
KR100219842B1 (ko) 1997-03-12 1999-09-01 서평원 이동 전화시스템
JP3266182B2 (ja) 1997-06-10 2002-03-18 日本電気株式会社 ビタビ復号器
US6381728B1 (en) * 1998-08-14 2002-04-30 Qualcomm Incorporated Partitioned interleaver memory for map decoder
US6434203B1 (en) * 1999-02-26 2002-08-13 Qualcomm, Incorporated Memory architecture for map decoder
CA2353019A1 (en) 2000-07-14 2002-01-14 Pmc Sierra Limited Minimum error detection in a viterbi decoder
US7131055B2 (en) 2003-02-25 2006-10-31 Intel Corporation Fast bit-parallel Viterbi decoder add-compare-select circuit
US7065696B1 (en) * 2003-04-11 2006-06-20 Broadlogic Network Technologies Inc. Method and system for providing high-speed forward error correction for multi-stream data
KR100520934B1 (ko) * 2003-12-30 2005-10-17 삼성전자주식회사 디인터리버 메모리의 크기가 절감된 디지털 방송 수신기의디인터리빙장치 및 그의 디인터리빙방법
US20070205921A1 (en) * 2004-04-05 2007-09-06 Koninklijke Philips Electronics, N.V. Four-Symbol Parallel Viterbi Decoder

Also Published As

Publication number Publication date
US7779338B2 (en) 2010-08-17
WO2007014043A2 (en) 2007-02-01
CN101268452A (zh) 2008-09-17
WO2007014043A3 (en) 2007-12-27
US20070067704A1 (en) 2007-03-22

Similar Documents

Publication Publication Date Title
TW200723709A (en) Deinterleaver and dual-viterbi decoder architecture
MY163671A (en) Interleaver apparatus and receiver for a signal generated by the interleaver apparatus
MY161986A (en) Coder using forward aliasing cancellation
WO2007127941A3 (en) Radix-4 viterbi decoding
TW200711364A (en) Parallel turbo decoders with multiplexed output
WO2009074979A3 (en) Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications
WO2008057041A3 (en) Quadratic permutation polynomial interleaver/de-interleaver for turbo codes
WO2007091820A8 (en) Digital broadcasting reception apparatus and robust stream decoding method thereof
JP2011504309A5 (zh)
TW200742271A (en) Channel decoder and method for channel decoding
TW200515713A (en) A re-configurable Viterbi decoder
TW200707921A (en) Trellis calculations
US20070277064A1 (en) Reconfigurable convolutional interleaver/deinterleaver using minimum amount of memory and an address generator
TW200638687A (en) Viterbi decoding apparatus and method thereof
US20090300470A1 (en) Memory architecture for high throughput rs decoding for mediaflo receivers
WO2007123863A3 (en) Dual pdfe system with forward-backward viterbi
Leroux et al. Towards Gb/s turbo decoding of product code onto an FPGA device
Liu et al. Compiler of Reed–Solomon Codec for 400-Gb/s IEEE 802.3 bs Standard
KR980006964A (ko) 격자복호기의 역추적장치
WO2006130605A3 (en) An efficient interleaver/de-interleaver design for the turbo decoder in a 3g wcdma system
TWI268664B (en) An efficient soft decision demapper to minimize Viterbi decoder complexity
TW200709579A (en) Device and method for variable length decoding
DE60117421D1 (de) Vollen Pfadmetrikrechner in Viterbidekodierung
MY154137A (en) System and method for memory usage and latency optimization in wireless networks
TW200725363A (en) Switch of multimedia audiovisual device