TW200707757A - Method for forming contact hole and method for fabricating thin film transistor plate using the same - Google Patents
Method for forming contact hole and method for fabricating thin film transistor plate using the sameInfo
- Publication number
- TW200707757A TW200707757A TW095125847A TW95125847A TW200707757A TW 200707757 A TW200707757 A TW 200707757A TW 095125847 A TW095125847 A TW 095125847A TW 95125847 A TW95125847 A TW 95125847A TW 200707757 A TW200707757 A TW 200707757A
- Authority
- TW
- Taiwan
- Prior art keywords
- contact hole
- thin film
- film transistor
- same
- forming contact
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 4
- 239000010409 thin film Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Nonlinear Science (AREA)
- Inorganic Chemistry (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050064490A KR20070009329A (ko) | 2005-07-15 | 2005-07-15 | 컨택홀 형성 방법 및 이를 이용한 박막 트랜지스터 기판의제조 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200707757A true TW200707757A (en) | 2007-02-16 |
Family
ID=37609707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095125847A TW200707757A (en) | 2005-07-15 | 2006-07-14 | Method for forming contact hole and method for fabricating thin film transistor plate using the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US20070015319A1 (zh) |
JP (1) | JP2007027710A (zh) |
KR (1) | KR20070009329A (zh) |
CN (1) | CN1897248A (zh) |
TW (1) | TW200707757A (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20080068240A (ko) * | 2007-01-18 | 2008-07-23 | 삼성전자주식회사 | 박막 트랜지스터 기판의 제조 방법 |
US8786793B2 (en) * | 2007-07-27 | 2014-07-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
US8247276B2 (en) | 2009-02-20 | 2012-08-21 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, method for manufacturing the same, and semiconductor device |
JP5424724B2 (ja) * | 2009-06-04 | 2014-02-26 | 富士フイルム株式会社 | 電界効果型トランジスタの製造方法、電界効果型トランジスタ、表示装置、及び電磁波検出器 |
EP2284891B1 (en) * | 2009-08-07 | 2019-07-24 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device and manufacturing method thereof |
KR20130011856A (ko) * | 2011-07-22 | 2013-01-30 | 삼성디스플레이 주식회사 | 표시기판 및 그 제조방법 |
KR101916949B1 (ko) * | 2011-11-03 | 2018-11-09 | 엘지디스플레이 주식회사 | 프린지 필드형 액정표시장치 및 그 제조방법 |
WO2013089754A1 (en) * | 2011-12-15 | 2013-06-20 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (bbul) packages |
KR101972170B1 (ko) | 2012-11-19 | 2019-04-25 | 동우 화인켐 주식회사 | 액정표시장치용 어레이 기판의 제조방법 |
CN103413782B (zh) * | 2013-07-23 | 2015-08-26 | 北京京东方光电科技有限公司 | 一种阵列基板及其制作方法和显示面板 |
CN110854171B (zh) * | 2019-11-21 | 2022-09-13 | 京东方科技集团股份有限公司 | 一种显示基板及其制备方法、显示装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5658425A (en) * | 1991-10-16 | 1997-08-19 | Lam Research Corporation | Method of etching contact openings with reduced removal rate of underlying electrically conductive titanium silicide layer |
US6756324B1 (en) * | 1997-03-25 | 2004-06-29 | International Business Machines Corporation | Low temperature processes for making electronic device structures |
JP2002270586A (ja) * | 2001-03-08 | 2002-09-20 | Tokyo Electron Ltd | 有機系絶縁膜のエッチング方法およびデュアルダマシンプロセス |
US6933568B2 (en) * | 2002-05-17 | 2005-08-23 | Samsung Electronics Co., Ltd. | Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same |
US20040224241A1 (en) * | 2003-02-03 | 2004-11-11 | Samsung Electronics Co., Ltd. | Thin film transistor array panel, manufacturing method thereof, and mask therefor |
US7285503B2 (en) * | 2004-06-21 | 2007-10-23 | Applied Materials, Inc. | Hermetic cap layers formed on low-k films by plasma enhanced chemical vapor deposition |
-
2005
- 2005-07-15 KR KR1020050064490A patent/KR20070009329A/ko not_active Application Discontinuation
-
2006
- 2006-06-28 JP JP2006178784A patent/JP2007027710A/ja active Pending
- 2006-07-12 US US11/484,934 patent/US20070015319A1/en not_active Abandoned
- 2006-07-14 TW TW095125847A patent/TW200707757A/zh unknown
- 2006-07-17 CN CNA2006100993289A patent/CN1897248A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
CN1897248A (zh) | 2007-01-17 |
JP2007027710A (ja) | 2007-02-01 |
US20070015319A1 (en) | 2007-01-18 |
KR20070009329A (ko) | 2007-01-18 |
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