TW200701404A - Method for fabricating semiconductor device with deep opening - Google Patents

Method for fabricating semiconductor device with deep opening

Info

Publication number
TW200701404A
TW200701404A TW094147248A TW94147248A TW200701404A TW 200701404 A TW200701404 A TW 200701404A TW 094147248 A TW094147248 A TW 094147248A TW 94147248 A TW94147248 A TW 94147248A TW 200701404 A TW200701404 A TW 200701404A
Authority
TW
Taiwan
Prior art keywords
openings
semiconductor device
deep opening
fabricating semiconductor
insulation layer
Prior art date
Application number
TW094147248A
Other languages
English (en)
Other versions
TWI287271B (en
Inventor
Yong-Tae Cho
Hae-Jung Lee
Sang-Hoon Cho
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020050058886A external-priority patent/KR100668508B1/ko
Priority claimed from KR1020050058893A external-priority patent/KR100677772B1/ko
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200701404A publication Critical patent/TW200701404A/zh
Application granted granted Critical
Publication of TWI287271B publication Critical patent/TWI287271B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
TW094147248A 2005-06-30 2005-12-29 Method for fabricating semiconductor device with deep opening TWI287271B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050058886A KR100668508B1 (ko) 2005-06-30 2005-06-30 깊은 콘택홀을 갖는 반도체소자의 제조 방법
KR1020050058893A KR100677772B1 (ko) 2005-06-30 2005-06-30 깊은 콘택홀을 갖는 반도체소자의 제조 방법

Publications (2)

Publication Number Publication Date
TW200701404A true TW200701404A (en) 2007-01-01
TWI287271B TWI287271B (en) 2007-09-21

Family

ID=37590162

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094147248A TWI287271B (en) 2005-06-30 2005-12-29 Method for fabricating semiconductor device with deep opening

Country Status (3)

Country Link
US (1) US20070004194A1 (zh)
JP (1) JP2007013081A (zh)
TW (1) TWI287271B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100760632B1 (ko) * 2006-03-03 2007-09-20 삼성전자주식회사 커패시터 형성 방법
KR20120028509A (ko) * 2010-09-15 2012-03-23 삼성전자주식회사 커패시터 형성 방법 및 이를 이용한 반도체 장치 제조 방법
CN102856276B (zh) * 2011-06-27 2015-08-12 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
US9183977B2 (en) * 2012-04-20 2015-11-10 Infineon Technologies Ag Method for fabricating a coil by way of a rounded trench
CN114628323B (zh) * 2022-05-05 2023-01-24 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468684A (en) * 1991-12-13 1995-11-21 Symetrix Corporation Integrated circuit with layered superlattice material and method of fabricating same
KR960009998B1 (ko) * 1992-06-08 1996-07-25 삼성전자 주식회사 반도체 메모리장치의 제조방법
JPH06209085A (ja) * 1992-07-23 1994-07-26 Texas Instr Inc <Ti> スタック形ｄｒａｍコンデンサ構造体とその製造方法
JPH0964179A (ja) * 1995-08-25 1997-03-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5567639A (en) * 1996-01-04 1996-10-22 Utron Technology Inc. Method of forming a stack capacitor of fin structure for DRAM cell
US5976986A (en) * 1996-08-06 1999-11-02 International Business Machines Corp. Low pressure and low power C12 /HC1 process for sub-micron metal etching
KR100246989B1 (ko) * 1996-09-09 2000-03-15 김영환 반도체소자의 캐패시터 형성방법
EP0895278A3 (de) * 1997-08-01 2000-08-23 Siemens Aktiengesellschaft Strukturierungsverfahren
KR100269323B1 (ko) * 1998-01-16 2000-10-16 윤종용 반도체장치의백금막식각방법
US6232171B1 (en) * 1999-01-11 2001-05-15 Promos Technology, Inc. Technique of bottle-shaped deep trench formation
US6451703B1 (en) * 2000-03-10 2002-09-17 Applied Materials, Inc. Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas
US6362109B1 (en) * 2000-06-02 2002-03-26 Applied Materials, Inc. Oxide/nitride etching having high selectivity to photoresist
JP2002190518A (ja) * 2000-12-20 2002-07-05 Mitsubishi Electric Corp 半導体装置とその製造方法
KR100388682B1 (ko) * 2001-03-03 2003-06-25 삼성전자주식회사 반도체 메모리 장치의 스토리지 전극층 및 그 형성방법
JP3903730B2 (ja) * 2001-04-04 2007-04-11 松下電器産業株式会社 エッチング方法
JP3976703B2 (ja) * 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
KR100538098B1 (ko) * 2003-08-18 2005-12-21 삼성전자주식회사 개선된 구조적 안정성 및 향상된 캐패시턴스를 갖는캐패시터를 포함하는 반도체 장치 및 그 제조 방법
US6846744B1 (en) * 2003-10-17 2005-01-25 Nanya Technology Corp. Method of fabricating a bottle shaped deep trench for trench capacitor DRAM devices
KR100555533B1 (ko) * 2003-11-27 2006-03-03 삼성전자주식회사 실린더형 스토리지 전극을 포함하는 반도체 메모리 소자및 그 제조방법
KR100553835B1 (ko) * 2004-01-26 2006-02-24 삼성전자주식회사 캐패시터 및 그 제조 방법

Also Published As

Publication number Publication date
JP2007013081A (ja) 2007-01-18
TWI287271B (en) 2007-09-21
US20070004194A1 (en) 2007-01-04

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees