TW200627577A - Method for forming trench gate dielectric layer - Google Patents

Method for forming trench gate dielectric layer

Info

Publication number
TW200627577A
TW200627577A TW094101265A TW94101265A TW200627577A TW 200627577 A TW200627577 A TW 200627577A TW 094101265 A TW094101265 A TW 094101265A TW 94101265 A TW94101265 A TW 94101265A TW 200627577 A TW200627577 A TW 200627577A
Authority
TW
Taiwan
Prior art keywords
gate dielectric
dielectric layer
trench gate
trench
forming trench
Prior art date
Application number
TW094101265A
Other languages
English (en)
Other versions
TWI240989B (en
Inventor
Min-San Huang
Hann-Jye Hsu
Leon Lai
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW094101265A priority Critical patent/TWI240989B/zh
Priority to US11/161,177 priority patent/US7205217B2/en
Application granted granted Critical
Publication of TWI240989B publication Critical patent/TWI240989B/zh
Publication of TW200627577A publication Critical patent/TW200627577A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28238Making the insulator with sacrificial oxide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
TW094101265A 2005-01-17 2005-01-17 Method for forming trench gate dielectric layer TWI240989B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094101265A TWI240989B (en) 2005-01-17 2005-01-17 Method for forming trench gate dielectric layer
US11/161,177 US7205217B2 (en) 2005-01-17 2005-07-26 Method for forming trench gate dielectric layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094101265A TWI240989B (en) 2005-01-17 2005-01-17 Method for forming trench gate dielectric layer

Publications (2)

Publication Number Publication Date
TWI240989B TWI240989B (en) 2005-10-01
TW200627577A true TW200627577A (en) 2006-08-01

Family

ID=36684466

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094101265A TWI240989B (en) 2005-01-17 2005-01-17 Method for forming trench gate dielectric layer

Country Status (2)

Country Link
US (1) US7205217B2 (zh)
TW (1) TWI240989B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738008A (zh) * 2012-07-04 2012-10-17 上海宏力半导体制造有限公司 沟槽场效应晶体管的制作方法
CN110391246A (zh) * 2019-07-22 2019-10-29 上海华力微电子有限公司 一种提高sonos有源区边角圆度的方法

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JP2007250855A (ja) * 2006-03-16 2007-09-27 Elpida Memory Inc 半導体装置及びその製造方法
KR100994891B1 (ko) * 2007-02-26 2010-11-16 주식회사 하이닉스반도체 반도체 메모리 소자의 소자 분리막 형성 방법
CN102280384A (zh) * 2011-07-05 2011-12-14 上海宏力半导体制造有限公司 功率沟槽式金属氧化物半导体场效应晶体管制作工艺
JP2013232533A (ja) * 2012-04-27 2013-11-14 Rohm Co Ltd 半導体装置および半導体装置の製造方法
CN102945793A (zh) * 2012-12-03 2013-02-27 上海集成电路研发中心有限公司 一种外延生长锗硅应力层的预清洗方法
KR20140099743A (ko) 2013-02-04 2014-08-13 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN105575809B (zh) * 2014-10-10 2019-02-01 中芯国际集成电路制造(上海)有限公司 一种沟槽式mosfet的制造方法
CN112802742A (zh) * 2021-03-24 2021-05-14 上海华虹宏力半导体制造有限公司 半导体器件的制造方法
CN113643997A (zh) * 2021-07-30 2021-11-12 天津环鑫科技发展有限公司 一种沟槽形貌监控方法、结构器件
CN114005756A (zh) * 2021-10-29 2022-02-01 上海华虹宏力半导体制造有限公司 屏蔽栅沟槽功率器件的制造方法

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US20030027403A1 (en) * 2001-08-03 2003-02-06 Macronix International Co., Ltd. Method for forming sacrificial oxide layer
US6503815B1 (en) * 2001-08-03 2003-01-07 Macronix International Co., Ltd. Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation
US20030040189A1 (en) * 2001-08-22 2003-02-27 Ping-Yi Chang Shallow trench isolation fabrication
US6800899B2 (en) * 2001-08-30 2004-10-05 Micron Technology, Inc. Vertical transistors, electrical devices containing a vertical transistor, and computer systems containing a vertical transistor
TW511186B (en) 2001-10-09 2002-11-21 Silicon Integrated Sys Corp Manufacturing method of shallow trench isolation structure
US6808748B2 (en) * 2003-01-23 2004-10-26 Applied Materials, Inc. Hydrogen assisted HDP-CVD deposition process for aggressive gap-fill technology
US6967136B2 (en) * 2003-08-01 2005-11-22 International Business Machines Corporation Method and structure for improved trench processing
US6855588B1 (en) * 2003-10-07 2005-02-15 United Microelectronics Corp. Method of fabricating a double gate MOSFET device
JP2005166700A (ja) * 2003-11-28 2005-06-23 Toshiba Corp 半導体装置及びその製造方法
KR100513405B1 (ko) * 2003-12-16 2005-09-09 삼성전자주식회사 핀 트랜지스터의 형성 방법
US6974743B2 (en) * 2004-02-02 2005-12-13 Infineon Technologies Ag Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates
US7067377B1 (en) * 2004-03-30 2006-06-27 Fasl Llc Recessed channel with separated ONO memory device
US7176105B2 (en) * 2004-06-01 2007-02-13 Applied Materials, Inc. Dielectric gap fill with oxide selectively deposited over silicon liner
KR100572329B1 (ko) * 2004-09-07 2006-04-18 삼성전자주식회사 소자분리막 형성 방법 및 이를 이용한 반도체 소자 형성방법
US7442609B2 (en) * 2004-09-10 2008-10-28 Infineon Technologies Ag Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
KR100650846B1 (ko) * 2004-10-06 2006-11-27 에스티마이크로일렉트로닉스 엔.브이. 플래시 메모리 소자의 소자 분리막 형성방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738008A (zh) * 2012-07-04 2012-10-17 上海宏力半导体制造有限公司 沟槽场效应晶体管的制作方法
CN110391246A (zh) * 2019-07-22 2019-10-29 上海华力微电子有限公司 一种提高sonos有源区边角圆度的方法

Also Published As

Publication number Publication date
US20060160306A1 (en) 2006-07-20
TWI240989B (en) 2005-10-01
US7205217B2 (en) 2007-04-17

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