TW200627561A - Chip package - Google Patents

Chip package

Info

Publication number
TW200627561A
TW200627561A TW094101502A TW94101502A TW200627561A TW 200627561 A TW200627561 A TW 200627561A TW 094101502 A TW094101502 A TW 094101502A TW 94101502 A TW94101502 A TW 94101502A TW 200627561 A TW200627561 A TW 200627561A
Authority
TW
Taiwan
Prior art keywords
chip
pads
interconnection structure
chip package
panel
Prior art date
Application number
TW094101502A
Other languages
English (en)
Other versions
TWI255518B (en
Inventor
Chi-Hsing Hsu
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW094101502A priority Critical patent/TWI255518B/zh
Priority to US11/111,303 priority patent/US7230332B2/en
Application granted granted Critical
Publication of TWI255518B publication Critical patent/TWI255518B/zh
Publication of TW200627561A publication Critical patent/TW200627561A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094101502A 2005-01-19 2005-01-19 Chip package TWI255518B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094101502A TWI255518B (en) 2005-01-19 2005-01-19 Chip package
US11/111,303 US7230332B2 (en) 2005-01-19 2005-04-20 Chip package with embedded component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094101502A TWI255518B (en) 2005-01-19 2005-01-19 Chip package

Publications (2)

Publication Number Publication Date
TWI255518B TWI255518B (en) 2006-05-21
TW200627561A true TW200627561A (en) 2006-08-01

Family

ID=36683045

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094101502A TWI255518B (en) 2005-01-19 2005-01-19 Chip package

Country Status (2)

Country Link
US (1) US7230332B2 (zh)
TW (1) TWI255518B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677062B (zh) * 2012-12-11 2019-11-11 南韓商三星電機股份有限公司 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI253701B (en) * 2005-01-21 2006-04-21 Via Tech Inc Bump-less chip package
JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
TWI292947B (en) 2006-06-20 2008-01-21 Unimicron Technology Corp The structure of embedded chip packaging and the fabricating method thereof
US8153472B2 (en) 2006-06-20 2012-04-10 Unimicron Technology Corp. Embedded chip package process
JP5326269B2 (ja) * 2006-12-18 2013-10-30 大日本印刷株式会社 電子部品内蔵配線板、及び電子部品内蔵配線板の放熱方法
TWI335652B (en) * 2007-04-04 2011-01-01 Unimicron Technology Corp Stacked packing module
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
US8482136B2 (en) * 2009-12-29 2013-07-09 Nxp B.V. Fan-out chip scale package
JP5636265B2 (ja) * 2010-11-15 2014-12-03 新光電気工業株式会社 半導体パッケージ及びその製造方法
KR20120053332A (ko) * 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
JP5703010B2 (ja) * 2010-12-16 2015-04-15 新光電気工業株式会社 半導体パッケージ及びその製造方法
JP5903337B2 (ja) * 2012-06-08 2016-04-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
US20150206855A1 (en) * 2014-01-22 2015-07-23 Mediatek Inc. Semiconductor package
KR102268388B1 (ko) 2014-08-11 2021-06-23 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US9837484B2 (en) * 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6507119B2 (en) * 2000-11-30 2003-01-14 Siliconware Precision Industries Co., Ltd. Direct-downset flip-chip package assembly and method of fabricating the same
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6770965B2 (en) * 2000-12-28 2004-08-03 Ngk Spark Plug Co., Ltd. Wiring substrate using embedding resin
US7176055B2 (en) * 2001-11-02 2007-02-13 Matsushita Electric Industrial Co., Ltd. Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
TWI251916B (en) * 2003-08-28 2006-03-21 Phoenix Prec Technology Corp Semiconductor assembled heat sink structure for embedding electronic components
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
TWI225670B (en) * 2003-12-09 2004-12-21 Advanced Semiconductor Eng Packaging method of multi-chip module
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
KR100645643B1 (ko) * 2004-07-14 2006-11-15 삼성전기주식회사 수동소자칩 내장형의 인쇄회로기판의 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677062B (zh) * 2012-12-11 2019-11-11 南韓商三星電機股份有限公司 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法

Also Published As

Publication number Publication date
US7230332B2 (en) 2007-06-12
US20060157847A1 (en) 2006-07-20
TWI255518B (en) 2006-05-21

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