TW200625001A - Semiconductor device with scattering bar adjacent conductive lines - Google Patents
Semiconductor device with scattering bar adjacent conductive linesInfo
- Publication number
- TW200625001A TW200625001A TW094119472A TW94119472A TW200625001A TW 200625001 A TW200625001 A TW 200625001A TW 094119472 A TW094119472 A TW 094119472A TW 94119472 A TW94119472 A TW 94119472A TW 200625001 A TW200625001 A TW 200625001A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- conductive lines
- adjacent conductive
- bar adjacent
- scattering bar
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 5
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 238000001459 lithography Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/867,076 US7339272B2 (en) | 2004-06-14 | 2004-06-14 | Semiconductor device with scattering bars adjacent conductive lines |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200625001A true TW200625001A (en) | 2006-07-16 |
TWI291595B TWI291595B (en) | 2007-12-21 |
Family
ID=35460956
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094119472A TWI291595B (en) | 2004-06-14 | 2005-06-13 | Semiconductor device with scattering bar adjacent conductive lines |
Country Status (4)
Country | Link |
---|---|
US (1) | US7339272B2 (zh) |
JP (1) | JP2006005350A (zh) |
CN (1) | CN100378983C (zh) |
TW (1) | TWI291595B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9268209B2 (en) | 2012-05-14 | 2016-02-23 | United Microelectronics Corp. | Mask and method of forming pattern by using the same |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9093448B2 (en) | 2008-11-25 | 2015-07-28 | Lord Corporation | Methods for protecting a die surface with photocurable materials |
WO2010068488A1 (en) * | 2008-11-25 | 2010-06-17 | Lord Corporation | Methods for protecting a die surface with photocurable materials |
CN101644889B (zh) * | 2009-06-24 | 2012-12-12 | 上海宏力半导体制造有限公司 | 用于提高焦深的光刻散射条及其制造方法 |
US8546048B2 (en) | 2010-10-29 | 2013-10-01 | Skyworks Solutions, Inc. | Forming sloped resist, via, and metal conductor structures using banded reticle structures |
KR101195267B1 (ko) * | 2010-12-29 | 2012-11-14 | 에스케이하이닉스 주식회사 | 미세 패턴 형성 방법 |
CN105093809B (zh) * | 2014-05-22 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | 增强光刻工艺窗口的光学邻近修正方法 |
US10388644B2 (en) * | 2016-11-29 | 2019-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing conductors and semiconductor device which includes conductors |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US92260A (en) * | 1869-07-06 | Improvement in electro-magnetic at | ||
US5476817A (en) * | 1994-05-31 | 1995-12-19 | Texas Instruments Incorporated | Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers |
JPH0845936A (ja) * | 1994-05-31 | 1996-02-16 | Texas Instr Inc <Ti> | ダミーリードを用いた高速lsi半導体装置およびその信頼性改善方法 |
KR0172561B1 (ko) * | 1995-06-23 | 1999-03-30 | 김주용 | 노강 마스크의 근접 효과 억제방법 |
JP3887035B2 (ja) * | 1995-12-28 | 2007-02-28 | 株式会社東芝 | 半導体装置の製造方法 |
US5798298A (en) * | 1996-02-09 | 1998-08-25 | United Microelectronics Corporation | Method of automatically generating dummy metals for multilevel interconnection |
JPH10247664A (ja) * | 1997-03-04 | 1998-09-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP3638778B2 (ja) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
US6245662B1 (en) * | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
US6258715B1 (en) * | 1999-01-11 | 2001-07-10 | Taiwan Semiconductor Manufacturing Company | Process for low-k dielectric with dummy plugs |
US6259115B1 (en) * | 1999-03-04 | 2001-07-10 | Advanced Micro Devices, Inc. | Dummy patterning for semiconductor manufacturing processes |
JP2000286263A (ja) * | 1999-03-29 | 2000-10-13 | Nec Corp | 半導体装置及びその製造方法 |
JP2000323372A (ja) * | 1999-05-07 | 2000-11-24 | Nikon Corp | 近接効果補正方法及びそれを用いた半導体素子製造方法 |
US6281583B1 (en) * | 1999-05-12 | 2001-08-28 | International Business Machines Corporation | Planar integrated circuit interconnect |
US6596624B1 (en) * | 1999-07-31 | 2003-07-22 | International Business Machines Corporation | Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier |
US6610592B1 (en) * | 2000-04-24 | 2003-08-26 | Taiwan Semiconductor Manufacturing Company | Method for integrating low-K materials in semiconductor fabrication |
TW447082B (en) * | 2000-09-07 | 2001-07-21 | United Microelectronics Corp | Method for increasing the line width window in a semiconductor process |
US6638863B2 (en) * | 2001-04-24 | 2003-10-28 | Acm Research, Inc. | Electropolishing metal layers on wafers having trenches or vias with dummy structures |
JP3575448B2 (ja) * | 2001-08-23 | 2004-10-13 | セイコーエプソン株式会社 | 半導体装置 |
CN1202443C (zh) * | 2001-10-10 | 2005-05-18 | 台湾积体电路制造股份有限公司 | 光罩组合及接触洞的制造方法 |
US6582974B2 (en) | 2001-11-15 | 2003-06-24 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming a dual damascene aperture while employing a peripherally localized intermediate etch stop layer |
US7363099B2 (en) * | 2002-06-07 | 2008-04-22 | Cadence Design Systems, Inc. | Integrated circuit metrology |
JP4005873B2 (ja) * | 2002-08-15 | 2007-11-14 | 株式会社東芝 | 半導体装置 |
US6958542B2 (en) * | 2002-09-03 | 2005-10-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20050110151A1 (en) * | 2002-11-15 | 2005-05-26 | Itaru Tamura | Semiconductor device |
US6833622B1 (en) * | 2003-02-27 | 2004-12-21 | Cypress Semiconductor Corp. | Semiconductor topography having an inactive region formed from a dummy structure pattern |
US7015582B2 (en) * | 2003-04-01 | 2006-03-21 | International Business Machines Corporation | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics |
US7423304B2 (en) * | 2003-12-05 | 2008-09-09 | Sandisck 3D Llc | Optimization of critical dimensions and pitch of patterned features in and above a substrate |
US20050253268A1 (en) * | 2004-04-22 | 2005-11-17 | Shao-Ta Hsu | Method and structure for improving adhesion between intermetal dielectric layer and cap layer |
-
2004
- 2004-06-14 US US10/867,076 patent/US7339272B2/en active Active
-
2005
- 2005-06-13 TW TW094119472A patent/TWI291595B/zh active
- 2005-06-13 JP JP2005172960A patent/JP2006005350A/ja active Pending
- 2005-06-14 CN CNB2005100767762A patent/CN100378983C/zh active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9268209B2 (en) | 2012-05-14 | 2016-02-23 | United Microelectronics Corp. | Mask and method of forming pattern by using the same |
Also Published As
Publication number | Publication date |
---|---|
CN1722426A (zh) | 2006-01-18 |
TWI291595B (en) | 2007-12-21 |
US20050277067A1 (en) | 2005-12-15 |
CN100378983C (zh) | 2008-04-02 |
JP2006005350A (ja) | 2006-01-05 |
US7339272B2 (en) | 2008-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200625001A (en) | Semiconductor device with scattering bar adjacent conductive lines | |
DE502006007549D1 (de) | Verfahren zum herstellen einer vielzahl von einen windelhauptteil und daran angefügte vordere und hintere windelseitenteile aufweisenden inkontinenzwegwerfwindeln | |
ATE505280T1 (de) | Feingusskernanordnung | |
ATE522924T1 (de) | Textilschicht-anordnung, textilschicht-array und verfahren zum herstellen einer textilschicht- anordnung | |
TW200721253A (en) | Method of forming pitch multipled contacts | |
FR2868466B1 (fr) | Outil de fond de type a propagation et a resistivite laterale combine | |
TW200733250A (en) | Process for forming an electronic device including a fin-type structure | |
BRPI0920344A2 (pt) | método de produção de eletrodo frontal de dispositivo fotovoltaico tendo superfície gravada e dispositivo fotovoltaico correspondente. | |
WO2009017982A3 (en) | Methods for device fabrication using pitch reduction and associated structures | |
TW200715556A (en) | Electronic device with a gate electrode having at least two portions and a process for forming the electronic device | |
FR2868628B1 (fr) | Generateur de nombres aleatoires et procede de production de nombres aleatoires | |
EP1628657A4 (en) | METHOD OF TREATING DISEASES USING HSP90 INHIBITING AGENTS IN CONJUNCTION WITH PLATINUM COORDINATION COMPLEXES | |
FR2893954B1 (fr) | Acier pour outillage a chaud, et piece realisee en cet acier et son procede de fabrication | |
ZA200410053B (en) | Method for improving efficiencies in livestock production | |
WO2008114341A1 (ja) | 半導体装置およびその製造方法 | |
TW200735189A (en) | Method for fabricating semiconductor device with dual poly-recess gate | |
AU2003297643A8 (en) | Methods for improving secondary metabolite production in fungi | |
DE60216825D1 (de) | Verfahren zum herstellen einer im wesentlichen transparenten elektrisch leitenden schichtanordnung | |
DE60305948D1 (de) | Verfahren zum herstellen eines kaltverformten differentialgehäuses mit integriertem zahnkranz | |
WO2011071372A3 (en) | Electro-optical device, electrode therefore, and method and apparatus of manufacturing an electrode and the electro-optical device provided therewith | |
TW200943397A (en) | Semiconductor device and method of fabricating the same | |
TW200943414A (en) | Semiconductor device and method of fabricating the same | |
AU2003247566A1 (en) | Method for selectively treating two producing intervals in a single trip | |
TW200737319A (en) | Photomask making method and semiconductor device manufacturing method | |
EP1635217A4 (en) | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR GENERATING MASK PATTERN DATA |