TW200614476A - Package substrate with nsmd pads - Google Patents

Package substrate with nsmd pads

Info

Publication number
TW200614476A
TW200614476A TW093132002A TW93132002A TW200614476A TW 200614476 A TW200614476 A TW 200614476A TW 093132002 A TW093132002 A TW 093132002A TW 93132002 A TW93132002 A TW 93132002A TW 200614476 A TW200614476 A TW 200614476A
Authority
TW
Taiwan
Prior art keywords
nsmd
pads
metal layer
nsmd pads
package substrate
Prior art date
Application number
TW093132002A
Other languages
Chinese (zh)
Other versions
TWI251923B (en
Inventor
Chia-Hui Chu
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093132002A priority Critical patent/TWI251923B/en
Application granted granted Critical
Publication of TWI251923B publication Critical patent/TWI251923B/en
Publication of TW200614476A publication Critical patent/TW200614476A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A package substrate with NSMD (Non-Solder Mask Defined) pads mainly includes a substrate, a metal layer, a plurality of NSMD pads and a solder mask. The metal layer and the NSMD pads are formed on a same surface of the substrate. The metal layer includes a plurality of imitative-NSMD pads formed. The solder mask partially covers the metal layer and has a plurality of first openings and a plurality of second openings to respectively expose the imitative-NSMD pads and the NSMD pads for avoiding cold joint during connecting bumps.
TW093132002A 2004-10-21 2004-10-21 Package substrate with NSMD pads TWI251923B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093132002A TWI251923B (en) 2004-10-21 2004-10-21 Package substrate with NSMD pads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093132002A TWI251923B (en) 2004-10-21 2004-10-21 Package substrate with NSMD pads

Publications (2)

Publication Number Publication Date
TWI251923B TWI251923B (en) 2006-03-21
TW200614476A true TW200614476A (en) 2006-05-01

Family

ID=37453816

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093132002A TWI251923B (en) 2004-10-21 2004-10-21 Package substrate with NSMD pads

Country Status (1)

Country Link
TW (1) TWI251923B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI656583B (en) * 2014-10-13 2019-04-11 美商艾馬克科技公司 Patterned liners used to create virtual solder masks in wafer level wafer size packages

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9935038B2 (en) 2012-04-11 2018-04-03 Taiwan Semiconductor Manufacturing Company Semiconductor device packages and methods

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI656583B (en) * 2014-10-13 2019-04-11 美商艾馬克科技公司 Patterned liners used to create virtual solder masks in wafer level wafer size packages

Also Published As

Publication number Publication date
TWI251923B (en) 2006-03-21

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