TW200701400A - Method for processing substrate - Google Patents

Method for processing substrate

Info

Publication number
TW200701400A
TW200701400A TW095117361A TW95117361A TW200701400A TW 200701400 A TW200701400 A TW 200701400A TW 095117361 A TW095117361 A TW 095117361A TW 95117361 A TW95117361 A TW 95117361A TW 200701400 A TW200701400 A TW 200701400A
Authority
TW
Taiwan
Prior art keywords
bond pads
planarization layer
filter region
substrate
scribe lines
Prior art date
Application number
TW095117361A
Other languages
Chinese (zh)
Other versions
TWI312552B (en
Inventor
Fu-Tien Weng
Yu-Kung Hsiao
Hung-Jen Hsu
Yi-Ming Dai
Chin-Chen Kuo
Te Fu Tseng
Chihkung Chang
Jack Deng
Chung Sheng Hsiung
Biijunq Chang
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/156,794 external-priority patent/US7507598B2/en
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200701400A publication Critical patent/TW200701400A/en
Application granted granted Critical
Publication of TWI312552B publication Critical patent/TWI312552B/en

Links

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Dicing (AREA)

Abstract

A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines arranged around the filter region and the bond pads. A first planarization layer is formed above the substrate. The planarization layer has a substantially flat top surface overlying the filter region, the bond pads and the scribe lines. At least one color resist layer is formed over the first planarization layer and within the filter region while the first planarization layer covers the bond pads and the scribe lines.
TW95117361A 2005-06-20 2006-05-16 Method for processing substrate TWI312552B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/156,794 US7507598B2 (en) 2003-06-06 2005-06-20 Image sensor fabrication method and structure

Publications (2)

Publication Number Publication Date
TW200701400A true TW200701400A (en) 2007-01-01
TWI312552B TWI312552B (en) 2009-07-21

Family

ID=37583604

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95117361A TWI312552B (en) 2005-06-20 2006-05-16 Method for processing substrate

Country Status (2)

Country Link
CN (1) CN1885526A (en)
TW (1) TWI312552B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015170702A (en) * 2014-03-06 2015-09-28 ソニー株式会社 Solid state imaging apparatus, manufacturing method thereof and electronic apparatus
US9252179B2 (en) * 2014-06-13 2016-02-02 Visera Technologies Company Limited Image sensor structures

Also Published As

Publication number Publication date
CN1885526A (en) 2006-12-27
TWI312552B (en) 2009-07-21

Similar Documents

Publication Publication Date Title
TW200739854A (en) Substrate structure having solder mask layer and process for making the same
TW200744218A (en) Semiconductor device and method of manufacturing the same
TW200739972A (en) Light-emitting device and method for manufacturing the same
SG144121A1 (en) Nitride semiconductor substrate and manufacturing method thereof
WO2009142391A3 (en) Light-emitting device package and method of manufacturing the same
TW200628574A (en) Adhesion promoter, electroactive layer and electroactive device comprising same, and method
TW200737376A (en) Chip package and fabricating method thereof
WO2011087591A3 (en) Multiple surface finishes for microelectronic package substrates
SG165231A1 (en) Semiconductor die and method of forming noise absorbing regions between thvs in peripheral region of the die
TW200610012A (en) Method of planarizing a semiconductor substrate
EP2237335A3 (en) White-light light emitting chips and fabrication methods thereof
WO2008017472A3 (en) Method for the production of a porous, ceramic surface layer
TW200612500A (en) Substrate with patterned conductive layer
TWI319893B (en) Nitride semiconductor substrate, method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate
TW200705677A (en) Method of manufacturing thin film transistor substrate
TW200719468A (en) Package, package module and manufacturing method of the package
WO2008152945A1 (en) Semiconductor light-emitting device and method for manufacturing the same
TW200735293A (en) Semiconductor device, substrate and manufacturing method thereof
TW200743191A (en) Chip structure and fabricating process thereof
WO2003083427A3 (en) Corrugated diaphragm
TW200729499A (en) Method of forming a semiconductor device
TW200701400A (en) Method for processing substrate
TW200733269A (en) Semiconductor device and manufacturing method for the same
WO2009071645A3 (en) Silicon-ceramic composite substrate
TW200707605A (en) Substrate for manufacturing semiconductor device, semiconductor device manufacturing method

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees