TW200531217A - Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method - Google Patents

Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method Download PDF

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TW200531217A
TW200531217A TW094105216A TW94105216A TW200531217A TW 200531217 A TW200531217 A TW 200531217A TW 094105216 A TW094105216 A TW 094105216A TW 94105216 A TW94105216 A TW 94105216A TW 200531217 A TW200531217 A TW 200531217A
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gate
semiconductor substrate
channel region
trench
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TW094105216A
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TWI287856B (en
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Bartlomiej Jan Pawlak
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Imec Inter Uni Micro Electr
Koninkl Philips Electronics Nv
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

200531217 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種製造半導體元件的方法，半導體元 件係包含雙閘極（duai gate)場效電晶體，在該方法中，具 ^表面之矽的半導體基體係設有第一導電類型之源極區域 與汲極區域、介於源極區域與汲極區域之間且相反於第— =電類型的第二導電類型之通道區域、藉由第一閘極介電 質與通道區域分離且位於通道區域的一側之第—閘極區 域、及藉由第二閘極介電質與通道區域分離且位於通道區 :的相對側之第二閘極區域’其中，二個閘極區域係形 半導體基體中所形成之溝槽内。雙閘極結構之運用 二：使用以降低當該電晶體為不導通時之茂漏電流，且 二”：晶體為導通時之驅動電流。這些方面係由於 的Γ步的小型化、較低的電力使用、與較佳
有關連……本發明亦關於 【先前技術】 6…如上述段落所提及之方法係已知於美國專利第 6,⑽，U7B2號中，其已於細3年㈠=專利第 -種設置雙閘極電晶體於溝槽中之 A 口。其卜 如：第Ι2β圖與說明欄 /係被描述（參閱例 顿 7 至 14)。一 個 P彳 r~ 溝槽之底部，…個_域係形成：=形成二 逼區，為插入於該二個間極區域之間成於溝槽之頂部，通 習知的方法之—個缺點係在於 八為相當稷雜且需要 6 200531217 現 需 相當多的步驟。因此，仍然存在對於一種可容易納入於 今與未來的CMOS技術之形成雙閘極電晶體的方法之 求0 因此，本發明之一個目的係避免上述的缺點，且提出 -：用於製造雙閘極電晶體的方法，其為相當簡單且極為 相谷於現今與未來的CMOS技術。 ^輯成此，於上述段落所描述類型之方法的特徵在於： 弟一間極區域為形成於第一溝槽内，而第 成於第二溝槽内，诵、蓄P A及丄續 匕3為升y 導…夕: 道£域係由第一與第二溝槽之間的半 二 ^分所形成’且源極與沒極區域係形成於半導 體基體之表面。此種方法係相當簡單且極為相容；= ⑽技術及非常可能相容於未來的、= :“體係一方面為垂直的’因為通道區域中之通 迢為形成於垂直半導體基體之表面的域中之通
:?閘r電晶體係另-方面為水平的，因為源:與::： i疋以白用的方式而形成於半導體基體之 個相=:之雙閘極係對於通道提供更有效的：。二 根據“明之方法的一個較佳實施例 體基體之表面係形成二個平行的溝槽，其壁^亥= 電層且為填充一導電性材料，其係藉著沉 ： 丰導體基體上，該半導體基體之表面的 曰於该 由化學機械拋光（p〇nshing)而移除。、之部分係藉 標準的CMOS技術。該導電性材料係較佳為::為::於 7 200531217 …材料係可用二個階段來形成，舉例而 -石夕層及藉著沉積一金屬層(例如：錄層)於該石夕層之二積 且隨後為低溫的it火（麵eal)’例如：數分鐘於攝& _戶4 其中，矽化鎳係被形成而提供高的導電性。 X， 於另-個實施例中，源極與沒極區域係藉著沉 (Μη"11—)的光罩層於該半導體基體之表面上而开^ 條狀的光罩層係橋接該等溝槽被形成或待形成於乂 ， 個區域，其後，第-導電類型的摻雜質被引入至；導體； 體於該條狀的光罩層之二側。較佳而言，源極與汲 係在该等溝槽被形成且填充具 π W守屯材枓/金屬之德 成。在根據本發明之一種方法中 ’
技二以麵極與沒極區域。低溫之所謂的固態 J Γ ltaxy)再生長（regr〇w賴程係可被運用以允 :午-…聚積㈣et)。於運用接面的高 製程I通道及源極與 於另一個較佳實施例中，二個 s 半導體基體中且彼此鄰接u电曰曰體係形成於 導體基體中，該三個=之=:由形成三個溝槽於該半 , 4的溝槽係形成該二個雙閘 極電晶體之共用的閘極區域。 係以亦為非常緊凑之簡單方^此方式’例如—個反相器 雔門p… 式而形成。此係需要：該二個 I !!; 係形成作為一個η"晶體而另-者 ^成作Κ固Ρηρ電晶體。在根據本發明之方法中，後 W4為該源極與汲極區域係均為形成於半導 8 200531217 體基體之表面。此外，該二個電晶體之一者的通道區域係 可藉由局部植入於半導體基體之表面而為設有另一種（即， 相反的）導電類型。 車乂佳而s ’雙閘極電晶體之源極與汲極區域係藉由另 • 外的溝槽而與相對於通道區域的一側之半導體基體分離。 本發明更關於一種半導體元件，其包含一個雙閘極電 晶體，且具有一個具有表面之矽的半導體基體、第一導電 類型之源極區域與汲極區域、介於源極區域與汲極區域之 響間且相反於第-導電類型的一第二導電類型之通道區域、 藉由第一閘極介電質與通道區域分離且位於通道區域的一 側之第閘極區域、及藉由第二閘極介電質與通道區域分 離且位於通道區域的一相對側之第二閘極區域，且其中， 二個閘極區域係形成於半導體基體中所形成之溝槽内。根 據本發明’此種元件之特徵在於：第—閘極區域係形成於 第一溝槽而第二閉極區域係形成於第二溝槽，通道區域係 •由第一與第二溝槽之間的半導體基體之部分所形成，且源 極與汲極區域係形成於半導體基體之表面。 此種元件係極為適用於未來的CM0S lc且可運用根據 本發明之方法而易於獲得。較佳而言，此種元件係包含具 有共用的一個閘極之二個相鄰的雙閘極電晶體。 本發明之此等與其他層面係參照下文所述的實施例而 將為明瞭’該些實施例為關連於圖式來加以解讀。 【實施方式】 ' 該等圖式係僅為概略圖示的，而非為依比例所繪製， 9 200531217 為了更清楚起見，於i 圖式之子度方向之尺寸係特別放大。於不同 陰的部分係概括為給定相同的參考符號與相同的 體之“丄8:係根據本發明之_種具有雙閘極場效電晶 圓)，其係藉由根據本發1 )或俯視圖(第6至8 段。用於形成元件1()=方法而製k该70件的各種階 於一其細Μ 0之方法於此實例為起始（參閱第丨圖） 石夕之2A 、方此例包含（但非為必須）矽且因此亦形成 夕=體基體1的部分，且其於此實例係P型導電類型。 在此注忍的是：基* 區域u亦可為於相反莫’、可具有相反的導電類型。甚者’ 的石⑴ 相反導電類型（例如：分別為P型與η型） 的秒基板内之例如一彳㈤ 於此例中，基板/區竹】 ）UP型井）。再者， ,.^ 土 °°或11包含將形成電晶體之通道區域4
=式為相反的導電類型層12 (在此為n型卜此層係可藉 入、擴散或蟲晶（epitaxy)所形成。待形成之元件1〇泮 ::例為包含一(雙間極)Nm〇st)係在靠近其邊界實際為含 隔離區域12 ’堵如所謂的溝槽或石夕局部氧化㈣⑽）隔 離’前者於先進技術點為較佳的。實際上，元# 1〇破常 將是一積體電路（IC)，且因此含有許多電晶體。nm〇s及 PMOS型式之電晶體係均將為存在於cm〇s幻牛w中。 於半導體基體1之表面（參閱第2圖），光罩13係沉产 於半導體基體i之上，Μ要的話，光罩13係在分別^ 含-光阻或一介電質的介電材料之沉積後，藉由光刻術 (ph〇t〇llth〇graphy)所形成。於此實例，光罩丨3係被運用以 200531217 藉由各向異性（電漿）钱刻來形成三個溝槽7A、7B、7C。介 表各對相鄰溝槽7之間的半導體基體1之區域4、4，係將 形成其為待形成的雙閘極電晶體Ti、T2之通道區域。溝 槽7之深度係使得於區域U、12之間的pn接面被越過。 在光罩13之移除後（參閱第3圖），一介電層6〇係沉 積於半導體基體1之上，例如，其包含二氧化矽。層6〇 係可藉著化學氣相沉積（CVD)而形成，但熱氧化亦適用於 該目的。 乂隧後（芩閱第4圖），一導電層80 (於此例為一金屬層80) 係〉儿積於半導體基體！之上，於此實例，金屬層8〇係包 3鐫（W)。層8G之厚度係選取為使得溝槽7被完全填充。 系可藉由CVD或藉著類似蒸鑛或濺鐘之物理技術而 形成。 接著（參閱第5圖），半導體基體j係藉由化學機械拋 光而被平面化’俾使在溝槽7之外的金㈣⑼之區域被
移除。此層80之JL铃卹八#…^ 八餘4 /刀係形成其為待形成的二個電晶 體τι、T2之四個閘極@ [或（5A、5B)、（5A’、5B，）的材料 8， 其中’閘極區域5 B盘s a，说r > ,^ 5A係形成二個電晶體之一共用的閘 極區域。 其後（參閱第6圖，苴顧-一 μ · ，、颂不兀件1 〇之俯視圖），一光罩 之頂歹’二二^化石夕或氮化石夕所作成）係形成於半導體基體1 =個係條狀的，具有小的寬度且橋接其為待 幵，成的二個電晶髀々_ y 电日日體之一個通道區域4、4,。 隨後（參閱第7 ^ 。 相反於通道區域4、4,之導電類型 200531217 的“•“於此例為像是蝴⑻之p型的 體基體！中，在此為藉由離子植入 衣+導 體之源極與汲極區域2、3、2,以此方式，二個電晶 j 2、3’係被形成。 退火）之後，光罩Π®二、 杜植入（及其 ’、再ζ人被移除。於二個雙鬧炼雷曰_ ΤΙ、T2兩亜η知g ΛΑ z丄 丨口雙閑極電晶體 上2而要疋相反的結構之情 之一去A 1 中此表不该二個電晶體 ^ 者為ηριι型式而另一去炎 焱ϋ 者為ρηΡ型式，則一額外的植入 係被運用以產生該二個電曰 r 7植入 日日體之一者的通道區域。此外， 源極與汲極的形成係於該二 以八門从止抱+ 1U电日日體之一者被遮罩期間而 以分開的步驟來進行。 接著（參閱第8圖），於丨士者7丨 成以Μ , 、此只例，另一個溝槽17係被形 成為&繞该二個電晶體ΤΙ、T9 ，〆 2。此係以如同針對於溝槽7 之類似方式而作成。該另一 Μ ^ ^ ^ 個溝槽17係可為部分或完全 填充電氣絕緣材料，例如， π ^ 以如同上述針對於溝槽7之相 问的方式。
产後：1=由一預金屬介電質(例如，二氧化梦)之沉積、 二" 一接點金屬層(例如，紹)之沉積、同樣
Ik後為圖案化，接點區域
..^ ^為稭其形成的，而完成n-MOSFET 之衣仏。此等步驟係未顯 ..…、負不於圖式。假使閘極區域5係包 各夕日日矽作為導電材料 你1私 守’一種（自我對準）矽化物製程 係可進而被運用以接觸 ^ . 寺，原極與汲極區域2、3及閘極 區域5。 將為顯明的是， 對於熟悉此技藝人士 與修改係均為可行的 本备明係不限於本文所述之實例，且 而言’於本發明之範疇内的諸多變化 12 200531217 【圖式簡單說明】 第1至8圖係根據本發明之一種具有雙閘極場效電晶 體之半導體元件的截面圖（第1至5圖）或俯視圖（第6至8 圖），其係藉由根據本發明之方法而製造該元件的各種階 段。 【主要元件符號說明】 1 :半導體基體 2、 2 ’ ：源極區域
3、 3 ’ ：汲極區域 4、 4 ’ ：通道區域 5A、5B、5A’、5B，：閘極區域 6A、6B、6A，、6B，：閘極介電質 7、7A、7B、7C :溝槽 8 :導電材料 9、13 :光罩 1 0 :元件 1 1 ·基板 12 :隔離區域 1 7 :溝槽 60 :介電層 80 :導電層（金屬層） ΤΙ、T2 :雙閘極電晶體 13

Claims (1)

  1. 200531217 十、申請專利範圍： 1·一種製造半導體元件之方法，該半導體元件包含一 雙閘極場效電晶體，於該方法中，具有一表面之石夕的半導 • 體基體係設有一第一導電類型之一源極區域與一汲極區 • 域、介於邊源極區域與汲極區域之間且相反於第一導電類 型的一第二導電類型之一通道區域、藉由一第一閘極介電 質與該通道區域分離且位於該通道區域的一側之一第一閘 極區域、及藉由一第二閘極介電質與該通道區域分離且位 *於該通道區域的一相對側之一第二閘極區域，其中，二個 閘極區域係形成於該半導體基體中所形成之一溝槽内，其 特徵在於：該第一閘極區域係形成於一第一溝槽内，而第 二閘極區域係形成於一第二溝槽内，該通道區域係由該第 一與第二溝槽之間的半導體基體之部分所形成，且該源極 與沒極區域係形成於該半導體基體之表面。 2.如申請專利範圍第〗項之方法，其特徵在於二個平 行的溝槽係形成於該半導體基體之表面，其壁部係設有一 介電層且藉由沉積一導電層於該半導體基體之上而被填充 :導電性材料，於該半導體基體之表面的頂部上之部分係 It由化學機械抛光而被移除。 、3.如巾請專利範㈣丨項之方法，其特徵在於該源極 與汲極區域係藉由沉積一條狀的光罩層於該半導體基體之 表面上而被形成，該條狀的光罩層係橋接該等溝槽被形成 或疋待形成於其中之二個區域，其後，該第_導電類型的 払減貝被引入至該半導體基體，於該條狀的光罩層之二 14 200531217 側0 外.如r睛專利範圍第丨至3項任一項、 在於該等源極與汲極區域係藉由植入而：二方法’其特徵 5·如申請專㈣圍第丨i 3熟—項 f於二個雙間極電晶體係形成於該半導體基體中且；：徵 鄰接’其係藉由形成三個溝槽於該半導體基體中，:二此 溝槽之中間的溝槽係形成對於該二個雙：二： 用的閘極區域。 弘日日體之一共 ’其特徵在於該二個 npn電晶體，而另_ 6·如申請專利範圍第5項之方法 雙閘極電晶體之一者係形成作為一個 者係形成作為一個pnp電晶體。 在二申請專利範圍第…項任-項之方法，其特徵 在方η亥又閘極電晶體之源極與沒極區域係藉由另外的溝槽 而與相對於該通道區域的一側之半導體基體分離。 8. 如申請專利範圍第丨纟3項任—項之方法，其特徵 h在於s亥雙閘極電晶體係與其他由習用的cm〇s技術所作成 之習用的電晶體一起形成。 9. 如申請專利範圍帛2項之方法，其特徵在於一金屬 層係被選擇以用於該導電層。 10·—種包含一雙閘極電晶體之半導體元件，其係具有 一個具有一表面之矽的半導體基體、一第一導電類型之一 源極區域與一汲極區域、介於該源極區域與汲極區域之間 且相反於第一導電類型的一第二導電類型之一通道區域、 藉由一第一閘極介電質與該通道區域分離且位於該通道區 200531217 域的一側之一第一閘極區域、及藉由一第二閘極介電質與 該通道區域分離且位於該通道區域的一相對側之一第二閘 極區域，其中，二個閘極區域係形成於該半導體基體中所 形成之-溝槽内’其特徵在於：言亥第一閘極區域係形成於 第一溝槽内，而该第二閘極區域係形成於一第二溝槽 内’該通道區域係由該第一與第二溝槽之間的半導體基體 之部分所形成，且該源極盥访托π a〆 興及極區域係形成於該半導體基
    體之表面。 10項之半導體元件，其特徵在 閘極區域之二個相鄰的雙閘極電 1 1 ·如申請專利範圍第 於其包含具有共用的一個 晶體。 十一、圖式： 如次頁
    16
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