TW200531179A - Junction barrier schottky with low forward drop and improved reverse block voltage - Google Patents

Abstract

This invention discloses a junction barrier Schottky device supported on a substrate that has a first conductivity type. The Schottky device includes a first diffusion region of a fist conductivity type for functioning as a forward barrier height reduction region. The Schottky device further includes a second diffusion region of a second conductivity type disposed immediately adjacent to the first diffusion region for functioning as a backward blocking enhancement region to reduce the backward leakage current.

Description

200531179 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention mainly relates to the structure and manufacturing process of a junction barrier Schottky device. The invention particularly relates to a novel structure and manufacturing process of a Schottky device with a low forward voltage drop and a high reverse blocking voltage junction barrier. [Prior art] Although the junction barrier Schottky device has the advantages of low forward voltage drop and fast reverse recovery time, its application is limited due to technical reasons. First, its reverse leakage current increases as the junction barrier height decreases. Although the reduction in junction barrier height reduces forward conduction losses, it also has the side effect of increasing reverse leakage current. Compared with ordinary pn junction diodes, Schottky devices have limited their practical applications because of their poor reverse characteristics. Another factor that limits the application of the junction barrier Schottky device is that when it is used as a large, power input device rectifier, it needs to provide a large silicon area because it needs to provide a large current. In order to improve the reverse characteristics of Schottky devices, Buchanan Jr. et al. Proposed a method using P + -type ion diffusion in a statutory invention registration patent (SIR) H40 entitled "Field Shields for Schottky Barrier Dev ices". One or more field protection zones to reduce reverse leakage current. As shown in Figure 1A, a P + electric field protection zone is formed under the Schottky positive electrode. The electric field protection zones are arranged in a certain way to reduce The surface electric field is reduced, so the reverse leakage current is reduced. However, forming a P + type electric field protection zone according to the method given by Buchanan Jr. using P + type ion implantation and then diffusion will cause another problem, the lateral diffusion of P + type ions Occupies a large portion of the silicon area

200531179 V. Description of Invention (2). Unless a large area of silicon is allowed between the P + -type ion implantation regions, the height of the forward junction barrier is increased. For this reason, Buchanari Jr.'s proposed method will be impractical for electronic devices that need to provide sufficient input current while requiring minimal power consumption. The size of the Schottky device manufactured by Buchanan Jr. using the P + ion diffusion method will greatly exceed the requirements of micro devices. In addition, unless a large-area Schottky device is used, the forward junction barrier will be greatly affected due to the lateral diffusion of p + ions. If the control is not good, the forward conduction current will be greatly reduced. "Xin Xinxuan encountered a similar problem when forming P + -type ion diffusion on the upper surface of the Schottky barrier device to increase the reverse blocking voltage to form an electric field protection zone to increase the forward junction barrier height. Figure 1B Fig. 1C and Fig. 1C are cross-sectional and top views of the junction barrier Schottky diode disclosed in U.S. Patent 6, 5 24, 900, respectively. Fig. 1B illustrates a control of the junction barrier Schottky diode. A method of temperature dependence. It firstly produces a large number of p-type doped gate regions 4 and then adjusts the doping of the drift layer 7 ✓ The degree of drift makes the drift region 7 a part of the gate region. Polar body drift region 2 can be grown by epitaxial method, which can provide donor carriers as high as 10 / cm ^ until the gate is close to the open state when it reaches a certain thickness. In order to ensure a sufficiently large constant current density, it can be controlled by The doping concentration of the gate region adjusts the intersection of the temperature coefficient from a negative number to a positive number. This is further explained in US Patent No. 6,524,900, which uses a greater lateral distance when forming a P + type doped region, Gate drift 7 the transverse cross-worn area increases in the proportion of the total lateral area, whereby the impedance of diode gate region becomes smaller. However, as described above, 6, 524, 9〇 ()

Will Page 8 V. Description of the invention (3) = Although the method proposed by Li Zhong improved the temperature stability, the lateral size of the P + doped region was made, which increased the size of Xiao Temei's "Adding Size". This greatly limits its application to the entire micro-devices that require long electricity, soil, and °. In the modern era that requires the power supply volume to be reduced, it is necessary to propose a new type of f-tertiary structure and f-work. In particular, a Schottky Seman device should have a ":" device and a reverse blocking voltage, and it will not increase Xiao = content of the invention] 艺 '㊁ί: = ϊ 于 ϊ contribute-a new type of Device structure and fabrication of I small forward potential s adjacent to the diffusion region to form a PN junction array to reduce the difficulty of "C reverse blocking voltage" so that all of the above two fabrications of the other 3: The purpose is to provide-a new The device structure ions and ions on the N + type base… type drift region are first implanted to reduce the P-type and simultaneously reverse the 'resistance and breaking lightning' line and diffuse simultaneously. Positive potentials are highly divalent. Further, through the father and son) to reduce the lateral second-order diffusion of p-type and n-type devices that deviate from the performance of the device, while reducing the size, the device can also be disclosed. A piece. The special Ln: type: junction barrier Schottky device 祜 the first semiconductor layer of the first conductivity type 200531179 V. Description of the invention (4)

It is the same as the second semiconductor layer grown on the above-mentioned semiconductor layer, but with a lower doping concentration than the first semiconductor layer. The device further includes a first diffusion region of a first conductivity type, which has a higher doping concentration than the first semiconductor layer, forming a forward barrier height reduction region. The Schottky device further includes a second diffusion region of a second conductivity type adjacent to the first diffusion region to form a reverse blocking enhancement region. The first diffusion region and the second diffusion region are both in the second semiconductor layer. on. In another embodiment, the Schottky device further includes a plurality of first diffusion regions and a second diffusion region that alternately grow next to each other. In another preferred embodiment, the Schottky device further includes a plurality of alternately grown first diffusion regions and second diffusion regions having a prescribed width and interval adjacent to each other. The invention also discloses a manufacturing process for making a junction barrier Schottky device on a substrate having a first semiconductor layer and a second semiconductor layer in advance. The second semiconductor layer is grown on the first semiconductor. The doping concentration is lower than that of the first semiconductor layer. This method includes doping a higher concentration of impurities of the first conductivity type into the second semiconductor layer, and performing diffusion to form a first diffusion region as a forward barrier height reduction region. The method further includes doping a second conductivity type impurity into the second semiconductor layer and diffusing to form a second diffusion region as a reverse blocking enhancement region.

With regard to these and those objects and advantages of the present invention, those skilled in the art can surely understand them as long as the detailed details of the preferred embodiment are summarized in conjunction with the drawings. [Embodiment] "First, please refer to the first Schottky junction barrier device disclosed in the present invention

Page 10 200531179 V. Description of the invention (5) A schematic sectional view of the embodiment. The Schottky junction device 100 is fabricated on a semiconductor substrate 105 of the first conductivity type (generally N-type), and a first semiconductor layer is grown on the substrate 105 in advance. It is shown in the figure as The N + type 'and the second semiconductor layer 105-2 are shown as n-type in the figure, in which the doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer. The Schottky junction barrier device further includes a metal layer 180 and a silicide layer 170 to form a Schottky junction, and the silicide layer serves as a cathode of the diode. The junction barrier Schottky device further includes a plurality of alternately grown P + -type and N + -type diffusion regions 145 and 15 having a prescribed width and interval adjacent to each other. The N + -type diffusion region 150 is used as a forward barrier reduction region, and the p + -type region 1 45 is used as a reverse blocking enhancement region to increase the reverse blocking voltage or reduce the reverse leakage current. The thick oxide layer 110 shown in the figure serves as an electric field insulation layer to increase the avalanche breakdown voltage of the lead region. 3A to 3K are schematic cross-sectional views showing the manufacturing process of the Schottky junction barrier device shown in FIG. 2. First, the substrate 105 having N + type semiconductor layers 105-1 and 105-2 in advance is subjected to 9000c to U5 (rc high temperature oxidation treatment. A thickness of 100 to 100 is formed on the upper surface of the substrate 105. 〇⑽'s oxide layer 10. Considering the interface charge of Si / Si 0, the thermal oxidation method should be preferred. For the oxide layer electrode, the oxide layer u 〇 is necessary to withstand a certain operating voltage. It can also be used as a masking layer for ion implantation, which will be described in detail below. Then, a photoresist 11 5 is coated on the oxide layer π to form a mask, and the unprotected oxide layer is etched to form a human figure 3B The structure shown. Then dry or wet oxygen treatment at 850 ° C is performed to grow a thin oxide film 120, as shown in Figure 3C, its thickness is approximately one

200531179 V. Description of the invention (6) 50nm ’to avoid damage to the silicon wafer caused by the subsequent ion implantation process. As shown in FIG. 3D ', p + -type ions 1 25 are implanted on the substrate with an implantation energy of 30-100 Kev and a dose of 5X1012 / cm2 to 5X1014 / cm2 to form a p + layer 130. Referring to FIG. 3E, the N + photoresist 135 lithographic mask protection is performed first, followed by ion filling (31) implantation 140, implantation energy 80Kev, and implantation amount 8 · 0X10 12 / cm 2 ~ 8 · 0X1014 / cm2. A plurality of P + regions 145 and N + regions 150 are formed on the P + layer 130, and then the photoresist 135 is removed, as shown in FIG. 3f. . Referring to FIG. 3G, the p + region 145 and the N + region 150 are simultaneously subjected to high-temperature diffusion at 1050 to 115 ° C for 30 minutes to 10 hours, and the diffusion depth is 0.5 // m to 10 // m. The P + and N + diffusion processes are performed in an atmosphere of n2, 0, and JJC1 to reduce the surface tension and surface defects generated during the heating process. An oxide layer with a thickness of 200 nm was grown, and then etched to remove the oxide layer. As described in the third example, the barrier metal layer 160 having a total thickness of more than 0 2 // m is grown on the surface of the substrate, and the material may be Titanium (Ti), Ti / TiN, f1Chr⑽e (Nl) 'Plantium (Pt ), Molybrium (Mo) or NiPt, as shown in Figure 31, 'anneal the barrier layer in a nitrogen atmosphere at a temperature of 400 to 300 minutes, or at a temperature of 400 to 800. Then, a rapid thermal annealing process is performed, and the time is 10 to 60 seconds. A silicide layer 17O will be formed under the barrier layer 16O. The remaining unactivated portion of the barrier layer 160 is etched away with Aqua Rega. Then a metal layer with a thickness of more than 1000n_ is grown thereon, and the material may be Aluminum (A1), and A 1 / S i / Cu Al / Si 'Al / Cu may also be Ti / Ni / Ag. As shown in FIG. 3J, a photoresist 175 is coated on the metal layer 180, and then the mask is engraved with #metal, and then the upper photoresist layer 175 is removed, as shown in FIG. 3K.

Page 12 200531179 V. Description of the Invention (7) Figures 4A to 4C are unveiled & ^. τ mushroom 4 β ^^ This is another preferred embodiment of the present invention ^. 9Λ,,. 9Λ 'does not have a ν + type semiconductor layer 205-1 on the substrate 20 0, and 205-1 Bugu η: There is an N-type drift layer 205-2 on XT and E, and a layer of low-doped N-type semiconductor drawer 9. 0 Λ r. 9 in > Pi #, layer 2 05 -3, and 2 5 5 are grown on it. — 3 with a natural oxide layer 210. Enter the HP mask (in the picture; soil 4 West,…, μμ 工 t X position * any picture is not shown) etch the oxide layer, and then ^ oonJi λΤ ^ 00Λ into the expansion, in the drift zone 205-2 forms P & 2 20 and N-region 2 3 0. As shown in the Figure __ Handyman, 7 4B, N mask 2 3 5 is performed, and then ions (phosphorus ions or arsenic ions) are implanted to form cells 240 around the P region 220. Unmask it as shown in Figure 4C

membrane. Perform a contact mask (not shown in the figure), mark the oxide layer (because it is similar to Figures 3H to 3K, so it is not shown in the figure), and then form a silicide layer 2 60. After performing a metal mask (not shown in the figure), a metal layer is grown on top, and then the metal layer is etched to complete the entire process flow. 5A to 5C illustrate a process flow of another embodiment of the present invention. As shown in FIG. 5A, there is an n + semiconductor layer 305-1 on the substrate 300, an N-type drift layer 305-2 on the 305-1, and a low-doped N-type semiconductor layer 305- is grown thereon. 3, with an initial oxide layer 310 on 305-3.

A P mask (not shown in the figure) is used to etch the oxide layer, and then ion implantation is performed, followed by diffusion, to form a middle N-region 3 p 3 around the p region 320 above the drift region 30-5-2. . As shown in FIG. 5B, an N mask 3 3 5 is performed, and then an N-type ion (a dish ion or a god ion) is implanted, followed by diffusion 'to form an N region 3 4 0 around the P region 3 2 0. The N-mask 3 3 5 does not cover the oxide layer 3 1 0. After N-type ion implantation, the p-region 3 2 0 under the oxide layer 3 2 0 becomes a contracted P- region. As shown in FIG. 5C, the ν-mask 3 3 5 is removed. get on

Page 13 200531179 V. Description of the invention (8) Contact mask (not shown in the figure), etching the oxide layer (because it is similar to Figures 3H to 3K, so it is not shown in the figure), then A silicide layer is formed. After performing a metal mask (not shown in the figure), a metal layer is grown thereon, and then the metal layer 3 50 is etched to complete the entire process flow. Figures 6, 7 and 8 show the junction barrier Schottky device structure and process flow similar to the devices described in Figures 2, 4C, and 5C. Compared with the devices disclosed in FIG. 2, FIG. 4C and FIG. 5C, the only difference is that the devices disclosed in FIG. 6, 7 and 8 do not have the N- Layer and the N-type buffer layer disclosed in Figure 4C and Figure 5C. These buffer layers are sandwiched between the N + substrate and the successively grown adjacent PN or PN-PN layers, and these PN or PN-PN layers can be Diffusion penetrates the N- epitaxial layer and contacts the N + substrate. Referring to FIG. 9A, FIG. 9A is a schematic cross-sectional view showing another embodiment of a Schottky junction barrier device according to the present invention. The Schottky junction barrier device 800 is fabricated on a semiconductor substrate 805 of the first doping type (such as the N-type doping shown in FIG. 9B). In FIGS. 9A and 9B, the bottom layer is the first semiconductor layer 805-1, which is shown as an N + region in the figure, the second semiconductor layer 8 0 5-2 is shown as an N- region, and the third semiconductor The layer is represented as an N-layer, and its doping concentration is lower than that of the first semiconductor layers 805-1 and 805-2, as shown in FIG. 9B. The Schottky junction barrier device further includes a metal layer 880 and a silicide layer 870, wherein the silicide layer forms a Schottky contact to form a positive electrode of the diode. The Schottky junction barrier device further includes a plurality of P + -type and N + -type diffusion regions 845 and 850 adjacent to each other at a prescribed interval and width. N + -type diffusion region 85 0 constitutes a reduced barrier region, while P + -type diffusion region

Page 14 200531179 V. Description of the invention (9) 8 4 5 constitutes a reverse blocking enhancement zone to increase the reverse blocking voltage and reduce the reverse leakage current. The 810-thick oxide layer shown in the figure constitutes the dielectric layer of the electric field oxide layer plate, which improves the avalanche breakdown voltage of the lead region. The Schottky junction barrier device 800 has its unique advantages (the advantages of this embodiment are added here). Please refer to Figs. 10A to 10J, which show the process flow diagram of the Schottky junction barrier device shown in Fig. 9A. First, the substrate 8 0 5 is subjected to a high temperature oxidation treatment at 90 0 to 1 150 ° C to form an oxide layer on the substrate. Among them, an N + bottom layer 8 0 5-1, N is grown on the substrate 8 0 5 in advance. -Type intermediate layer 8 0 5-2 and N-type upper layer 805-3. The thickness of the oxide layer 810 grown on the substrate 80 5 is about 100 to 100 nm. Considering the charge of the Si / SiO interface, the method of thermal oxidation should be given priority. For the electrode of the oxide layer, the oxide layer 8 i 〇 is necessary to withstand the working voltage. The oxide layer can also be used as an ion implantation mask in the etching step, which will be described further below. As shown in FIG. 10B, the oxide layer 8 10 is subjected to mask lithography 8 1 5, followed by etching, and then the photoresist is removed. As shown in Figure 10C, high-temperature oxidation is performed in a dry or humid environment at a temperature of 850 ° C to form a pad oxide layer 8 2 0, which has a thickness of about 20 to 50 nm. The damage caused by the subsequent ion implantation process to Shi Xi is reduced. As shown in FIG. 10D, p + -type ions 82 5 (B ions) are implanted into the substrate with an implantation energy of 30 to 10 OKev and a dose of 5X1012 / cm2 to 5X10 μ / cm2 to form a P + -type layer 830. Referring to FIG. 10E, N + mask lithography 8 35 is performed, and then N + type ions (P-31) are implanted, and the implantation energy is 80 KeV ′ dose 8X1 0 12 / cm2 to 8X1 0 14 / cm2. A plurality of P + regions 845 and N + regions 850 are formed on the P + type region 830, and the photoresist 835 is removed.

Page 15 200531179 V. Description of the invention (10) 10 F Referring to FIG. 10G, it is in the range of 5 to 5i. P + region 845 and N + region 850 are simultaneously diffused at a temperature of 〇, the diffusion time is about 30 minutes, and the diffusion depth is 0, · 5 to 10 // m. The diffusion process is performed in the environment of μ, 〇2, and HC1 to reduce the surface tension and surface defects generated during the heating process. An oxide layer is formed on the surface to a thickness of about 20 to 100 Å, and the oxide layer is etched. As shown in the ι〇Η diagram, a barrier metal layer 860 with a total thickness exceeding 0.2 m is grown on the surface of the wafer, wherein the metal material may be titanium (Ti), Ti / TiN, nickel (Nι) 'surface (Pt ), Molybdenum (Mo), or Nipt alloy, and so on. As shown in Fig. 101, the potential stack is annealed in a nitrogen atmosphere at a temperature of 400 to 700 ° C for a time of 30 to 60 minutes, or at 400 to 60 minutes. A rapid thermal annealing treatment was performed at 80 to 60 seconds for 10 to 60 seconds. Below the barrier layer 86, a stone oxide layer 87 is formed. The unactivated part of the barrier layer uses Aqua Rega. A thick metal layer 880, such as aluminum (Al), Al / Si / Cu, Al / Si, Al / Cu, or Ti / Ni / Ag, is then grown thereon. As shown in FIG. ΙΟ, a photoresist protective layer 8 75 is coated on the thick metal layer 88, and then the metal is etched, and then the photoresist is removed, as shown in FIG. ·· In an actual embodiment, the dopant concentration of the upper epitaxial layer 8 0 5-3 is the lowest, which is generally a P-type doping, and the doping concentration of the bottom 8 5-2 layer is more than- P-type doping. The substrate 805-1 is produced using a conventional standard process. The resistivity is less than 5 μm · cm, and arsenic is added. The thickness and power of the upper epitaxial layer 805-3 can be adjusted according to the depth of the P + ion diffusion, and the p + ion concentration depth depends on the ion implantation energy, diffusion temperature, and diffusion time. = Expansion, the rated voltage of the Schottky device increases, and the thickness of the upper epitaxial layer is 805 to 3%

Page 16 200531179 V. Description of the invention (11) also needs to be improved accordingly. The lower the N doping of the upper epitaxial layer 8 0 5-3, the deeper the P + junction of the Schottky device. The low N-type doping of the upper N-type layer 80 5-3 will help increase the N-type diffusion depth. P-type ion implantation is similar to this. The thickness and doping concentration of the upper N--type layer 8 0 5-3 can be adjusted according to the energy, dose, diffusion temperature and diffusion time of the ion implantation, so as to control the P + channel and N + trench. Channel parameters to optimize the device's forward and reverse current characteristics. Further, the thickness and / or doping concentration of the lower epitaxial layer 8 0 5 -2 can be adjusted during the device manufacturing process, thereby controlling the diffusion depth of the P + type region, adjusting the external diffusion of the substrate, and optimizing the parameters of the P + channel. To obtain the best device current characteristics. Therefore, the embodiments described above have three combined thicknesses and doping characteristics, which can be adjusted according to lithographic characteristics, diffusion processes, barrier height of the silicide layer, and ohmic metal contact to obtain the required blocking voltage. Reverse current and forward voltage characteristics. The process design and process flow provided by the present invention have good process compatibility. The parameters of the device such as Vbr, Vf, and the device can be optimized by optimizing the thickness and doping concentration of the three epitaxial layers 805-1 to 805.3. The reverse recovery characteristics are optimal. As described above, the present invention discloses a junction barrier rectifier device fabricated on a semiconductor substrate. What does this device include? Many first and second diffusion regions having different conductivity types are formed by ion implantation of the first conductivity type and the second conductivity type and performing diffusion. In a preferred embodiment, the substrate further includes a first semiconductor layer of a first conductivity type grown under the first and second diffusion regions. In one of the most important aspects of the present invention

Page 17 200531179 V. Description of the invention (12) In the embodiment, the substrate further includes a second semiconductor layer of the first conductivity type located below the first diffusion region and the second diffusion region and above the first semiconductor layer. Wherein its doping concentration is lower than that of the first semiconductor layer. In a preferred embodiment of the present invention, the ions of the first conductivity type and the ions of the second conductivity type have different vertical diffusion coefficients and lateral diffusion coefficients. In a preferred embodiment of the present invention, the ions of the first conductivity type are N-type ions, and the ions of the second conductivity type are P-type ions, which have different vertical diffusion coefficients and lateral diffusion coefficients. In one embodiment of the present invention, the lateral diffusion coefficient of the N-type ion is larger than the vertical diffusion coefficient, and the vertical diffusion coefficient of the P-type ion is larger than the lateral diffusion coefficient. In a preferred embodiment of the present invention, the first diffusion region and the second diffusion region are adjacent to each other and have a prescribed width. In a preferred embodiment of the present invention, the junction barrier rectifying device further includes an anode and a cathode for applying a voltage. In a preferred embodiment of the present invention, one of the electrodes further includes a conductive layer in contact with the first diffusion region and the second diffusion region. In a preferred embodiment of the present invention, the conductive layer further includes a silicide layer covering the surface of the substrate and in contact with the first diffusion region and the second diffusion region. In a preferred embodiment of the present invention, the conductive layer further includes an ohmic metal contact layer covering the surface of the substrate and contacting the first diffusion region and the second diffusion region. The invention further discloses a method for fabricating a junction barrier Schottky device on a substrate. A first semiconductor layer and a second semiconductor layer of a first conductivity type are grown on a substrate in advance, wherein the second semiconductor layer is located on the first semiconductor layer and its doping concentration is lower than that of the first semiconductor layer. . The process flow includes doping a first conductivity type into a second semiconductor layer

Page 18 200531179 V. Description of the invention (13) The ions are diffused to form a first diffusion region, which serves as a forward barrier height reduction region, wherein its doping concentration is higher than that of the second semiconductor layer. The process flow further includes doping a second conductivity type ion into the second semiconductor layer and performing diffusion to form a second diffusion region, which is used as a reverse blocking enhancement region. In a preferred embodiment of the present invention, the process steps of implanting ions into the second semiconductor layer and performing diffusion to form the first diffusion region and the second diffusion region further include diffusing the first diffusion region and the second diffusion into the second semiconductor layer. The ions of the first conductivity type and the second conductivity type are implanted in the region, and synchronous diffusion is performed. In essence, the present invention discloses a process flow for making a junction barrier rectifier device on a semiconductor substrate. The process includes implanting ions of a first conductivity type and a second conductivity type into a substrate and performing diffusion formation? Multiple first diffusion regions and second diffusion regions. In a preferred embodiment of the present invention, the process of implanting ions of the first conductivity type and the second conductivity type into the substrate and diffusing them further includes implanting a plurality of ions into the second semiconductor layer and diffusing the ions. A first semiconductor layer and a second semiconductor layer on the first semiconductor layer are grown in advance. They both belong to the first conductivity type, except that the doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer. In a preferred embodiment of the present invention, the process of implanting ions of the first conductivity type and the second conductivity type and performing the diffusion further includes implanting the first conductivity type and the second conductivity having different vertical diffusion coefficients and lateral diffusion coefficients. Type of ions and perform simultaneous diffusion. In a preferred embodiment of the present invention, the process steps of implanting and diffusing the ions of the first conductivity type and the second conductivity type further include implanting the ions of the second conductivity type and performing

Page 19, 200531179 V. Description of the invention Synchronous diffusion, on-chip fabrication of the present invention uses a PN junction entry mask and an ion implantation mask arranged in an active region to apply the process steps using a film of the present invention with a pattern > main One step in the embodiment of the ion implanted conductor substrate into the mask and junction includes singulating the junction in a single embodiment in which the hair and diffusion mask are uniform. The junction is fabricated on the wafer of the present invention and the active region is used to form the lead region. Ion beam on the potential Schottky barrier. The best implementation of the oxide film and the diffusion mask implant mask of the present invention further include a diffusion mask. One of the most important process steps for forming an epitaxial substrate of a PN junction with a mask and expanding a single epitaxial layer is to reveal an epitaxial layer on the epitaxial layer. Process. In this embodiment of the fabrication of a mask, the steps include using one of the most advanced process steps into the mask and ion implantation to mask the nitride. A best practice step is one step earlier in the diffusion mask of the present invention. In the epitaxy, the separation of the PN junction from the fundamental linear invention of the semiconductor has a long active flow. The protective ring made by this process mask is an optimal step in the process of masking and expanding in the pre-device process. In the present invention and the diffusion mask as examples of ion implantation, the application includes the use of a pattern to form a PN junction on the diffusion mask of the present invention. The implantation mask and the doping uniformity of the preferred embodiment further include forming a PN junction. The doping concentration presents a process for pre-device masking and diffusion. The basic flow of the zone structure includes numerous alternate applications of ion implantation photoresist as a preferred embodiment and further includes a diffuse mask. In the case where the film and the diffusion mask are used as ions, the PN step includes a basic process of forming a PN sub-injection mask on a half of an optimal process step into the layer, and do not have an optimal real or gradient region structure. Including numerous alternations

Page 20 200531179 V. Description of the invention (15) | PN-PN junctions arranged. In the practical application of the ion implantation mask and diffusion mask of the present invention, the application of ion implantation and ion implantation of the present invention-a best practice-including the use of a patterned oxide layer as the process steps of j- One of the best steps in the present invention is the implantation mask and the diffusion mask. The process steps of the mask are as follows: you can use the ion implantation mask and the ion implantation mask of the diffused PN junction to mask 2 and 垆: 2 in a preferred embodiment of the single semiconductor substrate: =; Step-by-step includes the process I-step including the step I junction of the implantation mask and the diffusion mask. In another preferred embodiment of forming PN-PN and Qu Ming q on a single epitaxial layer of the other 2J substrate of the present invention, the impurity concentration of the single epitaxial sound changes linearly or gradiently. For the doping of the outer L layer, the present invention is best practiced as it is all of the present invention. K should not be described in detail after 5 I, II: or connotation. After completing the above various replacements and modifications of the present invention, it is enough to perform various modifications to those technologies of the present invention. The present invention "envy :: disk can interpret all claims in the original spirit and field of the claims at the bottom of this application. Changes and amendments. Page 21 200531179 Brief description of the drawings [Simplified description of the drawings] Fig. 1A is a schematic cross-sectional view of a conventional Schottky barrier device including an electric field protection region. Figs. 1B and 1C are Sectional view and top view of another conventional junction barrier Schottky device. Fig. 2 is a cross-sectional view of an N + diffusion Schottky device according to the present invention. Figs. 3A to 3K are views of the device shown in Fig. 2. Sectional schematic diagrams of the manufacturing process. Figures 4A to 4C are schematic cross-sectional diagrams of the manufacturing process of an alternative preferred embodiment of the present invention. Figures 5A to 5C are alternative best practices of the present invention. A schematic cross-sectional view of the manufacturing process of the example. Figures 6 to 8 are shots similar to Figure 2, Figure 4C, and Figure 5C fabricated on a semiconductor substrate having a single N-type epitaxial layer according to the present invention. Base device Alternative best embodiment. Figure 9A is a schematic cross-sectional view of another embodiment of the present invention in which two epitaxial layers are introduced as an upper epitaxial layer to improve the performance of a high voltage rectifier. The doping concentration of the epitaxial layer is further improved. Lower. Figure 9B shows the doping profile of the epitaxial layer shown in Figure 9A. Figures 10A to 10J are schematic cross-sectional views of the process flow of the embodiment shown in Figure 9A. [Description of main component symbols ] Oxide layer 110 Photoresist 115

Page 22 200531179 Round type brief description P + layer 130 photoresist 135 barrier metal layer 160 petrified layer 170 photoresist 175 oxide layer 810 mask lithography 815 mask lithography 835 barrier metal layer 860 lliiill 23 page

Claims (1)

200531179 VI. Application Patent Scope 1. A junction barrier Schottky device, which is characterized by comprising: a first semiconductor layer of a first conductivity type and a second semiconductor layer of a first conductivity type, wherein the second semiconductor layer is located at Above the first semiconductor layer, its doping concentration is lower than that of the first semiconductor layer; a first diffusion region, which belongs to the first conductivity type, has a higher doping concentration than the second semiconductor layer, and is used as a forward potential A barrier height reduction region; and a second diffusion region of a second conductivity type, which is adjacent to the first diffusion region and grows on the second semiconductor layer to form a reverse blocking enhancement region. 2. The junction barrier Schottky device according to item 1 of the scope of patent application, further comprising: a plurality of the first diffusion region and the second diffusion region adjacent to each other. 3. The junction barrier Schottky device according to item 1 of the scope of patent application, further comprising: a majority of the first diffusion region and the second diffusion region adjacent to each other, with a predetermined width between them ( Or interval). 4. The junction barrier Schottky device according to item 1 of the scope of patent application, further comprising: implanting the first conductive type and the second conductive type ions into the second semiconductor layer, and performing synchronous diffusion The majority of the first diffusion region and the second diffusion region are formed. 5 · The junction barrier Schottky device described in item 1 of the scope of patent application, which Page 24 200531179 6. The scope of the patent application is characterized by further comprising: implanting the first conductive type and the second conductive type ions into the second semiconductor layer, and performing the majority of the first diffusion region and the second diffusion layer formed by synchronous diffusion. A diffusion region, in which the ions have different vertical diffusion coefficients and lateral diffusion coefficients. 6. The junction barrier Schottky device according to item 1 of the scope of patent application, further comprising: implanting said first conductivity type N-type and second conductivity type P-type ions into said second semiconductor layer, Most of the first diffusion region and the second diffusion region formed by the simultaneous diffusion, wherein the N-type ion and the P-type ion have different vertical diffusion coefficients and lateral diffusion coefficients. 7. The junction barrier Schottky device according to item 1 of the patent application, further comprising: implanting the first conductivity type N type and the second conductivity type P type ions into the second semiconductor layer. The majority of the first diffusion region and the second diffusion region formed by simultaneous diffusion, wherein the lateral diffusion coefficient of the N-type ion is larger than the vertical diffusion coefficient, and the lateral diffusion coefficient of the P-type ion is smaller than the vertical diffusion coefficient. 8. The junction barrier Schottky device according to item 1 of the scope of patent application, further comprising: implanting the first conductive type and the second conductive type ions into the second semiconductor layer, and performing synchronous diffusion The formed majority of the above-mentioned first diffusion regions and second diffusion regions, wherein the above-mentioned first diffusion regions and Page 25 200531179 VI. Scope of patent application The second diffusion areas are adjacent to each other with a predetermined interval. 9. The junction barrier Schottky device according to item 1 of the scope of patent application, further comprising: a cathode and an anode for applying a voltage. 1 0 · The junction barrier Schottky device according to item 9 of the scope of patent application, characterized in that: one of the electrodes further includes covering the upper surface of the substrate and contacting the first diffusion region and the second diffusion region. Conductive layer. 1 1 · The junction barrier Schottky device according to item 10 of the scope of patent application, characterized in that: the conductive layer further includes covering the upper surface of the substrate and contacting the first diffusion region and the second diffusion region. Layer of silicide. 1 2 · The junction barrier Schottky device according to item 10 of the scope of patent application, wherein the conductive layer further includes a phase covering the upper surface of the substrate and the first diffusion region and the second diffusion region. Contacted metal layer. 1 3 · The junction barrier Schottky device according to item 2 of the scope of patent application, characterized in that at least one diffusion region in the second diffusion region is located in the termination region and is used as a guard ring for receiving breakdown voltage. 1 4 · The junction barrier Schottky device according to item 2 of the scope of patent application, characterized in that: in correspondence with the upper surface, another electrode is formed on the lower surface of the substrate to be in contact with the first semiconductor layer. . Page 26 200531179 VI. Patent application scope 1 5 · The junction barrier Schottky device described in item 1 of the patent application scope, further comprising: growing on the second semiconductor layer and belonging to the first conductivity Type semiconductor lead region, in which its doping concentration is lower than that of the second semiconductor layer, and the position of the semiconductor lead region is adjacent to the pin region of the junction barrier Schottky device. 1 6 · A junction barrier rectifier device fabricated on a substrate, comprising: implanting ions of a first conductivity type and a second conductivity type ′ into the substrate and forming a plurality of first conductive materials of different conductivity types. A diffusion region and a second diffusion region. 1 7 · The junction barrier rectifier device according to item 16 of the scope of patent application, wherein the substrate further includes a first conductive type of a first conductive type located below the first diffusion region and the second diffusion region. A semiconductor layer. 1 8 · The junction barrier rectifier device according to item 17 in the scope of the patent application, wherein the substrate further includes a first conductive type of a first conductive type located below the first diffusion region and the second diffusion region. Two semiconductor layers, wherein the second semiconductor layer is located on the first semiconductor layer, and its doping concentration is lower than the doping concentration of the first semiconductor layer. The junction barrier rectifier device is characterized in that the ions of the first conductivity type and the second conductivity type have different Page 27 200531179 6. Scope of patent application Lateral diffusion coefficient and vertical diffusion coefficient. 2 0. The junction barrier rectifier device according to item 16 of the scope of patent application, characterized in that the ions of the first conductivity type are N-type ions, the ions of the second conductivity type and P-type ions, wherein the N-type Ions and P-type ions have different lateral and vertical diffusion coefficients. 2 1 · The junction barrier rectifier device according to item 20 of the scope of patent application, wherein the lateral diffusion coefficient of the N-type ions is larger than the vertical diffusion coefficient, and the lateral diffusion coefficient of the P-type ions is larger than the vertical diffusion. The coefficient is small. 2 2 · The junction barrier rectifier device according to item 20 of the scope of patent application, wherein the first diffusion region and the second diffusion region are adjacent to each other with a predetermined interval. 2 3 · The junction barrier rectifier device according to item 16 of the patent application scope, further comprising: a cathode and an anode for applying a voltage. 24. The junction barrier rectifier device according to item 23 of the scope of patent application, wherein one of the electrodes further includes a conductive layer covering the upper surface of the substrate and contacting the first diffusion region and the second diffusion region. 2 5 · The junction barrier rectifier device according to item 24 of the scope of patent application, wherein the conductive layer further includes a cover on the upper surface of the substrate and the above Page 28 200531179 6. Scope of patent application The silicide layer where the first diffusion region and the second diffusion region are in contact. 2 6 · The junction barrier rectifier device according to item 24 of the scope of patent application, wherein the conductive layer further includes a metal covering the upper surface of the substrate and contacting the first diffusion region and the second diffusion region. Floor. 27. A process flow for fabricating a junction barrier Schottky device on a substrate in which a first semiconductor layer of a first conductivity type and a second semiconductor layer are grown in advance, wherein the second semiconductor layer is located between the first semiconductor layers On the other hand, its doping concentration is lower than that of the first semiconductor layer, and is further characterized by: implanting ions of a first conductivity type with a higher doping concentration than the first semiconductor layer into the second semiconductor layer; A first diffusion region having a barrier height; and a second diffusion region for increasing a reverse blocking voltage by implanting a second conductive type ion into the second semiconductor layer and performing diffusion. 2 8 · The process flow as described in item 27 of the scope of patent application, characterized in that the process steps of implanting ions into the second semiconductor layer and performing diffusion to form the first diffusion region and the second diffusion region further include the step of The semiconductor layer simultaneously implants the ions of the first conductivity type and the second conductivity type, and diffuses to form a plurality of the first diffusion regions and the second diffusion regions. 29. The process steps of making a junction barrier rectifier device on a semiconductor substrate, which are characterized by: Page 29 200531179 VI. Scope of patent application The above semiconductor substrate is implanted with most of the first conductivity type and the second conductivity type ions, and is diffused to form the majority of the first diffusion region and the second diffusion region. 30. The process step as described in item 29 of the scope of the patent application, characterized in that the process step of implanting a majority of the first conductivity type and the second conductivity type ions into the semiconductor substrate further includes growing a first The substrates of the conductive type first semiconductor layer and the second semiconductor layer are implanted with ions and diffused. The second semiconductor layer is located above the first semiconductor layer, and its doping concentration is lower than that of the first semiconductor layer. 3 1 · The process step described in item 29 of the scope of patent application, characterized in that the process steps of implanting and diffusing the first and second types of ions further include implanting a material having different lateral diffusion coefficients and vertical diffusion coefficients. The first conductive type ions and the second conductive type ions are simultaneously diffused. 3 2 · The process step described in item 29 of the scope of patent application, characterized in that the process steps of implanting and diffusing the first and second types of ions further include implanting and synchronizing the ions of the second conductivity type Diffusion forms a guard ring in the termination region to withstand the breakdown voltage. 3 3 · Making a junction on a semiconductor substrate with an active area structure Page 30 200531179 VI. Scope of patent application The process flow of the Schottky device further includes: applying an ion implantation mask and a diffusion mask on the active region to make most of the PN junctions arranged alternately. 3 4 · The process step described in item 33 of the scope of patent application, characterized in that the above process steps of applying the ion implantation mask and the diffusion mask further include using a photoresist as the above ion implantation mask and the diffusion mask. 3 5 · The process step described in item 33 of the scope of patent application, characterized in that the process steps of applying the ion implantation mask and the diffusion mask further include using a patterned oxide layer as the ion implantation mask and diffusion Mask. 3 6 · The process step described in item 33 of the scope of patent application, characterized in that the process steps of applying the ion implantation mask and the diffusion mask further include using a patterned nitride layer as the ion implantation mask and diffusion Mask. 37. The process step described in item 33 of the scope of patent application, wherein the process steps of applying the ion implantation mask and the diffusion mask further include using a patterned nitride layer as the ion implantation mask and diffusion. Mask. Page 31, 200531179 VI. Patent application scope 3 8 · The process steps described in item 33 of the patent application scope, characterized in that the above process steps of applying a PN junction ion implantation mask and a diffusion mask are further included in the above semiconductor substrate The above PN junction is fabricated on a single epitaxial layer of the wafer. 3 9 · The process step described in item 33 of the scope of patent application, characterized in that the process steps of applying the PN junction ion implantation mask and the diffusion mask further include a uniformly doped single epitaxial layer on the semiconductor substrate The above-mentioned PN junction is fabricated. 40. The process step described in item 33 of the scope of application for a patent, wherein the process steps of applying the PN junction ion implantation mask and the diffusion mask further include a non-uniform doped single epitaxial layer on the semiconductor substrate. The above-mentioned PN junction is fabricated. 4 1 · The process flow for making a Schottky device with a junction barrier on a substrate with an active region structure in advance, further comprising: applying an ion implantation mask and a diffusion mask on the active region to make an alternate arrangement The majority of PN-PN junctions. 4 2 The process step according to item 41 of the scope of patent application, characterized in that the above process steps of applying the ion implantation mask and the diffusion mask further include using a photoresist as the ion implantation mask and the diffusion mask. Page 32, 200531179 VI. Patent application scope 4 3 · The process steps described in item 41 of the patent application scope, characterized in that the above-mentioned process steps using the ion implantation mask and the diffusion mask further include the use of a patterned oxide The layer serves as the above-mentioned ion implantation mask and diffusion mask. 4 4 · The process step described in item 41 of the scope of patent application, wherein the process steps of applying the ion implantation mask and the diffusion mask further include using a patterned nitride layer as the ion implantation mask and diffusion. Mask. 4 5 · The process step described in item 41 of the scope of patent application, characterized in that the process steps of applying the ion implantation mask and the diffusion mask further include using a patterned nitride layer as the ion implantation mask and diffusion. Mask. 4 6 · The process step described in item 41 of the scope of patent application, characterized in that the process steps of applying the PN-P N junction ion implantation mask and the diffusion mask further include a single epitaxial layer on the semiconductor substrate. Fabricate the PN-PN junction described above. Page 33