CN117317004A - Schottky trench MOS device and manufacturing method - Google Patents

Schottky trench MOS device and manufacturing method Download PDF

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Publication number
CN117317004A
CN117317004A CN202210712929.1A CN202210712929A CN117317004A CN 117317004 A CN117317004 A CN 117317004A CN 202210712929 A CN202210712929 A CN 202210712929A CN 117317004 A CN117317004 A CN 117317004A
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schottky
well
cell
mos device
manufacturing
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李稳
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Hubei Kerui Semiconductor Technology Co ltd
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Hubei Kerui Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0641—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The invention provides a schottky groove MOS device and a manufacturing method, wherein the device comprises the following components: gate oxide, polysilicon electrode, P-well, N+ source, ohmic contact hole and Schottky contact hole; adopting square cell structure including P-well cell and Schottky cell; the P-well is used as a trench MOSFET cell for leading forward operation; the duty cycle of the schottky cell dominates the reverse freewheeling. The reverse recovery time is greatly shortened by utilizing the characteristic of the Schottky diode, and the switching frequency of the trench MOSFET tube is improved.

Description

Schottky trench MOS device and manufacturing method
Technical Field
The invention relates to the technical field of MOSFET (Metal-oxide-semiconductor field-effect transistor), in particular to a Schottky trench MOS device and a manufacturing method thereof.
Background
The trench MOSFET is a semiconductor common power device and comprises three terminals, namely a source electrode, a grid electrode and a drain electrode, wherein the grid electrode is a control end, and the on-off between the source electrode and the drain electrode is controlled by loading voltage to the grid electrode, so that the aim of controlling the on-off of the device is fulfilled.
In the prior art, the conduction characteristic of a trench MOS tube is utilized, and the characteristic of the trench Schottky is utilized.
There is also a diode manufactured by using a MOS structure in a MOS tube, which has a basic structure of: and shorting the grid electrode and the source electrode of the MOS tube to serve as the anode of the diode, and taking the drain electrode as the cathode of the diode.
The inside nature of the trench MOSFET tube is also a PN junction structure, once the forward voltage is larger than the on voltage (about 0.6V) of the PN junction, the inside PN junction is also conducted, so that after the forward voltage disappears, the reverse recovery time of the MOS structure diode is longer, the reverse response time of the MOS structure diode is greatly influenced, and the switching frequency of the diode is lower.
Disclosure of Invention
The present invention has been made in view of the above problems, and has been made to provide a schottky trench MOS device and a method of manufacturing that overcome or at least partially solve the above problems.
According to one aspect of the present invention, there is provided a schottky trench MOS device comprising: gate oxide, polysilicon electrode, P-well, N+ source, ohmic contact hole and Schottky contact hole;
adopting square cell structure including P-well cell and Schottky cell;
the P-well is used as a trench MOSFET cell for leading forward operation;
the duty cycle of the schottky cell dominates the reverse freewheeling.
Optionally, the ratio of the P-well cells to the schottky cells is 3:1.
Optionally, the optimal operating frequency of the MOS device is 75KHZ.
The invention also provides a schottky trench MOS device and a manufacturing method thereof, comprising the following steps: selecting an epitaxial wafer: selecting proper epitaxy according to product definition, and selecting epitaxy with crystal orientation of 110, doping atoms of boron, resistivity of 1 ohm cm and thickness of 10um for a product with withstand voltage of N type 70V;
manufacturing grooves: forming a groove by hard mask CVD, photoresist coating, exposure, development, hard mask dry etching and groove etching;
preparing gate oxide: after forming the groove, introducing oxygen into the furnace tube at a high temperature of 1000 ℃ to enable the oxygen to react with the epitaxial surface, the inner side wall of the groove and the bottom to generate an oxide layer as gate oxygen; thickness is 0.5 microns;
p-well formation: through Pwell photoetching, then using an implantation machine to implant boron ions, wherein the implantation dosage is 1E13, and the energy is 100Kev; removing the photoresist, and forming a P-well by high-temperature annealing at 1100 ℃ for 10 minutes;
manufacturing an N+ source: using an implantation machine to implant phosphorus ions with the dosage of 1E15 and the energy of 100Kev to form an N+ source;
ILD deposition is performed: depositing an oxide film of boron and phosphorus by a CVD mode to form an ILD with the thickness of 0.1 micrometer;
ohmic contact hole formation: forming an ohmic contact hole by photoresist coating, exposing, developing and dry etching, and then forming the ohmic contact hole by boron ion 1E14 and 20Kev injection;
schottky contact hole formation: forming a Schottky contact hole in a dry etching mode through photoresist coating, exposure and development, and then forming the Schottky contact hole in a phosphorus ion implantation mode with the dosage of 1E13 and the energy of 40 Kev;
sputtering of schottky barrier metal: and sputtering titanium and titanium nitride respectively in a physical sputtering mode, wherein the thicknesses of the titanium and the titanium nitride are 30 nanometers and 50 nanometers respectively, so as to form the Schottky barrier metal.
Top metal formation: sputtering aluminum with the thickness of 2 microns in a physical sputtering mode to serve as top metal;
thinning back gold: the back substrate of the wafer is thinned by a physical grinding mode, the final thickness of the wafer is 250 micrometers, and a layer of metallic titanium and metallic silver are sputtered by a physical sputtering mode to form contact metal for packaging conductive adhesive, wherein the thickness of the contact metal is 100 nanometers and 4 micrometers.
Optionally, the selecting the epitaxial wafer specifically includes: an epitaxial wafer having a resistance of 0.4ohm.
Optionally, the schottky adjustment implantation condition is B,9.5E11, 35K.
The invention provides a schottky groove MOS device and a manufacturing method, wherein the device comprises the following components: gate oxide, polysilicon electrode, P-well, N+ source, ohmic contact hole and Schottky contact hole; adopting square cell structure including P-well cell and Schottky cell; the P-well is used as a trench MOSFET cell for leading forward operation; the duty cycle of the schottky cell dominates the reverse freewheeling. The reverse recovery time is greatly shortened by utilizing the characteristic of the Schottky diode, and the switching frequency of the trench MOSFET tube is improved.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a trench MOSFET with a Schottky diode structure in accordance with the present disclosure;
FIG. 2 is a schematic diagram of a cell structure of a trench MOSFET with a Schottky diode structure in accordance with the present invention;
FIG. 3 is a schematic cross-sectional view of a trench MOSFET cell with a Schottky diode structure in accordance with the present invention;
fig. 4 is a process flow of a trench MOSFET device with a schottky diode structure according to the present disclosure;
FIG. 5 is a schematic diagram of a selected epitaxial wafer according to the present disclosure;
FIG. 6 is a schematic illustration of a trench made in accordance with the present disclosure;
FIG. 7 is a schematic illustration of a gate oxide fabricated in accordance with the present disclosure;
FIG. 8 is a schematic illustration of a P-well formation in accordance with the present disclosure;
FIG. 9 is a schematic diagram of a manufacturing N+ source in accordance with the present disclosure;
FIG. 10 is a schematic diagram of an ILD deposition process in accordance with the present disclosure;
FIG. 11 is a schematic view of ohmic contact hole formation according to the present disclosure;
fig. 12 is a schematic diagram of schottky contact hole formation in accordance with the present disclosure;
fig. 13 is a schematic diagram of a schottky barrier metal sputtering of the present disclosure;
FIG. 14 is a schematic illustration of the formation of a top metal of the present disclosure;
fig. 15 is a schematic view of a thinned back gold according to the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terms "comprising" and "having" and any variations thereof in the description embodiments of the invention and in the claims and drawings are intended to cover a non-exclusive inclusion, such as a series of steps or elements.
The technical scheme of the invention is further described in detail below with reference to the accompanying drawings and the examples.
As shown in fig. 1, the highest voltage applied to the schottky diode-equipped trench MOSFET of the present invention is 100V. The N-type electrode of the Schottky diode is connected with the drain electrode of the trench MOSFET, and the P-type electrode is connected with the source electrode of the trench MOSFET.
The invention adopts square cell structure, one part has P-well as trench MOSFET cell, and the other part has no P-well as Schottky cell. The invention relates to an N-type 30V50A MOS, wherein the proportion of cells with P-well and Schottky element cells is 3:1. the cell with P-well plays a leading role in forward operation of the device, and the duty ratio of the Schottky cell plays a leading role in reverse freewheeling; for an N-type 30V50A MOS, this ratio was experimentally demonstrated to achieve the optimum ratio for use at an operating frequency of 75KHZ. The specific design and cross-sectional view are shown in figures 2 and 3 below.
The polysilicon electrode is the control terminal of the device. The bottom of the device is the drain. The drain electrode is connected with a working power supply, and the N+ source is grounded; when the polysilicon electrode is connected with a high level, the device is started, and current flows from the drain electrode at the bottom to N+ source through P-well to form working current; when the polysilicon electrode is connected to the low level, the device is turned off.
As shown in fig. 4, for the N-type 30V50A MOS, the ratio of P-well cells to schottky cells is 3: in addition to 1, the two processes of epitaxial wafer selection and Schottky injection in the process flow are particularly critical, and an epitaxial wafer with the resistance of 0.4ohm.com and the thickness of 6 microns is selected; the conditions of Schottky adjusting injection are B,9.5E11 and 35K, under the combined action of epitaxy and Schottky adjusting injection, the Schottky voltage drop of 0.415V is obtained, the reverse voltage drop of the device is optimized to the greatest extent, and the speed of the device is improved.
The manufacturing method of the Schottky trench MOS device comprises the following steps:
selecting an epitaxial wafer, as shown in fig. 5;
according to the definition of the product, a proper epitaxy is selected, for the product with the withstand voltage of 70V, the crystal orientation is 110, the doping atoms are boron, the resistivity is 1 ohm cm, and the thickness is 10 um.
Making a trench, as shown in fig. 6;
forming a groove by hard mask CVD, photoresist coating, exposure, development, dry etching of the hard mask and groove etching
Making gate oxide as shown in fig. 7;
after forming the groove, oxygen is introduced into the furnace tube at a high temperature of 1000 ℃ to enable the oxygen to react with the epitaxial surface, the inner side wall of the groove and the bottom to generate an oxide layer as gate oxygen. The thickness was 0.5 microns.
P-well formation, as shown in FIG. 8;
using an implantation machine to implant boron ions, wherein the implantation dosage is 1E13, and the energy is 100Kev; then P-well is formed by high temperature annealing at 1100 degrees for 10 minutes.
Making an n+ source, as shown in fig. 9; using an implanter, phosphorus ions were implanted at a dose of 1E15 and an energy of 100Kev to form an n+ source.
ILD deposition is performed as shown in fig. 10; CVD deposited boron and phosphorus oxide films to form ILD with a thickness of 0.1 microns.
Ohmic contact holes were formed by photoresist coating, exposure, development, and dry etching, and boron ions 1E14 and 20Kev were implanted as shown in fig. 11.
Schottky contact holes are formed as shown in fig. 12; schottky contacts were formed by phosphorus ion implantation, at a dose of 1E13, energy of 40 Kev.
Schottky barrier metal sputtering as shown in fig. 13; and sputtering titanium and titanium nitride respectively in a physical sputtering mode, wherein the thicknesses of the titanium and the titanium nitride are 30 nanometers and 50 nanometers respectively, so as to form the Schottky barrier metal.
Top metal formation, as shown in fig. 14; and sputtering aluminum with the thickness of 2 microns by a physical sputtering mode to serve as top metal.
The back gold is thinned as shown in fig. 15. The back substrate of the wafer is thinned by a physical grinding mode, the final thickness of the wafer is 250 micrometers, and a layer of metallic titanium and metallic silver are sputtered by a physical sputtering mode to form contact metal for packaging conductive adhesive, wherein the thickness of the contact metal is 100 nanometers and 4 micrometers.
The beneficial effects are that: schottky is integrated in the MOSFET to greatly increase the reverse recovery speed of the device. The invention optimizes the proportion of P-well cells and Schottky cells, and achieves the balance of maximum performance. The invention optimizes the Schottky voltage drop and improves the speed of the device through Schottky adjustment injection.
The foregoing detailed description of the invention has been presented for purposes of illustration and description, and it should be understood that the invention is not limited to the particular embodiments disclosed, but is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the invention.

Claims (6)

1. A schottky trench MOS device, the device comprising: gate oxide, polysilicon electrode, P-well, N+ source, ohmic contact hole and Schottky contact hole;
adopting square cell structure including P-well cell and Schottky cell;
the P-well is used as a trench MOSFET cell for leading forward operation;
the duty cycle of the schottky cell dominates the reverse freewheeling.
2. The schottky trench MOS device of claim 1 wherein the ratio of the P-well cells to the schottky cells is 3:1.
3. The schottky trench MOS device of claim 1 wherein the MOS device has an optimal operating frequency of 75KHZ.
4. The manufacturing method of the Schottky trench MOS device is characterized by comprising the following steps of:
selecting an epitaxial wafer: selecting proper epitaxy according to product definition, and selecting epitaxy with crystal orientation of 110, doping atoms of boron, resistivity of 1 ohm cm and thickness of 10um for a product with withstand voltage of N type 70V;
manufacturing grooves: forming a groove by hard mask CVD, photoresist coating, exposure, development, hard mask dry etching and groove etching;
preparing gate oxide: after forming the groove, introducing oxygen into the furnace tube at a high temperature of 1000 ℃ to enable the oxygen to react with the epitaxial surface, the inner side wall of the groove and the bottom to generate an oxide layer as gate oxygen; thickness is 0.5 microns;
p-well formation: using an implantation machine to implant boron ions, wherein the implantation dosage is 1E13, and the energy is 100Kev; then forming a P-well by high-temperature annealing at 1100 ℃ for 10 minutes;
manufacturing an N+ source: using an implantation machine to implant phosphorus ions with the dosage of 1E15 and the energy of 100Kev to form an N+ source
ILD deposition is performed: depositing an oxide film of boron and phosphorus by a CVD mode to form an ILD with the thickness of 0.1 micrometer;
ohmic contact hole formation: forming ohmic contact holes by means of photoresist coating, exposure, development, dry etching and the like, and injecting boron ions 1E14 and 20 Kev;
schottky contact hole formation: forming a Schottky contact hole in a dry etching mode through photoresist coating, exposure and development, and then forming a Schottky contact in a phosphorus ion implantation mode with the dosage of 1E13 and the energy of 40 Kev;
sputtering of schottky barrier metal: and sputtering titanium and titanium nitride respectively in a physical sputtering mode, wherein the thicknesses of the titanium and the titanium nitride are 30 nanometers and 50 nanometers respectively, so as to form the Schottky barrier metal.
Top metal formation: sputtering aluminum with the thickness of 2 microns in a physical sputtering mode to serve as top metal;
thinning back gold: the back substrate of the wafer is thinned by a physical grinding mode, the final thickness of the wafer is 250 micrometers, and a layer of metallic titanium and metallic silver are sputtered by a physical sputtering mode to form contact metal for packaging conductive adhesive, wherein the thickness of the contact metal is 100 nanometers and 4 micrometers.
5. The method for manufacturing a schottky trench MOS device of claim 4, wherein the selecting the epitaxial wafer specifically comprises: an epitaxial wafer having a resistance of 0.4ohm.
6. The method of manufacturing a schottky trench MOS device of claim 4 wherein the schottky tuning implant conditions are B,9.5E11, 35K.
CN202210712929.1A 2022-06-22 2022-06-22 Schottky trench MOS device and manufacturing method Pending CN117317004A (en)

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CN202210712929.1A CN117317004A (en) 2022-06-22 2022-06-22 Schottky trench MOS device and manufacturing method

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Application Number Priority Date Filing Date Title
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