CN112466753A - Preparation method of junction field effect transistor device - Google Patents

Preparation method of junction field effect transistor device Download PDF

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CN112466753A
CN112466753A CN202011150276.XA CN202011150276A CN112466753A CN 112466753 A CN112466753 A CN 112466753A CN 202011150276 A CN202011150276 A CN 202011150276A CN 112466753 A CN112466753 A CN 112466753A
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buried layer
type buried
type
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forming
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蒋骞苑
赵德益
吕海凤
郝壮壮
张啸
王允
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Shanghai Wei'an Semiconductor Co ltd
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Shanghai Wei'an Semiconductor Co ltd
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8086—Thin film JFET's

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  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses a preparation method of a junction field effect transistor device, belonging to the field of design and manufacture of semiconductor devices, comprising a silicon wafer, wherein a first N-type buried layer and a first P-type buried layer are formed on the first surface of the silicon wafer and are annealed; growing a first P type epitaxial layer after cleaning; forming a second N-type buried layer in the first P-type epitaxial layer; cleaning again, and growing a second P-type epitaxial layer; forming an N + injection region and a P + injection region; growing a silicon dioxide dielectric layer, and forming a deep groove along the Y-axis direction to form a deep P + doped region; cleaning, and then depositing P + polysilicon; forming a corresponding gate contact hole; forming a drain metal, a first gate metal and a source metal; and forming a second gate metal on the second surface. The invention has the beneficial effects that: the switch has the advantages of low on-resistance, strong grid control capability, low pinch-off voltage, low switch power consumption, low turn-off power consumption and the like; meanwhile, the stability is high, and the circuit is suitable for various constant current source circuits.

Description

Preparation method of junction field effect transistor device
Technical Field
The invention relates to the field of design and manufacture of semiconductor devices, in particular to a preparation method of a junction field effect transistor device.
Background
A Junction Field-Effect Transistor (JFET) is a three-terminal active device with an amplifying function, which is composed of a PN Junction gate, a source, and a drain, and its operating principle is to change the conductivity of a channel by a gate voltage to control an output current. The JFET has the advantages of high input impedance, low power consumption, good switching stability and the like, so that the JFET is widely applied to the fields of power devices, low-noise amplifiers, high-input-impedance circuits and the like.
Junction field effect transistors include depletion mode JFETs and enhancement mode JFETs, with depletion mode JFETs being generally more common. For a depletion type JFET, when no voltage is applied to a grid electrode, the channel resistance is minimum, and a transistor is in a conducting state; when voltage is applied to the grid electrode, the width of a depletion region of the grid control PN junction is changed, so that the thickness of a channel is reduced, the resistance of the channel is increased, the output current is controlled to be reduced, when the voltage applied to the grid electrode is continuously increased, the depletion region of the grid control PN junction is expanded until the conductive channel is pinched off, and the transistor enters a turn-off state.
The JFET manufactured by the traditional technology is usually higher in turn-off voltage while pursuing low on-resistance, which can lead to the increase of switch power consumption and easily cause larger power waste in power electronic equipment, so that aiming at the problems, a JFET device is urgently needed to be designed to meet the requirement of practical use.
Disclosure of Invention
In order to solve the technical problems, the invention provides a preparation method of a junction field effect transistor device, which has the advantages of low on resistance, strong grid control capability, low pinch-off voltage and low switching power consumption.
The technical problem solved by the invention can be realized by adopting the following technical scheme:
the invention provides a preparation method of a junction field effect transistor device, which comprises the following steps:
step S1, providing a silicon wafer, wherein the silicon wafer is provided with a first surface and a second surface, and at least one first N-type buried layer is formed on the first surface of the silicon wafer through a photoetching process and an ion implantation process;
step S2, forming a P-type buried layer at the adjacent side of the first N-type buried layer through a photoetching process and an ion implantation process, and performing high-temperature annealing on the first N-type buried layer and the P-type buried layer to obtain a first N-type buried layer and a P-type buried layer with a certain junction depth;
step S3, cleaning, and forming a first P-type epitaxial layer on the first surface, the first N-type buried layer, and the upper surface of the P-type buried layer;
step S4, forming a second N-type buried layer on the upper surface of the first P-type epitaxial layer by a photolithography process and an ion implantation process;
step S5, cleaning, and forming a second P-type epitaxial layer on the upper surfaces of the first P-type epitaxial layer and the second N-type buried layer;
step S6, forming an N + injection region on the surface of the second P type epitaxial layer through a photoetching process and an ion injection process, and annealing;
step S7, forming a P + injection region on the adjacent side of the N + injection region through a photoetching process and an ion injection process;
step S8, growing silicon dioxide dielectric layers on the second P-type epitaxial layer, the N + injection region and the P + injection region, and forming a deep groove along the Y-axis direction by adopting a photoetching process and a dry etching process;
step S9, forming a deep P + doped region by high-temperature boron source diffusion;
step S10, cleaning by using a cleaning solution, and then depositing P + polysilicon in the deep groove;
step S11, removing a local silicon dioxide dielectric layer through a photoetching process and an etching process to expose the N + injection region, and forming a corresponding gate contact hole above the N + injection region;
step S12, forming drain metal, first grid metal and source metal through a metal sputtering process, a photoetching process and a dry etching process, and adhering a blue film protective layer;
and step S13, thinning the second surface of the silicon wafer, evaporating metal on the second surface to form second grid metal.
Preferably, the silicon wafer is an N + type semiconductor substrate, and the resistivity of the N + type semiconductor substrate is [0.001 Ω cm, 0.01 Ω cm ].
Preferably, the doping implantation element of the first N-type buried layer is antimony or arsenic, the ion implantation dosage is 4E 15-1E 16 per square centimeter, and the implantation energy is 60-120 KeV;
the doping implantation element of the P-type buried layer is boron, the ion implantation dosage is 2E 15-5E 15 per square centimeter, the implantation energy is 60-80 KeV, high-temperature annealing is carried out after the ion implantation, the high-temperature annealing temperature is [1150 ℃, 1200 ℃), and the time is 90-120 minutes, so that the junction depth formed by the P-type buried layer is smaller than the junction depth formed by the first N-type buried layer.
Preferably, the resistivity of the first P-type epitaxial layer is [0.005 Ω cm, 0.01 Ω cm ], the thickness is [6 μm, 8 μm ], the growth temperature for forming the first P-type epitaxial layer is [1140 ℃, 1180 ℃ ], the first N-type buried layer and the P-type buried layer are diffused into the first P-type epitaxial layer, and the junction depth of the upward diffusion of the first N-type buried layer is greater than the junction depth of the upward diffusion of the P-type buried layer.
Preferably, the doping implantation element of the second N-type buried layer is antimony or arsenic, the ion implantation dosage is 6E 15-1E 16 per square centimeter, and the implantation energy is 60-120 KeV.
Preferably, the second P-type epitaxial layer has a resistivity of [0.005 Ω cm, 0.01 Ω cm ], a thickness of [5 μm, 7 μm ], and a growth temperature of [1140 ℃, 1180 ℃ ] at which the second P-type epitaxial layer is formed.
Preferably, the implantation element of the N + implantation region is phosphorus or arsenic, the ion implantation dose is 3E 15-8E 15 per square centimeter, the implantation energy is 100-120 KeV, the annealing temperature for forming the N + implantation region is [950 ℃, 1000 ℃), the time is 30-60 minutes, and the N + implantation region, the first N-type buried layer, and the second N-type buried layer are aligned up and down in the Y-axis direction.
Preferably, the implantation element of the P + implantation region is boron, the ion implantation dose is 2E 15-6E 15 per square centimeter, the implantation energy is 60-80 KeV, and the P + implantation region and the P-type buried layer are vertically aligned in the Y-axis direction.
Preferably, the width of the deep trench is [1 μm, 2 μm ], and the depth is 80% to 85% of the sum of the thicknesses of the first P-type epitaxial layer and the second P-type epitaxial layer.
Preferably, the diffusion dopant source for the high temperature boron source diffusion is borane at a diffusion temperature of [1000 ℃, 1050 ℃ C ] for a period of 60 minutes.
The invention has the beneficial effects that:
the invention provides a preparation method of a junction field effect transistor device, wherein grids are arranged on the upper surface and the lower surface of the device, when the junction field effect transistor device is applied to a circuit, the two grids are connected together, and reverse bias voltage is applied at the same time, so that the capability of accurately controlling current by the grids is realized; due to the design of the second N-type buried layer, the device can be turned off only by applying smaller reverse bias voltage on the grid electrode, so that the turn-off power consumption of the device is reduced by 60% compared with the loss of the traditional technology; when the grid is not applied with bias voltage, the grid has the advantages of lower on-resistance and low on-power consumption; meanwhile, the source electrode and the drain electrode form a deep P + doped region by utilizing deep groove diffusion respectively, and meanwhile, the P + polycrystalline silicon leading-out technology is adopted, so that the current densities of the first P type epitaxial layer and the second P type epitaxial layer are almost the same, the stability is high, and the constant current source circuit is suitable for various constant current source circuits.
Drawings
Fig. 1 to fig. 13 are schematic structural diagrams of steps in a method for manufacturing a junction field effect transistor device according to the present invention:
FIG. 1 is a schematic structural diagram of an embodiment of forming a first N-type buried layer in the present invention;
FIG. 2 is a schematic structural diagram of an embodiment of forming a P-type buried layer in the present invention;
FIG. 3 is a schematic structural diagram of an embodiment of forming a first P-type epitaxial layer in the present invention;
FIG. 4 is a schematic structural diagram of an embodiment of forming a second N-type buried layer in the present invention;
FIG. 5 is a schematic structural diagram of an embodiment of forming a second P-type epitaxial layer in the present invention;
FIG. 6 is a schematic structural diagram of an embodiment of forming an N + implant region in the present invention;
FIG. 7 is a schematic structural diagram of an embodiment of forming a P + implant region in the present invention;
FIG. 8 is a schematic structural diagram of an embodiment of growing a silicon dioxide dielectric layer and forming deep trenches in accordance with the present invention;
FIG. 9 is a schematic structural diagram of an embodiment of forming a deep P + doped region in the present invention;
FIG. 10 is a schematic structural diagram of an embodiment of the present invention for depositing P + polysilicon;
FIG. 11 is a schematic structural diagram of an embodiment of forming a gate contact hole in the present invention;
FIG. 12 is a schematic structural diagram of an embodiment of forming a drain metal, a first gate metal and a source metal in the present invention;
fig. 13 is a schematic structural diagram of a junction field effect transistor device according to an embodiment of the invention after a second gate metal is formed.
Reference numerals:
the silicon chip comprises a silicon chip (1), a first N-type buried layer (21), a P-type buried layer (22), a first P-type epitaxial layer (3), a second N-type buried layer (4), a second P-type epitaxial layer (5), an N + injection region (61), a P + injection region (62), a silicon dioxide dielectric layer (7), a deep groove (81), P + polycrystalline silicon (82), a deep P + doping region (9), a grid contact hole (10), drain metal (110), first grid metal (111), source metal (112) and second grid metal (113).
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The invention provides a preparation method of a junction field effect transistor device, belonging to the field of semiconductor device design and manufacture, as shown in figure 13, comprising the following steps:
step S1, providing a silicon wafer 1, wherein the silicon wafer 1 has a first surface and a second surface, and at least one first N-type buried layer 21(NBL1) is formed on the first surface of the silicon wafer 1 through a photolithography process and an ion implantation process;
step S2, forming a P-type buried layer 22(PBL) at the adjacent side of the first N-type buried layer 21(NBL1) by photolithography and ion implantation, and performing high temperature annealing on the first N-type buried layer 21(NBL1) and the P-type buried layer 22(PBL) to obtain the first N-type buried layer 21(NBL1) and the P-type buried layer 22(PBL) with a certain junction depth;
step S3, cleaning, and forming a first P-type epitaxial layer 3 on the first surface, the first N-type buried layer 21(NBL1) and the upper surface of the P-type buried layer 22 (PBL);
step S4, forming a second N-type buried layer 41(NBL2) on the upper surface of the first P-type epitaxial layer 3 by photolithography and ion implantation;
step S5, cleaning, and forming a second P-type epitaxial layer 5 on the upper surfaces of the first P-type epitaxial layer 3 and the second N-type buried layer 41(NBL 2);
step S6, forming an N + implantation region 61 on the surface of the second P-type epitaxial layer 5 by a photolithography process and an ion implantation process, and annealing;
step S7, forming a P + implantation region 62 on the adjacent side of the N + implantation region 61 by a photolithography process and an ion implantation process;
step S8, growing a silicon dioxide dielectric layer 7 on the second P-type epitaxial layer 5, the N + injection region 61 and the P + injection region 62, and forming a deep groove 81 along the Y-axis direction by adopting a photoetching process and a dry etching process;
step S9, forming a deep P + doped region 9 by high temperature boron source diffusion;
step S10, cleaning by using a cleaning solution, and then depositing P + polysilicon 82 in the deep groove 81;
step S11, removing a local silicon dioxide dielectric layer 7 through a photolithography process and an etching process to expose the N + injection region 61, and forming a corresponding gate contact hole 10 above the N + injection region 61;
step S12, forming a drain metal 110, a first gate metal 111, and a source metal 112 by a metal sputtering process, a photolithography process, and a dry etching process, and attaching a blue film protective layer;
step S13, thinning the second surface of the silicon wafer 1, and evaporating metal on the second surface to form the second gate metal 113.
Specifically, the junction field effect transistor device in the embodiment of the invention includes a silicon wafer 1, a first N-type buried layer 21(NBL1), a P-type buried layer 22(PBL), a first P-type epitaxial layer 3, a second N-type buried layer 41(NBL2), a second P-type epitaxial layer 5, an N + implantation region 61, a P + implantation region 62, a silicon dioxide dielectric layer 7, P + polysilicon 82, a deep P + doping region 9, a drain metal 110, a first gate metal 111, a source metal 112, and a second gate metal 113. The preparation method specifically comprises the following steps:
step S1, as shown in fig. 1, providing a silicon wafer 1 as a semiconductor substrate, wherein the conductivity type impurity of the semiconductor substrate is N-type, and the resistivity thereof is [0.001 Ω × cm, 0.01 Ω × cm ], the silicon wafer 1 has a first surface and a second surface, the first surface of the silicon wafer 1 is subjected to growth of a first N-type buried layer 21(NBL1), and at least one first N-type buried layer 21(NBL1) is grown, it should be noted that the present embodiment does not limit the number thereof, in the present embodiment, the number of the first N-type buried layers 21(NBL1) is two, the two first N-type buried layers 21(NBL1) are spaced apart, and the spacing distance is adjusted according to actual needs;
in a preferred embodiment, the first N-type buried layer 21(NBL1) has an ion implantation element of Sb or As, an ion implantation dose of 4E 15-1E 16 per square centimeter, and an implantation energy of 60-120 KeV.
Step S2, as shown in fig. 2, growing a P-type buried layer 22(PBL) on the adjacent side of the first N-type buried layer 21(NBL1), and then performing a high temperature anneal, wherein the P-type buried layer 22(PBL) is connected to the adjacent side of the first N-type buried layer 21(NBL1), i.e. the distance between the P-type buried layer 22(PBL) and the first N-type buried layer 21(NBL1) is zero, and the junction depths of the P-type buried layer 22(PBL) and the first N-type buried layer 21(NBL1) into the N-type substrate are different due to the different implantation concentrations;
in a preferred embodiment, the P-type buried layer 22(PBL) is doped with boron at an implantation dose of 2E 15-5E 15 per square centimeter and an implantation energy of 60-80 KeV, and is annealed at a high temperature of [1150 ℃ and 1200 ℃ for 90-120 minutes after ion implantation, so that the junction depth formed by the P-type buried layer 22(PBL) is less than the junction depth formed by the first N-type buried layer 21(NBL 1).
Step S3, as shown in fig. 3, cleaning the device in step S2 to remove the impurity particles and native oxide layer on the surface, and growing the first P-type epitaxial layer 3 on the upper surface;
in a preferred embodiment, the resistivity of the first P-type epitaxial layer 3 is [0.005 Ω cm, 0.01 Ω cm ], the thickness is [6 μm, 8 μm ], the growth temperature is [1140 ℃, 1180 ℃ ], the first N-type buried layer 21(NBL1) and the P-type buried layer 22(PBL) are diffused upward into the first P-type epitaxial layer 3 during the high temperature growth process, and the junction depth of the first N-type buried layer 21(NBL1) diffused upward is greater than the junction depth of the P-type buried layer 22(PBL) diffused upward after the epitaxial thermal process because the ion implantation concentration of the first N-type buried layer 21(NBL1) is higher than that of the P-type buried layer 22(PBL), and further the total junction depth of the first N-type buried layer 21(NBL1) is greater than that of the P-type buried layer 22 (PBL).
Step S4, as shown in fig. 4, doping antimony or arsenic on the upper surface of the first P-type epitaxial layer 3, with an ion implantation dose of 6E 15-1E 16 per square centimeter and an implantation energy of 60-120 KeV, to grow the second N-type buried layer 41(NBL2), wherein the size and number of the second N-type buried layer 41(NBL2) are the same as those of the first N-type buried layer 21(NBL1), and are aligned up and down in the Y-axis direction, so that the second N-type buried layer 41(NBL2) and the first N-type buried layer 21(NBL1) share the same reticle;
step S5, as shown in fig. 5, cleaning the device processed in step S4, removing the impurity particles and the native oxide layer on the surface, and growing a second P-type epitaxial layer 5 on the upper surface;
in a preferred embodiment, the second P-type epitaxial layer 5 has a resistivity of [0.005 Ω cm, 0.01 Ω cm ] and a thickness of [5 μm, 7 μm ], the second P-type epitaxial layer 5 is grown at [1140 ℃, 1180 ℃), and the second N-type buried layer 41(NBL2) diffuses upward into the second P-type epitaxial layer 5 after the high temperature treatment.
Step S6, as shown in FIG. 6, injecting phosphorus or arsenic to the upper surface of the second P-type epitaxial layer 5 to form an N + injection region 61, preferably, the ion injection dosage is 3E 15-8E 15 per square centimeter, the injection energy is 100-120 KeV, and then, the N + injection region enters a furnace tube to be subjected to annealing treatment at the annealing temperature of [950 ℃, 1000 ℃ for 30-60 minutes, so that the junction depth of the formed N + injection region 61 is about 2 um;
in a preferred embodiment, the N + implant region 61, the first N-type buried layer 21(NBL1), and the second N-type buried layer 41(NBL2) are vertically aligned in the Y-axis direction, so that the N + implant region 61 may share the same photolithography mask as the first N-type buried layer 21(NBL1) and the second N-type buried layer 41(NBL 2).
Step S7, as shown in FIG. 7, implanting boron element after photolithography treatment on the adjacent side of the N + implantation region 61 to form a P + implantation region 62, wherein the implantation dose of the boron element is 2E 15-6E 15 per square centimeter, and the implantation energy is 60-80 KeV;
in a preferred embodiment, the P + implant region 62 and the P-type buried layer 22(PBL) are aligned up and down in the Y-axis direction, i.e., the P + implant region 62 and the P-type buried layer 22(PBL) may share the same reticle.
In step S8, as shown in FIG. 8, a silicon dioxide dielectric layer 7 with a thickness of [0.8 μm ] is grown on the upper surface of the device obtained in step S7m，1.5μm]The silicon dioxide dielectric layer 7 is used as a barrier layer with excellent barrier property, and then photoetching and dry etching are carried out along the Y-axis direction to form two symmetrical deep grooves 81, wherein the etching gas of the dry etching is chlorine (Cl)2) And sulfur hexafluoride (SF)6) Forming a good silicon groove shape;
in a preferred embodiment, the deep trench 81 has a width of [1 μm, 2 μm ], and the deep trench 81 is deep into the first P-type epitaxial layer 3, and has a specific depth of 80% to 85% of the sum of the thicknesses of the first P-type epitaxial layer 3 and the second P-type epitaxial layer 5.
Step S9, as shown in fig. 9, the device obtained in step S8 is pushed into a furnace apparatus, and boron source diffusion is performed by doping and implanting borane (BH3), since the surface is SiO2Therefore, the implanted diffusion dopant source can only diffuse through deep trench 81 to form deep P + doped region 9, preferably at a temperature of [1000 ℃, 1050 ℃ ]]For 60 minutes;
step S10, as shown in fig. 10, cleaning the device with a cleaning solution to remove the impurity particles and native oxide layer in the deep trench 81, depositing P + polysilicon 82 in the deep trench 81, and removing the polysilicon on the surface by an etching back process to leave only the P + polysilicon 82 in the deep trench 81;
in a preferred embodiment, the cleaning solution contains a certain amount of hydrofluoric acid, which can effectively remove the native oxide layer in the deep trench 81 to ensure that the polysilicon forms a good ohmic contact with the silicon wafer 1 during the subsequent deposition process, wherein the sheet resistance of the P + polysilicon 82 is controlled to [4 Ω, 8 Ω ].
It should be noted that, during the deposition process, polysilicon is deposited while boron source is doped, and as the deposition height of polysilicon increases, the boron source in the deep P + doping region 9 can be more uniformly diffused, and the concentration of the boron source is uniform, so as to avoid that the doped boron source can only diffuse to both sides through the bottom of the deep trench 81, which causes the concentration at the bottom to be too high, and the concentrations at both sides of the top of the deep trench 81 are lower or almost zero.
Step S11, as shown in fig. 11, performing photolithography and etching on the device, and removing the silicon dioxide dielectric layer 7 on the part above the N + injection region 61 to expose the part N + injection region 61 and form two corresponding gate contact holes 10, that is, two gate contact holes 10;
step S12, as shown in fig. 12, performing metal sputtering, photolithography and dry etching on the device to form a drain metal 110, a first gate metal 111 and a source metal 112, wherein the drain metal 110 covers the P + polysilicon 82 in one of the deep trenches 81, the source metal 112 covers the P + polysilicon 82 in the other deep trench 81, the first gate metal 111 is connected to the two gate contact holes 10, and a blue film is pasted on the upper surface of the first gate metal 111;
in step S13, as shown in fig. 13, the second surface of the silicon wafer 1 is thinned, and evaporation metal treatment is performed to form the second gate metal 113 on the back surface, wherein after thinning, the thickness of the silicon wafer 1 is [100 μm, 200 μm ], and the thinner thickness can be beneficial to improving the control capability of the back gate metal on the channel.
Through the technical scheme, when the gate structure is applied to circuit application, the two gates are connected together, reverse bias voltage is applied at the same time, so that a depletion region formed by the N + injection region 61 and the second P-type epitaxial layer 5 is expanded downwards, a depletion region formed by the first N-type buried layer 21(NBL1) and the depletion region formed by the first P-type epitaxial layer 3 is expanded upwards, the width of the depletion region is increased, the width of the first P-type epitaxial layer 3 conducting in the middle is narrowed, the on-resistance is increased, the source and drain current is reduced, and the capability of accurately controlling the current by the gates is realized;
because the device designed by the invention has very strong gate control capability, the on-resistance of the device can be rapidly adjusted only by applying a small reverse bias voltage on the gate, particularly when the device needs to be turned off, when the voltage of the gate is continuously increased, the depletion region formed by the N + injection region 61 and the second P-type epitaxial layer 5 is expanded downwards until being connected with the second N-type buried layer 41(NBL2), the first N-type buried layer 21(NBL1) and the depletion region of the first P-type epitaxial layer 3 are expanded upwards and are also connected with the second N-type buried layer 41(NBL2), and at the moment, the channel is turned off, and the device is turned off; because the design of the middle second N-type buried layer 41(NBL2) can turn off the device only by applying not large reverse bias voltage on the grid, the invention provides a new design junction field effect transistor device, the turn-off power consumption of which is very small and is reduced by 60% compared with the loss of the traditional technology;
when bias voltage is not applied to the grid electrode, the conduction path of the grid electrode is the deep P + doping area 9, the first P type epitaxial layer 3, the second P type epitaxial layer 5, the P type buried layer 22(PBL) and the P + injection area 62 in sequence, the conduction resistance is low, and the conduction power consumption of the device is reduced.
In addition, the two ends of the source electrode and the drain electrode of the invention both adopt deep silicon groove diffusion to form a deep P + region, and simultaneously, the P + polysilicon 82 leading-out technology is applied, so that current can uniformly flow through the device in a conducting state, the current densities of the first P type epitaxial layer 3 and the second P type epitaxial layer 5 are almost the same, the stability is higher, and the invention is suitable for various constant current source circuits.
The invention has the beneficial effects that:
the invention provides a preparation method of a junction field effect transistor device, wherein grids are arranged on the upper surface and the lower surface of the device, when the junction field effect transistor device is applied to a circuit, the two grids are connected together, and reverse bias voltage is applied at the same time, so that the capability of accurately controlling current by the grids is realized; due to the design of the second N-type buried layer 41(NBL2), the device can be turned off only by applying a smaller reverse bias voltage to the gate, so that compared with the loss of the traditional technology, the turn-off power consumption of the device is reduced by 60%; when the grid is not applied with bias voltage, the grid has the advantages of lower on-resistance and low on-power consumption; meanwhile, the source electrode and the drain electrode are respectively diffused by utilizing the deep groove 81 to form the deep P + doping area 9, and meanwhile, the P + polysilicon 82 leading-out technology is adopted, so that the current densities of the first P type epitaxial layer 3 and the second P type epitaxial layer 5 are almost the same, the stability is high, and the constant current source circuit is suitable for various constant current source circuits.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (10)

1. A method for fabricating a junction field effect transistor device, comprising:
step S1, providing a silicon wafer, wherein the silicon wafer is provided with a first surface and a second surface, and at least one first N-type buried layer is formed on the first surface of the silicon wafer through a photoetching process and an ion implantation process;
step S2, forming a P-type buried layer at the adjacent side of the first N-type buried layer through a photoetching process and an ion implantation process, and performing high-temperature annealing on the first N-type buried layer and the P-type buried layer to obtain a first N-type buried layer and a P-type buried layer with a certain junction depth;
step S3, cleaning, and forming a first P-type epitaxial layer on the first surface, the first N-type buried layer, and the upper surface of the P-type buried layer;
step S4, forming a second N-type buried layer on the upper surface of the first P-type epitaxial layer by a photolithography process and an ion implantation process;
step S5, cleaning, and forming a second P-type epitaxial layer on the upper surfaces of the first P-type epitaxial layer and the second N-type buried layer;
step S6, forming an N + injection region on the surface of the second P type epitaxial layer through a photoetching process and an ion injection process, and annealing;
step S7, forming a P + injection region on the adjacent side of the N + injection region through a photoetching process and an ion injection process;
step S8, growing silicon dioxide dielectric layers on the second P-type epitaxial layer, the N + injection region and the P + injection region, and forming a deep groove along the Y-axis direction by adopting a photoetching process and a dry etching process;
step S9, forming a deep P + doped region by high-temperature boron source diffusion;
step S10, cleaning by using a cleaning solution, and then depositing P + polysilicon in the deep groove;
step S11, removing a local silicon dioxide dielectric layer through a photoetching process and an etching process to expose the N + injection region, and forming a corresponding gate contact hole above the N + injection region;
step S12, forming drain metal, first grid metal and source metal through a metal sputtering process, a photoetching process and a dry etching process, and adhering a blue film protective layer;
and step S13, thinning the second surface of the silicon wafer, evaporating metal on the second surface to form second grid metal.
2. The method of claim 1, wherein the silicon wafer is an N + type semiconductor substrate having a resistivity of [0.001 Ω cm, 0.01 Ω cm ].
3. The method of claim 1, wherein the first N-type buried layer is doped with antimony or arsenic at a dose of 4E 15-1E 16 per square centimeter and at an implant energy of 60-120 KeV;
the doping implantation element of the P-type buried layer is boron, the ion implantation dosage is 2E 15-5E 15 per square centimeter, the implantation energy is 60-80 KeV, high-temperature annealing is carried out after the ion implantation, the high-temperature annealing temperature is [1150 ℃, 1200 ℃), and the time is 90-120 minutes, so that the junction depth formed by the P-type buried layer is smaller than the junction depth formed by the first N-type buried layer.
4. The method of claim 1, wherein the first P-type epitaxial layer has a resistivity of [0.005 Ω cm, 0.01 Ω cm ] and a thickness of [6 μm, 8 μm ], the first P-type epitaxial layer is formed at a growth temperature of [1140 ℃, 1180 ℃ ], the first N-type buried layer and the P-type buried layer are diffused into the first P-type epitaxial layer, and a junction depth of the upward diffusion of the first N-type buried layer is greater than a junction depth of the upward diffusion of the P-type buried layer.
5. The method of claim 1, wherein the second N-type buried layer is doped with antimony or arsenic at an ion implantation dose of 6E 15-1E 16 per square centimeter and an implantation energy of 60-120 KeV.
6. The method of claim 1, wherein the second P-type epitaxial layer has a resistivity of [0.005 Ω cm, 0.01 Ω cm ] and a thickness of [5 μm, 7 μm ], and the second P-type epitaxial layer is formed at a growth temperature of [1140 ℃ C., 1180 ℃ C ].
7. The method of claim 1, wherein the N + implant region is formed by implanting phosphorus or arsenic at a dose of 3E 15-8E 15 per square centimeter and at an implant energy of 100-120 KeV, the N + implant region is formed by annealing at [950 ℃, 1000 ℃) for 30-60 minutes, and the N + implant region, the first N-type buried layer, and the second N-type buried layer are aligned up and down in a Y-axis direction.
8. The method of claim 1, wherein the P + implant region is boron, the ion implantation dose is 2E 15-6E 15 per square centimeter, the implantation energy is 60-80 KeV, and the P + implant region and the P-type buried layer are vertically aligned in the Y-axis direction.
9. The method of claim 1, wherein the deep trench has a width of [1 μm, 2 μm ] and a depth of 80-85% of a sum of thicknesses of the first P-type epitaxial layer and the second P-type epitaxial layer.
10. The method of claim 1 wherein the diffusion dopant source for the high temperature boron source diffusion is borane at a diffusion temperature of [1000 ℃, 1050 ℃ C ] for a period of 60 minutes.
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JP2008140805A (en) * 2006-11-30 2008-06-19 Sanyo Electric Co Ltd Semiconductor device
CN108962978A (en) * 2018-07-25 2018-12-07 盛世瑶兰（深圳）科技有限公司 Metal oxide semiconductor field effect tube and its manufacturing method
CN109860047A (en) * 2019-01-08 2019-06-07 福州臻美网络科技有限公司 A kind of power device and preparation method thereof
TWI684277B (en) * 2019-02-20 2020-02-01 新唐科技股份有限公司 Semiconductor devices and methods for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140805A (en) * 2006-11-30 2008-06-19 Sanyo Electric Co Ltd Semiconductor device
CN108962978A (en) * 2018-07-25 2018-12-07 盛世瑶兰（深圳）科技有限公司 Metal oxide semiconductor field effect tube and its manufacturing method
CN109860047A (en) * 2019-01-08 2019-06-07 福州臻美网络科技有限公司 A kind of power device and preparation method thereof
TWI684277B (en) * 2019-02-20 2020-02-01 新唐科技股份有限公司 Semiconductor devices and methods for forming the same

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