200529286 九、發明說明： 【發明所屬之技術領域】 本發明是有關於用以於一種鍍敷裝置與鍍敷方法、其將 鍍敷應用於基板上，以及有關及半導體裝置之製造方法。 【先前技術】 在近年來在半導體裝置操作速度之改善要求達成：此裝 置之高整合密度與高功能表現。因此，連接至各元件之接 線變得更精密且多層。在目前為符合此精密與多層之接 線’此接線是以此種方式形成：將銅（Cu)填入通孔與在中 間層絕緣薄膜上所形成接線溝槽、以及然後將不須要之cu 去除而形成。 此電解電鍍方法目前使用於將從填滿速度之觀點填入 銅。然而，當半導體晶圓（以下稱為"晶圓浸入於電鍍溶液 中時，則種子層可能會溶解及/或泡沫將存留在將被電鍍晶 圓之表面上。因此，令人期望限制此種子層之溶解及/或泡 沫之存留，因為其會造成洞之發生。 為解決此問題而採用一種方法··將晶圓浸入於電鍍溶液 中，同時在晶圓與陽極間施加電壓且將晶圓傾斜。在此處， 當將晶圓浸入於電鍍溶液中時，其所被施加之電壓與當電 鍍時所施加之電壓實質上相同。作為另一種方法，據瞭解 是將參考電極設置在晶圓附近，且將晶圓浸入於電鍍溶液 中，而同時控制晶圓之電位至由此參考電極所提供之預先 設定之電位（例如：請參考美國專利案號us 6,551，843之說 明書與美國專利案號us 6,562,204之說明書）。 97666.doc 200529286 然而，在此前一案中，將傾斜晶圓浸入於電鍍溶液中而 同時對其施加電壓，以致於所形成電鑛薄膜之厚度在先前 濕潤之部份與稍後濕潤之部份是不同，以及因此所造成之 問題是：難以均勻地形成電鍍薄膜。在此前一案中，此參 考電極是設置在晶圓附近，以致於在電鍍時此參考電極干 擾到電場，以及因此其問題是：難以均勻地形成電鍵薄膜。 【發明内容】 根據本發明之一觀點，提供一種電鍍裝置包括：電鑛溶 液槽其儲存電鍍溶液；保持具其握持住基板，於該電鍍溶 液槽中種子層係形成於此基板上；第一陽極設置在電鍍溶 液槽中，其在其氧化還原電位中具有較構成種子層之金屬 在其氧化還原電位中更多陽極材料，且可電性連接至由今 保持具所握持住之基板之種子層；以及第一陽極設置在電 鍍溶液槽中，其可在由該保持具所握持住之基板之種子層 間施加電壓。 规 扠供一種電鍍方法，其包括以 根據本發明之另 了步驟：將第“陽極連接至基板之種子層，其中第一陽極 疋设置在電鍍溶液中，其構成材料之氧化還原電位較構成 ，子層之金屬之氧化還原電佳更具陽極性；將基板於電錢 溶液中潤濕；以及藉由在種子層與設置於電錢溶液中之第 二陽極間施加電壓，將基板電鍍。 根據本發明之又一觀點，提供一種電鍍方法，其包括以 下步驟：在表面上具有凹人部份之基板上形成種子^= 致於填人於凹人部份之之-部份巾；將第—部份^連接 97666.doc 200529286 至種子層，其中此第一陽極是設置在此電鍍溶液中，且其 在其氧化還原電位中具有較構成種子層之金屬在其氧化還 原電位中更多陽極材料；將基板溼潤，在其上第一陽極電 性連接至電鍍溶液中之種子層；在種子層上形成電鍍薄 膜，以致於藉由在設置在電鍍容液中之種子層與第二陽極 間軛加電壓而被填入於凹入部份中；以及將填入於凹入部 伤以外之電鍍薄膜與填入於凹入部份以外之種子層去除。 【實施方式】 第一實施例 以下％明本發明之第一實施例。圖丨為根據第一實施例之 電鍍裝置之概要垂直截面圖；以及圖2為根據第一實施例之 晶圓之概要垂直截面圖。 如同於圖1中所示，此電鍍裝置1係包含電鍍容液槽2等， 而行成為圓柱體形狀。此電鍍溶液槽2是用於儲存電鍍溶 液其主要成份為電解溶液，例如像是硫酸銅溶液。 此用於握持晶圓w之保持具3是設置在電鍍溶液槽2上。 此保持具3是以.所謂面向下之方式握住晶圓，以致於此晶圓 W被電鍵之表面朝下。 保持具3係包含保持具主體3八等，用於將晶圓w實質上水 平握持於其中。保持具主體3 A之下表面該開啟，以致於此 晶圓W被電鍍之表面在電鍍溶液中濕潤。 在保持具主體3 A中握持具有以下結構之晶圓界。如圖2 所不’此晶圓w包括層間絕緣薄膜1〇1。此層間絕緣薄膜1〇1 係包s低"電常數絕緣材料，例如：si〇F、si〇c、多孔矽 97666.doc 200529286 石等。此層間絕緣薄膜101形成於設有半導體元件（未圖示） 等之半導體基板上。在層間絕緣薄膜1〇1中形成通孔1〇1 A 作為凹入部份，以及形成接線溝渠1〇1B作為凹入部份。 在層間絕緣薄膜1〇1上形成阻障金屬層1〇2用於防止構成 以下說明之電鍍薄膜104之金屬擴散至層間絕緣薄膜1(H。 阻障金屬層102是由導電材料構成。此種導電材料係包含金 屬，例如：钽（Ta)、鈦（Ti)等，或包含金屬氮化物，例如： TiN、TaN、WN等，其具有小的金屬擴散係數而構成電鍍 薄膜104。附帶說明，此阻障金屬層1〇2可以由此等金屬或 金屬氮化物之成層材料所形成。 種子層103形成於阻障金屬層1〇2上用於使電流流經晶圓 W。種子層1〇3係包含金屬例如銅（Cu)。 接觸3B設置在保持具主體3八之内表面上且與種子層 接觸。此接觸3B裝附於密封環3C，其防止電鍍溶液接觸3B 接觸。藉由將晶圓W壓在密封環3C上而將其開口封閉，此 密封環3C可以彈性變形，以致於密封環3C將晶圓w牢固地 固定。因此，限制電鍍溶液與接觸3B接觸。 此傾斜與旋轉機構4裝附於保持具3，用於將晶圓w對電 鍍溶液之溶液表面傾斜與旋轉。此傾斜與旋轉機構4將晶圓 w相對於電鍍溶液之溶液表面傾斜，且將保持具3以及其他 所有旋轉。 此上升/下降機構（未圖示）裝附於保持具3而將晶圓W上 升/下降。此上升/下降機構將保持具3與其上所有其他上升/ 下降。藉由啟動此上升/下降機構，此保持具3被上升/下降， 97666.doc 200529286 以致於可將晶圓W浸入於雷拉w 、錢，谷液中或從電鍍溶液拉出。 此實質上碟形陽極5(第_ (弟一％極）是設置在電鍍溶液槽2之 底部位置。接觸3B與陽極5帝柯、*社 私ί±連接至電源6，用於經由接 觸3Β將電Μ供應至種子層1()3與陽極之間。 此實質上桿形之犧牲陽極7(第一陽極）、其可電性連接至 種子層103,是設置在電錄溶㈣2巾由晶圓％與陽極$所夹 區域之外。在此實施例中’此犧牲陽極7是設置在電鑛溶液 槽2之側壁附近。 犧牲陽極7之構成材料之氧化還原電位較構成種子層1〇3 之金屬之氧化還原電位更具陽極性。作為此種材料可以列 舉例如：金屬、金屬氧化物、以及碳(c)等。特定而言，例 如，當種子層103係包含銅時，則犧牲陽極7可以包含辞 (Zn)、鈕（Ta)、此兩者之氧化物、碳（c)等。形成犧牲陽極7 其與電鍍溶液之接觸面積小於晶圓w與電鍍溶液之接觸面 積0 刀隔壁8设置於電鍍溶液槽2中。此分隔壁8將晶圓w濕潤 與浸入之區域與犧牲陽極7設置之區域分開。分隔壁8防 止·晶圓W濕潤與浸入區域中之電鐘溶液、與設置犧牲陽 極7區域之電鍍溶液相混合，但其建構將此兩區域電性連 接。附帶說明，可以使用膜而非分隔壁8。 然後討論電鍍裝置1之操作狀態。圖3為流程圖其顯示根 據本實施例電錢過程之流程。第4A至4D圖為概要圖其顯示 根據此實施例電鍍裝置之操作狀態。第5A與5B圖為根據此 實施例為晶圓W之概要垂直截面圖。 97666.doc -10- 200529286 士同於第4A圖中所示，晶圓w之種子層工〇3與犧牲陽極7 電性連接，而晶圓W是由保持具3握持（步驟1}。然後，啟動 此傾斜與旋轉機構4將晶圓w旋轉且將晶圓W傾斜（步驟2)。 然後，啟動上升/下降機構，在此狀態中將晶圓w濕潤且 浸入於電鍍溶液中，如同於第43圖中所示（步驟3)。在將晶 圓冒濕’閏且/叉入於電錢溶液中後，將種子層1 與犧牲陽極 7包II連接解除連接，如同於第4C圖中所示（步驟4)。 然後，啟動電源6，以致於在種子層1〇3與陽極5之間施加 電壓，如同於第4D圖中所示，隨後將晶圓w電鍍（步驟5)。 如同於第5A圖中所示，在將電鍍薄膜1〇4形成至預先設定厚 度之後，停止施加電壓以致於電鍍停止（步驟6)。最後，啟 動此上升/下降機構，將晶圓W從電鍍溶液拉出（步驟7)。 附帶說明，在此之後，對晶圓W實施熱處理（回火），以及 因此成長種子層103與電鍍薄膜1〇4之晶體。因此，形成接 線薄膜其為種子層1〇3與電鍍薄膜104之組合。然後，如同 於第5B圖所示，藉由例如化學機械拋光（CMP)將在層間絕 緣溥膜101上之’阻障金屬層1〇2與接線薄膜之不須要部份各 別去除，以致於在通孔1〇1八與接線溝渠1〇1B中阻障金屬層 102與接線薄膜存留。因此，在通孔101A與接線溝渠101B 中形成接線105。 在本實施例中’由於將晶圓w濕潤且浸入於電鍍溶液 中’同時種子層103與犧牲陽極7是在電性連接狀態中，而 可以限制由於種子層溶解所造成之洞孔，以及可以改善電 鍍溥膜104上薄膜厚度表面之均勻度。這即是說，當晶圓… 97666.doc 200529286 濕潤且浸入於電鍍溶液中、且種子層103與犧牲陽極7是在 電性連接狀態中時，在種子層103上產生還原反應，且在犧 牲陽極7上產生氧化反應，這是因為犧牲陽極7之構成材料 之氧化還原電位較構成種子層103之金屬之氧化還原電位 更具陽極性。因此，可以限制種子層1〇3之溶解，以致於可 以限制洞孔發生。在另一方面，在種子層103上產生還原反 應’且因此將種子層1 〇 3電鑛。然而，相較於下列情形其可 以減少對晶圓W施加電鍍之數量：當晶圓w濕潤且浸入於電 鑛溶液中，而將與當電鍍時之實質上相同之電壓施加於種 子層103與陽極5之間。此外，藉由使犧牲陽極7對電鐘溶液 之接觸面積較小，而可使電鍍數量更加減少。因此，限制 當晶圓W濕潤且浸入於電鍍溶液中施加至晶圓％電艘數量 之不均勻，以致於可以改善電鍍薄膜1〇4之膜厚度表面之均 勻度。 在本實施例中，由於晶圓W濕潤且浸入之區域與犧牲陽 極7設置之區域是以分隔壁8分開，因此可以限制此溶解之 犧牲陽極7沉積，至晶圓W。即，當晶圓w濕潤且浸入於電鍍 >谷液中、且此種子層1 〇3與犧牲陽極7是在電性連接狀態 中，則取決於其構成材料，此犧牲陽極7可以溶解於電鍍溶 液中。在此處，如果犧牲陽極7溶解，則此所溶解材料可以 禁止在晶圓w上產生電鍍。反之，在本實施例中，此晶圓w 濕潤且浸入之區域與犧牲陽極7設置之區域是以分隔壁$分 開，因此即使當犧牲陽極7溶解時，亦可以避免禁止將晶圓 W電鍍。 97666.doc -12- 200529286 在本實轭例中，由於是在種子層ι〇3與犧牲陽極7之電性 連接解除後將此晶’顿，可以改善電鑛薄錢4上薄膜 厚度表面之均勻度。即，當藉由在種子層與陽極$間施 加電壓將晶圓W雷雜 -r- ^ ^ „ U ^私鍍、而種子層ι〇3與犧牲陽極7是在電性 連接狀態中時，其電場分佈可能不均勻。反之，在本實施 例中纟於日3圓|是在種子層1()3與犧牲陽極7之電性連接 解除後被電鍍，而可以避免電場分佈不均勻。因此，可以 改善電鍍薄膜104之膜厚度表面之均勻度。 θ此外，在本實施例中，由於犧牲陽極7是設置在晶圓W與 陽極5所夾區域之外，當晶圓w電鍍時，電場分佈少有不均 勻者。因此，可以改善電鍍薄膜1〇4之膜厚度表面之均勻度。 (舉例） 以下說明-例。在此例中可以觀察電鑛之填滿狀態。 在此例中使用在以上第一實施例中所說明之電鍍裝置。 所使用之電鍍溶液其主要成份為硫酸溶液，以及使用包含 鋅之犧牲陽極。此外，使用如下所形成之晶圓。藉由熱氧 化在矽基板上形成100 111厚之氧化物薄膜，以及然後藉由使 用化學氣相沉積（CVD)法在氧化物薄膜形成大約i μιη厚之 層間絕緣薄膜。此外，藉由光學餘刻過程（ρΕρ)與姓刻，在 氧化物薄膜上形成〇·〇9 μηι寬300 nm深之接線溝渠。在此之 後在層間絕緣薄膜上藉由使用賤鐘法形成由组（Ta)構成1 5 nm厚之阻障金屬層，以及在阻障金屬層上形成包含銅8〇nm 厚之種子層。附帶說明，此等薄膜之厚度是在層間絕緣薄 膜平面上所測得之值，在其中並未形成接線溝渠。 97666.doc -13- 200529286 藉由使用上述電鑛裝置晶圓等、以及在第一實施例中所 說明相同方法將晶圓電鍍，以致於電鑛將接線溝渠填至一 半南度。在此時觀察到在晶園中央與邊緣部份電鍍之填滿 狀態。 附帶說明，當比較例1與本例比較時，可以觀察到在此浸 入於電鍍溶液中之晶圓中央與邊緣部份電鍍之填滿狀態， 而在種子層與陽極間並未施加電壓。此外，作為比較例2， 可以觀察到在此浸入於電鍍溶液中之晶圓中央與邊緣部份 電鎪之填滿狀態，而將與當電鍍時實質上相同之電壓施加 介於種子層與陽極之間。 現在說明觀察之結果。纟i與表2顯示根據本例以及比較 例1以及2之觀察結果。 較例1 比較ίϊϊ __f填滿 半填落 _半填滿 全填滿 一 -—~-— 比較例2 無洞？ 中央 邊緣200529286 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a plating device and a plating method, which applies plating to a substrate, and a method for manufacturing a semiconductor device. [Prior art] In recent years, improvements in the operation speed of semiconductor devices have been achieved: high integration density and high performance of this device. Therefore, the wiring to each component becomes more precise and multilayered. At present, in order to meet this precision and multilayer wiring, this wiring is formed by filling copper (Cu) into the through hole and forming a wiring groove on the interlayer insulating film, and then removing unnecessary cu And formed. This electrolytic plating method is currently used for filling copper from the viewpoint of filling speed. However, when a semiconductor wafer (hereinafter referred to as " wafer is immersed in a plating solution, the seed layer may be dissolved and / or foam will remain on the surface to be plated. Therefore, it is desirable to limit this The dissolution of the seed layer and / or the retention of the foam, as it will cause the occurrence of holes. To solve this problem, a method is adopted. The wafer is immersed in a plating solution, a voltage is applied between the wafer and the anode, and the crystal is The circle is inclined. Here, when the wafer is immersed in a plating solution, the voltage applied to the wafer is substantially the same as the voltage applied when plating. As another method, it is understood that the reference electrode is placed on the crystal The wafer is immersed in a plating solution near the circle, and the potential of the wafer is controlled to a preset potential provided by the reference electrode (for example, please refer to the specification of US Patent No. 6,551,843 and the US Patent Instruction No. us 6,562,204). 97666.doc 200529286 However, in the previous case, the tilted wafer was immersed in a plating solution while voltage was applied to it, so that The thickness of the power deposit film is different between the previously wetted part and the later wetted part, and the problem caused by this is that it is difficult to uniformly form the electroplated thin film. In the previous case, this reference electrode was provided on the crystal It is near the circle, so that the reference electrode interferes with the electric field during plating, and therefore the problem is that it is difficult to uniformly form an electric bond film. [Summary of the Invention] According to an aspect of the present invention, there is provided an electroplating device including: an electric ore solution tank which The plating solution is stored; the holder holds the substrate, and a seed layer is formed on the substrate in the plating solution tank; the first anode is disposed in the plating solution tank, and has a metal that constitutes the seed layer in its redox potential More anode material in its redox potential, and can be electrically connected to the seed layer of the substrate held by the present holder; and the first anode is arranged in the plating solution tank, which can be placed in the holder by the holder A voltage is applied between the seed layers of the substrate being held. The electroplating method includes a step of plating according to another aspect of the present invention: The electrode layer is connected to the seed layer of the substrate. The first anode is set in the plating solution. The redox potential of the constituent material is better than that of the constituent layer. The redox potential of the metal in the sublayer is better than that of the anode. Wetting; and electroplating the substrate by applying a voltage between the seed layer and a second anode disposed in the money solution. According to still another aspect of the present invention, a plating method is provided, which includes the following steps: Seeds are formed on the concave part of the substrate ^ = to fill the concave part of the-part of the towel; connect the first part ^ 97666.doc 200529286 to the seed layer, where the first anode is set at The electroplating solution has more anode materials in its redox potential than the metal constituting the seed layer in its redox potential; the substrate is wetted and the first anode is electrically connected to the seed in the electroplating solution Forming a plating film on the seed layer so that it is filled in the recessed portion by applying a voltage between the seed layer and the second anode provided in the plating volume; and Plated film other than the concave portion is filled with the wound other than the recessed portion of the seed layer is removed. [Embodiment] First Embodiment The following describes the first embodiment of the present invention. Fig. 丨 is a schematic vertical sectional view of a plating apparatus according to the first embodiment; and Fig. 2 is a schematic vertical sectional view of a wafer according to the first embodiment. As shown in FIG. 1, the plating apparatus 1 includes a plating tank 2 and the like, and the rows have a cylindrical shape. The electroplating solution tank 2 is used to store the electroplating solution, and its main component is an electrolytic solution, such as a copper sulfate solution. The holder 3 for holding the wafer w is provided on the plating solution tank 2. This holder 3 holds the wafer in a so-called face-down manner so that the surface of the wafer W is faced down by the key. The holder 3 includes a holder main body 38 and the like for holding the wafer w substantially horizontally therein. The lower surface of the holder main body 3A should be opened, so that the surface of the wafer W to be plated is moistened in the plating solution. The wafer body having the following structure is held in the holder body 3A. As shown in FIG. 2, the wafer w includes an interlayer insulating film 101. This interlayer insulating film 101 is made of a low " electric constant insulating material, such as SiOF, SiOC, porous silicon 97666.doc 200529286, etc. This interlayer insulating film 101 is formed on a semiconductor substrate provided with a semiconductor element (not shown) and the like. A through-hole 10A is formed as a recessed portion in the interlayer insulating film 101, and a wiring trench 101B is formed as a recessed portion. A barrier metal layer 102 is formed on the interlayer insulating film 101 to prevent the metal constituting the plating film 104 described below from diffusing into the interlayer insulating film 1 (H. The barrier metal layer 102 is made of a conductive material. The conductive material contains a metal, such as tantalum (Ta), titanium (Ti), or the like, or a metal nitride, such as TiN, TaN, WN, etc., which has a small metal diffusion coefficient to constitute the plating film 104. Incidentally, The barrier metal layer 102 may be formed of such a metal or metal nitride layering material. The seed layer 103 is formed on the barrier metal layer 102 to allow a current to flow through the wafer W. The seed layer 10 The 3 series contains a metal such as copper (Cu). The contact 3B is provided on the inner surface of the holder body 38 and contacts the seed layer. The contact 3B is attached to the seal ring 3C, which prevents the plating solution from contacting the 3B contact. The wafer W is pressed on the sealing ring 3C to close the opening. The sealing ring 3C can be elastically deformed so that the sealing ring 3C firmly fixes the wafer w. Therefore, the contact of the plating solution with the contact 3B is restricted. This tilt and rotation Mechanism 4 attached to holder 3 It is used to tilt and rotate the wafer w with respect to the solution surface of the plating solution. The tilt and rotation mechanism 4 tilts the wafer w with respect to the solution surface of the plating solution, and will rotate the holder 3 and all other mechanisms. This raising / lowering mechanism (Not shown) the wafer W is raised / lowered by being attached to the holder 3. This raising / lowering mechanism raises and lowers the holder 3 and all other raising / lowering thereon. By activating this raising / lowering mechanism, the holder 3 Was raised / lowered, 97666.doc 200529286, so that the wafer W can be immersed in Leila w, money, valley liquid or pulled out from the plating solution. This is essentially a dish-shaped anode 5 (the first (the first) It is set at the bottom of the plating solution tank 2. The contact 3B and the anode 5 are connected to the power source 6 for supplying electricity M between the seed layer 1 () 3 and the anode via the contact 3B. This substantially rod-shaped sacrificial anode 7 (the first anode), which can be electrically connected to the seed layer 103, is disposed outside the area between the recording solution 2 and the wafer% and the anode $. In this embodiment The 'this sacrificial anode 7 is disposed near the side wall of the electric mineral solution tank 2. The redox potential of the constituent material of the anode 7 is more anodic than the redox potential of the metal constituting the seed layer 103. Examples of such materials include metals, metal oxides, and carbon (c). Specific and In other words, for example, when the seed layer 103 is made of copper, the sacrificial anode 7 may include a Zn (Zn), a button (Ta), an oxide of the two, carbon (c), etc. The sacrificial anode 7 is formed with a plating solution. The contact area is smaller than the contact area between the wafer w and the plating solution. The knife partition wall 8 is provided in the plating solution tank 2. This partition wall 8 separates the area where the wafer w is wet and immersed from the area where the sacrificial anode 7 is provided. The partition wall 8 The wafer W is prevented from being wet and immersed in the electric clock solution in the area and mixed with the plating solution in the area where the sacrificial anode 7 is provided, but its structure electrically connects the two areas. Incidentally, a film may be used instead of the partition wall 8. Then, the operation state of the plating apparatus 1 will be discussed. Fig. 3 is a flowchart showing the flow of the power money process according to this embodiment. 4A to 4D are schematic diagrams showing the operation state of the plating apparatus according to this embodiment. 5A and 5B are schematic vertical sectional views of a wafer W according to this embodiment. 97666.doc -10- 200529286 As shown in Figure 4A, the seed layer of wafer w is electrically connected to sacrificial anode 7, and wafer W is held by holder 3 (step 1). Then, the tilting and rotating mechanism 4 is activated to rotate the wafer w and tilt the wafer W (step 2). Then, the ascending / descending mechanism is activated, and in this state, the wafer w is wet and immersed in the plating solution, as if It is shown in Fig. 43 (step 3). After the wafer is wetted and / forked into the electricity solution, the seed layer 1 is disconnected from the sacrificial anode 7 package II, as in Fig. 4C. (Step 4). Then, the power source 6 is turned on so that a voltage is applied between the seed layer 103 and the anode 5, as shown in FIG. 4D, and then the wafer w is plated (Step 5). As shown in FIG. 5A, after the plating thin film 104 is formed to a predetermined thickness, the application of voltage is stopped so that the plating stops (step 6). Finally, the ascending / descending mechanism is activated to remove the wafer W from the plating. The solution is pulled out (step 7). Incidentally, after that, the wafer W is heat-treated (tempered), and Therefore, the crystal of the seed layer 103 and the plating film 104 is grown. Therefore, a wiring film is formed which is a combination of the seed layer 103 and the plating film 104. Then, as shown in FIG. 5B, for example, chemical mechanical polishing ( CMP) The unnecessary metal barrier layer 102 and the unnecessary portion of the wiring film on the interlayer insulating film 101 are removed separately, so that the barrier metal is formed in the through hole 108 and the wiring trench 101B. The layer 102 and the wiring film remain. Therefore, the wiring 105 is formed in the through hole 101A and the wiring trench 101B. In this embodiment, 'because the wafer w is wet and immersed in the plating solution', the seed layer 103 and the sacrificial anode 7 are In the electrical connection state, it is possible to limit the holes caused by the dissolution of the seed layer, and to improve the uniformity of the thickness of the film on the electroplated film 104. This means that when the wafer ... 97666.doc 200529286 is wet and When immersed in the plating solution and the seed layer 103 and the sacrificial anode 7 are in an electrically connected state, a reduction reaction occurs on the seed layer 103 and an oxidation reaction occurs on the sacrificial anode 7 because of the structure of the sacrificial anode 7 The redox potential of the material is more anodic than the redox potential of the metal constituting the seed layer 103. Therefore, the dissolution of the seed layer 103 can be restricted so that the occurrence of holes can be restricted. On the other hand, in the seed layer 103 A reduction reaction is generated on the surface and thus the seed layer is 103 ore. However, it can reduce the amount of plating applied to the wafer W compared to the following cases: When the wafer w is wet and immersed in the electric ore solution, the A voltage substantially the same as that when plating is applied between the seed layer 103 and the anode 5. In addition, by making the contact area of the sacrificial anode 7 to the clock solution smaller, the amount of plating can be further reduced. Therefore, the unevenness of the number of% electric boats applied to the wafer when the wafer W is wet and immersed in the plating solution is limited, so that the uniformity of the film thickness surface of the plated film 104 can be improved. In this embodiment, since the region where the wafer W is wet and immersed and the region where the sacrificial anode 7 is provided are separated by the partition wall 8, it is possible to limit the deposition of the dissolved sacrificial anode 7 to the wafer W. That is, when the wafer w is wet and immersed in the electroplating > valley liquid, and the seed layer 103 and the sacrificial anode 7 are in an electrically connected state, depending on the constituent materials, the sacrificial anode 7 can be dissolved in In plating solution. Here, if the sacrificial anode 7 is dissolved, the dissolved material can inhibit plating on the wafer w. Conversely, in this embodiment, the region where the wafer w is wet and immersed is separated from the region where the sacrificial anode 7 is disposed, so even when the sacrificial anode 7 is dissolved, the plating of the wafer W can be avoided. 97666.doc -12- 200529286 In this real yoke example, since the crystal layer is removed after the electrical connection between the seed layer ι03 and the sacrificial anode 7 is released, it is possible to improve the Evenness. That is, when the wafer W is plated by applying a voltage between the seed layer and the anode $, and the seed layer ι03 and the sacrificial anode 7 are in an electrically connected state, Its electric field distribution may not be uniform. On the contrary, in this embodiment, it is 3 yen | It is electroplated after the electrical connection between the seed layer 1 () 3 and the sacrificial anode 7 is released, so that the uneven electric field distribution can be avoided. Therefore Can improve the uniformity of the film thickness surface of the plated film 104. θ In addition, in this embodiment, since the sacrificial anode 7 is disposed outside the area sandwiched between the wafer W and the anode 5, when the wafer w is plated, the electric field There are few uneven distributions. Therefore, the uniformity of the film thickness surface of the electroplated thin film 104 can be improved. (Example) The following explanations-examples. In this example, you can observe the filling state of the electric ore. Use in this example The electroplating device described in the first embodiment above. The electroplating solution used is mainly a sulfuric acid solution, and a sacrificial anode containing zinc is used. In addition, a wafer formed as follows is used. The silicon substrate is thermally oxidized Over 100 111 thick oxides Film, and then an approximately 1 μm thick interlayer insulating film is formed on the oxide film by using a chemical vapor deposition (CVD) method. In addition, an optical epitaxial process (ρΕρ) and a surname are formed on the oxide film 〇 · 09 μηι wide wiring trench with a depth of 300 nm. After that, a barrier metal layer consisting of a group (Ta) with a thickness of 15 nm was formed on the interlayer insulating film by using a low-frequency method, and the barrier metal layer was formed. A seed layer containing copper at a thickness of 80 nm is formed thereon. Incidentally, the thickness of these films is a value measured on the plane of the interlayer insulating film, and no wiring trench is formed therein. 97666.doc -13- 200529286 By The wafer was electroplated using the above-mentioned power mining device wafer and the like, and the same method described in the first embodiment, so that the power mining filled the wiring trench to half south. At this time, it was observed in the center and edge of the crystal garden It is noted that when Comparative Example 1 is compared with this example, the full state of plating in the center and edge of the wafer immersed in the plating solution can be observed, and the seed layer and anode Occasionally No voltage was applied. In addition, as Comparative Example 2, it was possible to observe the state of filling the electrodes in the center and edge portions of the wafer immersed in the plating solution, and to apply substantially the same voltage as when plating was between Between the seed layer and the anode. The observation results will now be described. 纟 i and Table 2 show the observation results according to this example and Comparative Examples 1 and 2. Comparative Example 1 Comparison ϊϊ __f Fill half fill _ Half fill full fill I-— ~ -— Comparative Example 2 No hole? Central edge
有洞孔 系同孔 士同於表1中所不，根據比較例ι電鍍將晶圓中央與邊緣 部份之接線溝渠填滿至-半高度。然…同於表2中所 不，根據比較例1在晶圓中央與邊緣部份產生洞孔。因此可 以想像：洞孔之產生是由於種子層溶解。 此外，如表1中所*，根據比較例2電鑛將晶圓中央部份 97666.doc -14- 200529286 之接線溝渠填滿至一半高度，但在晶圓之邊緣部份，藉由 電鑛將接線溝渠完全填滿。同時如表2所示，根據比較例2 在晶圓邊緣部份形成孔。因此可以想像，洞孔之產生並不 因為是種子層溶解，而是因為當晶圓浸入於電鍍溶液中時 在適當填入情況下並未實施電鍍。 反之，如同表1中所示，根據此例在晶圓中央與邊緣部份 電鑛將接線溝渠填至—半高度。此外，如表2中所示，根據 此例在晶圓中央與邊緣部份產生洞孔。 從此等結果可以証實，當晶圓浸入於電鍍溶液中且種子 層與犧牲陽極是在電性連接狀態中時，較以下情形難以形 成洞孔：當晶圓浸入於電鍍溶液中在此狀態中種子層與陽 極間未施加電壓；以及而且較以下情形容易改善電鍍薄膜 上薄膜厚度表面之均勻度：當晶圓浸入於電鍍溶液中在此 狀悲中種子層與陽極間施加電壓。 第一實施例 以下況明第二實施例。在此實施例中說明當使用碳形成 犧牲陽極之情形。圖6為根據第此實施例電鍍裝置之概要垂 直截面圖。 如同與第一實施例中相同，犧牲陽極7是設置在電鍍溶液 槽2中。本實施例之犧牲陽極7係包含碳。在此處，在使用 含碳之犧牲陽極7之情形中，即使當晶圓界浸入於電鍍溶液 中且種子層103與犧牲陽極7是在電性連接狀態中時，犧牲 陽極7幾乎不溶解。因此，當使用含碳之犧牲陽極7時，可 以如同第6圖_所不將分隔壁8去除，因為所溶解之犧牲陽 97666.doc 200529286 極7並不會干擾到對晶圓w之電鍍。 【圖示簡單說明】 在並不受限於在以上實施例中所說明之内容，可以 ^不㈣本發明之精神之範圍中在各構件等之結構、材 讚^及配置中作適當改變。以上實施例中所說明當晶圓 Μ:%極5傾斜時將晶圓w電鑛之情形，但在晶圓w對陽極$ 貫貝上。平形時，亦可將晶圓w電錄。此外，在以上實施例 中曰曰圓w疋保持在面朝下之方式，但晶圓w是保持在所謂 面朝上之方式，其中晶圓W被電鍍之表面朝上。 圖1為根據第一實施例之電鍍裝置之概要垂直截面圖； 圖2為根據第一實施例之晶圓之概要垂直截面圖； 圖3為流程圖其顯示根據第一實施例電鍍過程之流程·， 圖4A至4D為概要圖其顯示根據第一實施例電鍍裝置之 操作狀態； 圖5 A至5B為根據第一實施例之晶圓之概要垂直截面 圖；以及 圖6為根據第·二實施例電鍍裝置之概要垂直截面圖。 【主要元件符號說明】 1 電鍍裝置 2 電鍍溶液槽 3 保持具 3A 保持具主體 3B 接觸 3C 密封環 97666.doc 200529286 4 傾斜與旋轉機構 5 陽極 6 電源 7 犧牲陽極 8 分隔壁 101 層間絕緣薄膜 101A 通孔 101B 接線溝渠 102 阻障金屬層 103 種子層 104 電鍍薄膜 105 接線 w 晶圓 97666.doc -17-Holes are the same as those in Table 1. According to Comparative Example I, the wiring trenches at the center and edge of the wafer are filled to -half the height. However, as in Table 2, holes were formed in the center and edge portions of the wafer according to Comparative Example 1. Therefore, it is conceivable that the holes are generated due to the dissolution of the seed layer. In addition, as shown in Table 1 *, according to Comparative Example 2, the electric ore fills the wiring trench of the central portion of the wafer 97666.doc -14-200529286 to half the height, but at the edge of the wafer, the electric ore Fill the wiring trench completely. At the same time, as shown in Table 2, holes were formed in the edge portion of the wafer according to Comparative Example 2. Therefore, it can be imagined that the holes are not generated because the seed layer is dissolved, but because the wafers are immersed in the plating solution and the plating is not performed under the proper filling conditions. Conversely, as shown in Table 1, according to this example, the electrical ore fills the wiring trenches to a half height in the center and edge portions of the wafer. In addition, as shown in Table 2, holes were formed in the center and edge portions of the wafer according to this example. From these results, it can be confirmed that when the wafer is immersed in the plating solution and the seed layer and the sacrificial anode are in an electrically connected state, it is more difficult to form a hole than the following: When the wafer is immersed in the plating solution, the seed layer is in this state No voltage is applied to the anode; and it is easier to improve the uniformity of the film thickness surface on the electroplated film than when the voltage is applied between the seed layer and the anode when the wafer is immersed in the electroplating solution. First Embodiment The second embodiment will be described below. In this embodiment, a case where a sacrificial anode is formed using carbon is explained. Fig. 6 is a schematic vertical sectional view of a plating apparatus according to this embodiment. As in the first embodiment, the sacrificial anode 7 is provided in the plating solution tank 2. The sacrificial anode 7 of this embodiment contains carbon. Here, in the case of using the carbon-containing sacrificial anode 7, even when the wafer boundary is immersed in the plating solution and the seed layer 103 and the sacrificial anode 7 are in an electrically connected state, the sacrificial anode 7 is hardly dissolved. Therefore, when the carbon-containing sacrificial anode 7 is used, the partition wall 8 can be removed as shown in Fig. 6 because the dissolved sacrificial anode 97666.doc 200529286 electrode 7 does not interfere with the plating of the wafer w. [Brief description of the diagram] Without being limited to the content described in the above embodiments, the structure, materials, and configuration of each component and the like can be appropriately changed within the scope of the spirit of the present invention. In the above embodiment, the wafer w is mined when the wafer M:% pole 5 is tilted, but the wafer w is on the anode. In the flat shape, the wafer w can also be recorded. In addition, in the above embodiment, the circle w is kept in a face-down manner, but the wafer w is kept in a so-called face-up manner, in which the surface of the wafer W to be plated faces up. 1 is a schematic vertical cross-sectional view of a plating apparatus according to a first embodiment; FIG. 2 is a schematic vertical cross-sectional view of a wafer according to a first embodiment; FIG. 3 is a flowchart showing a flow of a plating process according to the first embodiment 4A to 4D are schematic diagrams showing the operation state of the plating apparatus according to the first embodiment; FIGS. 5A to 5B are schematic vertical cross-sectional views of the wafer according to the first embodiment; and FIG. 6 is a diagram according to the second embodiment. A schematic vertical cross-sectional view of an example plating apparatus. [Description of main component symbols] 1 Plating device 2 Plating solution tank 3 Holder 3A Holder body 3B Contact 3C Seal ring 97666.doc 200529286 4 Tilt and rotation mechanism 5 Anode 6 Power source 7 Sacrificial anode 8 Partition wall 101 Interlayer insulation film 101A Hole 101B Wiring trench 102 Barrier metal layer 103 Seed layer 104 Plating film 105 Wiring wafer 97666.doc -17-