US20050145500A1

US20050145500A1 - Plating apparatus, plating method, and manufacturing method of semiconductor device

Info

Publication number: US20050145500A1
Application number: US10/998,970
Authority: US
Inventors: Hiroshi Toyoda; Yoshitaka Matsui; Kazuyuki Yahiro; Junsei Yamabe; Shiro Mishima; Takahito Nagamatsu
Original assignee: Individual
Current assignee: Toshiba Corp
Priority date: 2003-12-01
Filing date: 2004-11-30
Publication date: 2005-07-07
Also published as: TWI250552B; CN100342062C; JP2005163080A; TW200529286A; CN1624208A

Abstract

According to an embodiment of the present invention, a plating apparatus, including: a plating solution tank configured to store a plating solution; a holder configured to hold a substrate on which a seed layer is formed in said plating solution tank; a first anode disposed in said plating solution tank, composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer, and electrically connectable to the seed layer of the substrate held by said holder; and a second anode disposed in said plating solution tank, capable of applying a voltage between the seed layer of the substrate held by holder, is provided.

Description

CROSS-REFERENCE TO THE INVENTION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-401773, filed on Dec. 1, 2003; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to, a plating apparatus and a plating method which applies plating on a substrate, and a manufacturing method of a semiconductor device.
2. Description of the Related Art
In recent years, improvement in operating speed of a semiconductor device is required to achieve high integration density and high function of the device. Accordingly, wiring to connect each element becomes finer and multilayered. At present, to correspond to this finer and multilayered wiring, wiring is formed by filling Cu in via holes and wiring trenches formed on an interlayer insulation film, and then removing unnecessary Cu.
Currently, an electrolytic plating method is used for filling Cu from the point of view of a filling speed. However, when a semiconductor wafer (hereinafter, referred to as a ‘wafer’) is immersed in a plating solution, it is possible that a seed layer is dissolved and/or bubbles remain on a surface to be plated of a wafer. It is desirable to restrain these dissolution of the seed layer and/or the retention of bubbles because they may cause the occurrence of voids.
To solve these problems, a method to immerse a wafer in a plating solution while applying a voltage between the wafer and an anode, and tilting the wafer, is adopted. Here, when the wafer is immersed in the plating solution, a voltage being substantially the same as is applied when plating is applied. As another method, it is known that a reference electrode is disposed in the vicinity of a wafer, and the wafer is immersed in a plating solution while controlling the electric potential of the wafer to a predetermined electric potential by the reference electrode (for example, refer to the specification of U.S. Pat. No. 6,551,483, and the specification of U.S. Pat. No. 6,562,204).
However, in the former case, the wafer is tilted to be immersed in the plating solution while applying a voltage thereto, so the amounts of plating film to be formed are different between the early wetted portion and the later wetted portion, and thus there is a problem that it is difficult to form the plating film uniformly. In the latter case, the reference electrode is disposed in the vicinity of the wafer, so an electric field is disturbed by the reference electrode at the time of plating, and thus there is a problem that it is difficult to form the plating film uniformly.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, a plating apparatus, including: a plating solution tank configured to store a plating solution; a holder configured to hold a substrate on which a seed layer is formed in said plating solution tank; a first anode disposed in said plating solution tank, composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer, and electrically-connectable to the seed layer of the substrate held by said holder; and a second anode disposed in said plating solution tank, capable of applying a voltage between the seed layer of the substrate held by said holder, is provided.
According to another aspect of the present invention, a plating method, including: electrically connecting a first anode to a seed layer of a substrate, wherein the first anode is disposed in a plating solution, and composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer; wetting the substrate in the plating solution; and plating the substrate by applying a voltage between the seed layer and a second anode disposed in the plating solution, is provided.
According to still another aspect of the present invention, a manufacturing method of a semiconductor device, including: forming a seed layer on a substrate having a recessed portion on the surface, so as to be filled in a part of the recessed portion; electrically connecting a first anode to the seed layer, wherein the first anode is disposed in a plating solution, and composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer; wetting the substrate on which the first anode is electrically connected to the seed layer in the plating solution; forming a plating film on the seed layer so as to be filled in the recessed portion, by applying a voltage between the seed layer and a second anode disposed in the plating solution; and removing the plating film other than the one filled in the recessed portion and the seed layer other than the one filled in the recessed portion, is provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic vertical cross-sectional view of a plating apparatus according to a first embodiment.
FIG. 2 is a schematic vertical cross-sectional view of a wafer according to the first embodiment.
FIG. 3 is a flowchart showing the flow-of a plating process according to the first embodiment.
FIG. 4A to FIG. 4D are schematic views showing the operating state of the plating apparatus according to the first embodiment.
FIG. 5A and FIG. 5B are schematic vertical cross-sectional views of a wafer according to the first embodiment.
FIG. 6 is a schematic vertical cross-sectional view of a plating apparatus according to a second embodiment.

DESCRIPTION OF THE EMBODIMENTS

First Embodiment

Hereinafter, a first embodiment will be described. FIG. 1 is a schematic vertical cross-sectional view of a plating apparatus according to the present embodiment, and FIG. 2 is a schematic vertical cross-sectional view of a wafer according to the present embodiment.
As shown in FIG. 1, a plating apparatus 1 is composed of a plating solution tank 2, and so on, formed in a cylindrical shape. The plating solution tank 2 is for storing a plating solution whose main constituent is an electrolytic solution, for example, such as aqueous copper-sulfate solution.
A holder 3 to hold a wafer W (substrate) is disposed above the plating solution tank 2. The holder 3 holds the wafer W in a so-called facedown manner so that a surface to be plated of the wafer W faces downward.
The holder 3 is composed of a holder main body 3A and so on, for housing the wafer W inside thereof substantially horizontally. A lower surface of the holder main body 3A opens so that the surface to be plated of the wafer W is to be wetted in a plating solution.
In the holder main body 3A, the wafer W having the following structure is housed. The wafer W includes an interlayer insulation film 101 as shown in FIG. 2. The interlayer insulation film 101 is composed of a low dielectric constant insulation material, for example, SiOF, SiOC, porous silica, or the like. The interlayer insulation film 101 is formed above a semiconductor substrate provided with a semiconductor element (not shown), or the like. In the interlayer insulation film 101, via holes 101A as a recessed portion and wiring trenches 101B as the recessed portion are formed.
On the interlayer insulation film 101, a barrier metal layer 102 is formed for inhibiting the diffusion of metal composing a later-described plating film 104 to the interlayer insulation film 101. The barrier metal layer 102 is made of a conductive material. Such a conductive material is composed of such as metal, for example, Ta, Ti, or the like, or metal nitride, for example, TiN, TaN, WN, or the like, having a small diffusion coefficient of metal composing the plating film 104 therein. Incidentally, the barrier metal layer 102 may be formed of layered material of these metal or metal nitride.
A seed layer 103 is formed on the barrier metal layer 102 for flowing a current through the wafer W. The seed layer 103 is composed of metal, for example, such as Cu.
A contact 3B is disposed on inner surface of the holder main body 3A to bring into contact with the seed layer 103. The contact 3B is attached to a seal ring 3C which inhibits the contact of the plating solution with the contact 3B. By pressing the wafer W onto the seal ring 3C so as to block off the opening thereof, the seal ring 3C is elastically deformed, so that the seal ring 3C sticks fast to the wafer W. Consequently, the contact of the plating solution with the contact 3B is restrained.
A tilting and rotating mechanism 4 for tilting the wafer W relative to the solution surface of the plating solution and rotating the wafer W is attached to the holder 3. The tilting and rotating mechanism 4 tilts the wafer W relative to the solution surface of the: plating solution and rotates the holder 3 and all.
A hoisting/lowering mechanism (not shown) to hoist/lower the wafer W is attached to the holder 3. The hoisting/lowering mechanism hoists/lowers the holder 3 and all. By activating the hoisting/lowering mechanism, the holder 3 is hoisted/lowered, so that the wafer W is immersed in the plating solution or pulled out of the plating solution.
A substantially disk-shaped anode 5 (second anode) is disposed at the bottom position of the plating solution tank 2. The contact 3B and the anode 5 are electrically connected to a power supply 6 for applying a voltage between the seed layer 103 and the anode 5 via the contact 3B.
A substantially bar-shaped sacrificial anode 7 (first anode) which is electrically connectable to the seed layer 103 is disposed outside-of the region sandwiched by the wafer W and the anode 5 in the plating solution tank 2. In the present embodiment, the sacrificial anode 7 is disposed in the vicinity of the side-wall of the plating solution tank 2.
The sacrificial anode 7 is composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer 103. As such a material, for example, metal, metal oxide, carbon (C), or the like, can be cited. Specifically, for example, when the seed layer 103 is composed of Cu, the sacrificial anode 7 is possible to be composed of Zn, Ta, oxides of those, C, or the like. The sacrificial anode 7 is formed to have a smaller contact area with the plating solution than the contact area of the wafer W width the plating solution.
A partition wall 8 is disposed in the plating solution tank 2. The partition wall 8 separate the region where the wafer W is wetted and immersed, from the region where the sacrificial anode 7 is disposed. The partition wall 8 is preventing the mixture of the plating solution in the region where the wafer W is wetted and immersed, and the plating solution in the region where the sacrificial anode 7 is disposed, but it is configured to connect the both regions electrically. Incidentally, a membrane may be used instead of the partition wall 8.
Hereinafter, an operating state of a plating apparatus 1 will be described. FIG. 3 is a flowchart showing the flow of a plating process according to the present embodiment. FIG. 4A to FIG. 4D are schematic views showing the operating state of the plating apparatus 1 according to the present embodiment, and FIG. 5A and FIG. 5B are schematic vertical cross-sectional views of the wafer W according to the present embodiment.
As shown in FIG. 4A, the seed layer 103 of the wafer W and the sacrificial anode 7 are electrically connected while the wafer W is held by a holder 3 (Step 1). After that, the tilting and rotating mechanism 4 is activated to rotate the wafer W and tilt the wafer W (Step 2).
Next, the hoisting/lowering mechanism is activated in that status to wet the wafer W and immerse the wafer W in the plating solution as shown in FIG. 4B (Step 3). After the wafer W is wetted and immersed in the plating solution, the electrical connection between the seed layer 103 and the sacrificial anode 7 is disconnected as shown in FIG. 4C (Step 4).
After that, the power supply 6 is activated, so that a voltage is applied between the seed layer 103 and the anode 5 as shown in FIG. 4D, then the wafer W is plated (Step 5). As shown in FIG. 5A, after the plating film 104 is formed up to the predetermined thickness, the application of the voltage is stopped, so that the plating is stopped (Step 6). Finally, the hoisting/lowering mechanism is activated to pull the wafer W out of the plating solution (Step 7).
Incidentally, after that, a heat treatment (annealing) is applied to the wafer W, and thereby crystals of the seed layer 103 and the plating film 104 grow up. Accordingly, a wiring film being a combination-of the seed layer 103 and the plating film 104 is formed. Next, as shown in FIG. 5B, unnecessary portions of the barrier metal film 102 and the wiring film on the interlayer insulation film 101 are removed respectively by, for example, a Chemical Mechanical Polishing (CMP) so that the barrier metal film 102 and the wiring film existing in the via holes 101A and the wiring trenches 101B remain respectively. Consequently, a wiring 105 is formed in the via holes 101A and the wiring trenches 101B.
In the present embodiment, since the wafer W is wetted and immersed in the plating solution while the seed layer 103 and the sacrificial anode 7 are in the electrically connected status, the occurrence of voids which is caused by dissolution of a seed layer can be restrained, and the uniformity in a surface of the filmy thickness on the plating film 104 can be improved. That is to say, a reduction-reaction occurs on the seed layer 103 and an oxidization reaction occurs on the sacrificial anode 7, when the wafer W is wetted, and immersed in the plating solution while the wafer-W and the sacrificial anode 7 are in the electrically connected status, because the sacrificial anode 7 is composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer 103. Therefore, it is possible to restrain the dissolution of the seed layer 103, so that it is possible to restrain the occurrence of voids. On the other hand, the reduction reaction occurs on the seed layer 103, and thereby the seed layer 103 is plated. However, it is possible to reduce the amount of plating applied with the wafer W compared to the case when the wafer W is wetted and immersed in the plating solution while a voltage being substantially the same as the voltage when plating, is applied between the seed layer 103 and the anode 5. Moreover, the amount of plating is even more reduced by making the contact area of the sacrificial anode 7 to the plating solution smaller. Therefore, the non-uniformity of the amount-of plating applied to the wafer W when the wafer W is wetted and immersed in the plating solution is restrained, so that it is possible to improve the uniformity in the surface of the film thickness on the plating film 104.
In the present embodiment, since the region where the wafer W is wetted and immersed and the region where the sacrificial anode 7 is disposed are separated by the partition-wall 8, it is possible to restrain the precipitation of the dissolved sacrificial anode 7 to the wafer W. Namely, when the wafer W is wetted and immersed in the plating solution while the seed layer 103 and the sacrificial anode 7 are in the electrically connected status, the sacrificial anode 7 may be dissolved into the plating solution depending on they composing material thereof. Here, if the sacrificial anode 7 is dissolved, the dissolved material may inhibit the plating on the wafer W. On the contrary, in the present embodiment, the region where the wafer W is wetted and immersed and the region where the sacrificial anode 7 is disposed, are separated by the partition wall 8, and therefore it is possible to avoid the inhibition of the plating to the wafer W even when the sacrificial anode 7 is dissolved.
In the present embodiment, since the wafer W is plated after the electrical connection between the seed layer 103 and the sacrificial anode 7 is disconnected, the uniformity in the surface of the film thickness on the plating film 104 can be improved. Namely, when the wafer W is plated by applying a voltage between the seed layer 103 and the anode 5 while the seed layer 103 and the sacrificial anode 7 are in the electrically connected status, it is possible that the electric field distribution may be in disorder. On the contrary, in the present embodiment, since the wafer W is plated after the electrical connection between the seed layer 103 and the sacrificial anode 7 is disconnected, the disorder of electric field distribution can be avoided. Therefore, the uniformity in the surface of the film thickness on the plating film 104 can be improved.
Besides, in the present embodiment, since the sacrificial anode 7 is disposed outside of the region sandwiched by the wafer W and the anode 5, the electric field distribution is rare to be in disorder when the wafer W is plated. Consequently, the uniformity in the surface of the film thickness on the plating film 104 can be improved.

EXAMPLE

Hereinafter, an example will be explained. In the present examples a filled status of a plating is observed.
In the present example, a plating 7 apparatus described in the above first embodiment is used. A plating solution whose main constituent is aqueous copper sulfate solution is used, and a sacrificial anode composed of Zn is used. Besides, a wafer which is formed as follows is used. An oxide film of 100 nm thickness is formed on an Si substrate by a thermal oxidation, and thereafter an interlayer insulation film of approximately 1 μm thickness is formed on the oxide film by using a Chemical Vapor Deposition (CVD) method. Further, wiring trenches having 0.09 μm width and 300 nm depth are formed on the interlayer insulation film by Photo Engraving Process (PEP) and etching. After that, a barrier metal layer of 15 nm thickness composed of Ta is formed by using a sputtering method on the interlayer insulation film, and a seed layer of 80 nm thickness composed of Cu is formed on the barrier metal layer. Incidentally, these film thicknesses are values measured on the plane of the interlayer insulation film in which the wiring trenches are not formed.
The wafer is plated so that the plating is filled up to the half height of wiring trenches by using the above-described plating apparatus and wafer and so on, and the same method described in the first embodiment. The filled status of plating at the center and edge portions of the wafer at that time is observed.
Incidentally, as a comparative example 1 to compare with the present example, the filled status of plating at the center and, edge portions of the wafer which is immersed to the plating solution while a voltage is not applied between the seed layer and the anode is also observed. Besides, as a comparative example 2, the filled, status of plating at the center and edge portions of the wafer which is immersed in the plating solution while a voltage being substantially the same as when plating, is applied between the seed layer and the anode is also observed.
Results of the observation is described. Table 1 and Table 2 show the results-of the observation-according to the present example and comparative examples 1 and 2.

TABLE 1

COMPARATIVE COMPARATIVE

EXAMPLE EXAMPLE 1 EXAMPLE 2

CENTER HALF FILLED HALF FILLED HALF FILLED

EDGE HALF FILLED HALF FILLED FULLY FILLED

TABLE 2


	COMPARATIVE	COMPARATIVE
EXAMPLE	EXAMPLE 1	EXAMPLE 2

CENTER	WITHOUT VOID	WITH VOID	WITHOUT VOID
EDGE	WITHOUT VOID	WITH VOID	WITH VOID

As shown in Table 1, the platings are filled up to half height of the wiring trenches at both the center and edge portions of the wafer according to the comparative example 1. However, as shown in Table 2, voids occurred at the center and edge portions of the wafer according to the comparative example 1. It is conceivable that the voids occurred because the seed layer is dissolved.
Besides, as shown in Table 1, the plating is filled up to half height of the wiring trenches at the center portion of the wafer according to the comparative example 2, but at the edge portion of the wafer, the wiring trenches are fully filled by the plating. Meanwhile, as shown in Table 2, voids occurred at the edge portions of the wafer according to the comparative example 2. It is conceivable that the voids occurred not because the seed layer is dissolved but because the plating is not applied under; the appropriate filling condition when the wafer is immersed in the plating solution.
On the contrary, as shown in Table 1, the platings are filled up to half height of the wiring trenches at both the center and edge portions of the wafer according to the example. Besides, as shown in Table 2, no void occurred at the center and edge portions of the wafer according to the example.
From these results, it is verified that when the wafer is immersed in the plating solution while the seed layer and the sacrificial anode is in electrically connected status, it is hard to occur the voids than the case when the wafer is immersed in the plating solution in the status that no voltage is applied between the seed layer and the anode, and also, the uniformity in the surface of the film thickness on the plating film can be improved than the case when the wafer is immersed in the plating solution while a voltage is applied between the seed layer and the anode.

Second Embodiment

Hereinafter, a second embodiment will be described. In the present embodiment, the case when a sacrificial anode formed of carbon is used is explained. FIG. 6 shows a schematic vertical cross-sectional view of a plating apparatus according to the present embodiment.
As it is the same as the first embodiment, a sacrificial anode 7 is disposed in a plating solution tank 2. The sacrificial anode 7 of the present embodiment is composed of carbon. Here, in the case when the sacrificial anode 7 composed of carbon is used, the sacrificial anode 7 is hardly dissolved even when a wafer W is immersed in a plating solution while a seed layer 103 and the sacrificial anode 7 are in an electrically connected status. Accordingly, when the sacrificial anode 7 composed of carbon is used, a partition wall 8 can be removed as shown in FIG. 6 because the dissolved sacrificial anode 7 does not disturb the plating to the wafer W.
The present invention is not limited to the contents described in the above embodiments, and appropriate changes in the structure, the materials, the arrangement of each member, and so on may be made within a range not departing from the sprit of the present invention. In the above embodiments, the case that the wafer W is plated-while the wafer W is tilted relative to the anode 5 is described, but, the wafer W can be plated while the wafer W is substantially in parallel with the anode 5. Further, in the above embodiments, the wafer W is held in the facedown manner, but the wafer W, can be held in a so-called face-up manner, in which the surface to be plated of the wafer W faces upward.

Claims

1. A plating apparatus, comprising:

a plating solution tank configured to store a plating; solution;

a holder configured to hold a substrate on which a seed layer is formed in, said plating solution tank;

a first anode disposed in said plating solution tank, composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer, and electrically connectable to the seed layer of the substrate held by said holder; and

a second anode disposed in said plating solution tank, capable of applying a voltage between the seed layer of the substrate held by said holder.

2. The plating apparatus according to claim 1, further comprising:

a partition wall or a membrane which is disposed in said plating solution tank, and separates the region where the substrate held by said holder is immersed in the plating solution-from the region where said first anode is disposed.

3. The plating apparatus according to claim 1, wherein said first anode is composed of metal, metal oxide, or carbon.

4. The plating apparatus according to claim 3, wherein the seed layer is composed of Cu, and said first anode is composed of Zn, Ta, oxides of those, or C.

5. The plating apparatus according to claim 1, wherein said first anode is disposed outside of the region sandwiched by the substrate held by said holder and said second anode.

6. The plating apparatus according to claim 1, wherein said first anode is formed to have a smaller contact area with the plating solution than a contact area of the substrate with the plating solution.

7. A plating method, comprising:

electrically connecting a first anode to a seed layer of a substrate,

wherein the first anode is disposed in a plating solution, and composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer;

wetting the substrate in the plating solution; and

plating the substrate by applying a voltage between the seed layer and a second anode disposed in the plating solution.

8. The plating method according to claim 7, further comprising:

disconnecting the electrical connection between the first anode and the seed layer between said wetting the substrate in the plating solution and said plating the substrate.

9. The plating method according to claim 7, wherein said wetting the substrate in the plating solution is performed while separating the region where the substrate is wetted in the plating solution from the region where the first anode is disposed by a partition wall or a membrane.

10. The plating method according to claim 7, wherein the first anode is composed of metal, metal oxide, or carbon.

11. The plating method according to claim 10, wherein the seed layer is composed of Cu, the first anode is composed of Zn, Ta, oxides of those, or C.

12. The plating method according to claim 7, wherein the first-anode is disposed outside of the region sandwiched by the substrate and the second anode.

13. The plating method according to claim 7, wherein the first anode has a smaller contact area with the plating solution than a contact area of the substrate with the plating solution.

14. A manufacturing method of a semiconductor device, comprising:

forming a seed layer on a substrate having a recessed portion on the surface, so as to be filled in a part of the recessed portion;

electrically connecting a first anode to the seed layer,

wetting the substrate on which the first anode is electrically connected to the seed layer in the plating solution;

forming a plating film on the seed layer so as to be filled in the recessed portion, by applying a voltage between the seed layer and a second anode disposed in the plating solution; and

removing the plating film other than the one filled in the recessed portion and the seed layer other than the one filled in the recessed portion.

15. The manufacturing method according to claim 14, further comprising:

disconnecting the electrical connection between the first anode and the seed layer, between said wetting the substrate in the plating solution and said forming the plating film.

16. The manufacturing method according to claim 14, wherein said wetting the substrate in the plating solution is performed while separating the region where the substrate is wetted in the plating solution from the region where the first anode is disposed by a partition-wall or a membrane.

17. The manufacturing method according to claim 14, wherein the first anode is composed of metal, metal oxide, or carbon.

18. The manufacturing method according to claim 17, wherein the seed layer-is composed of Cu, the first anode is composed of Zn, Ta, oxides of those, or C.

19. The manufacturing method according to claim 14, wherein the first anode is disposed outside of the region sandwiched by the substrate and the second anode.

20. The manufacturing method according to claim 14, wherein the first anode has a smaller contact area with the plating solution than a contact area of the substrate with the plating solution.