CN100342062C - Electroplate device, electroplate method and method for manufacturing semiconductor device - Google Patents
Electroplate device, electroplate method and method for manufacturing semiconductor device Download PDFInfo
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- CN100342062C CN100342062C CNB2004100965542A CN200410096554A CN100342062C CN 100342062 C CN100342062 C CN 100342062C CN B2004100965542 A CNB2004100965542 A CN B2004100965542A CN 200410096554 A CN200410096554 A CN 200410096554A CN 100342062 C CN100342062 C CN 100342062C
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- 238000000034 method Methods 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title description 3
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000007747 plating Methods 0.000 claims abstract description 30
- 238000009713 electroplating Methods 0.000 claims description 101
- 239000013078 crystal Substances 0.000 claims description 72
- 238000007654 immersion Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 238000005192 partition Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 238000002791 soaking Methods 0.000 claims 2
- 230000033116 oxidation-reduction process Effects 0.000 abstract 2
- 239000010405 anode material Substances 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 60
- 239000010410 layer Substances 0.000 description 57
- 239000011229 interlayer Substances 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 230000007246 mechanism Effects 0.000 description 8
- 239000010949 copper Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000006722 reduction reaction Methods 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/002—Cell separation, e.g. membranes, diaphragms
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/10—Electrodes, e.g. composition, counter electrode
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D21/00—Processes for servicing or operating cells for electrolytic coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
According to an embodiment of the present invention, a plating apparatus, including: a plating solution tank configured to store a plating solution; a holder configured to hold a substrate on which a seed layer is formed in said plating solution tank; a first anode disposed in said plating solution tank, composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer, and electrically connectable to the seed layer of the substrate held by said holder; and a second anode disposed in said plating solution tank, capable of applying a voltage between the seed layer of the substrate held by holder, is provided.
Description
Cross reference of the present invention
The present invention is based on the Japanese patent application No.2003-401773 of application in 1 day December in 2003 formerly, and require its right of priority; Its full content here is incorporated herein by reference.
Technical field
The present invention relates to be used for galvanized electroplanting device and electro-plating method on substrate, and the manufacture method of semiconducter device.
Background technology
Recent years, requirement improves the working speed of semiconducter device, to realize the high density of integration and the high function of device.Therefore, it is thinner and be multiwalled to be connected to the wiring of each element.At present, corresponding to this thinner multilayer wiring,, remove unnecessary Cu then and form wiring by filling Cu in the via hole that on interlayer dielectric, forms and the wire laying slot.
Now, from the viewpoint of filling speed, use electrolytic plating method to fill Cu.But when in semiconductor wafer (hereinafter being called ' wafer ') the immersion plating solution, inculating crystal layer may dissolve and/or want leave bubble on the galvanized surface at wafer.Wish to suppress the dissolving of these inculating crystal layers and/or the bubble of reservation, because they can cause the appearance in cavity.
In order to address these problems, adopt in the wafer immersion plating solution, between wafer and anode, apply voltage simultaneously, and the method for inclination wafer.Here, when in the wafer immersion plating solution, apply and electroplate the essentially identical voltage of time institute's making alive.As another method, known near wafer the placement reference electrode, and the current potential of control wafer is predetermined current potential (for example, with reference to the specification sheets of U.S. Patent No. 6551483 and the specification sheets of U.S. Patent No. 6562204) with respect to reference electrode in wafer immersion plating solution.
But, in the previous case, in the time of in the wafer inclination immersion plating solution it is applied voltage, thereby, thus, has the problem that is difficult to form uniform electroplating film at the different amts that soaks partly and soak after a while formed electroplating film between the part morning.Under latter event, reference electrode is placed near the wafer, thus when electroplating the reference electrode electric interfering field, have the problem that is difficult to form the uniformly-coating film thus.
Summary of the invention
According to an aspect of the present invention, provide a kind of electroplanting device, comprising: the electroplating solution groove of storing electroplating solution; In described electroplating solution groove, fix the fixer that forms the substrate of inculating crystal layer on it; Be placed on the first anode in the described electroplating solution groove, this first anode is made of the Eo+ anode metal higher than the Eo+ of the metal that constitutes inculating crystal layer and is electrically connected on the inculating crystal layer by described fixer fixed substrate; And being placed on second anode in the described electroplating solution groove, this second anode can apply voltage between itself and the inculating crystal layer by fixer fixed substrate.
According to another aspect of the present invention, a kind of electro-plating method is provided, comprise: the first anode is electrically connected to the inculating crystal layer of substrate, and wherein the first anode is placed in the electroplating solution, and is made of the Eo+ anode metal higher than the Eo+ of the metal that constitutes inculating crystal layer; In electroplating solution, soak substrate; And by at inculating crystal layer and be placed on and apply voltage between the second anode in the electroplating solution and electroplate substrate.
According to a further aspect of the invention, provide a kind of manufacture method of semiconducter device, comprising: have from the teeth outwards on the substrate of sunk part and form inculating crystal layer, thereby the part of this sunk part is filled; The first anode is electrically connected to inculating crystal layer, and wherein the first anode is placed in the electroplating solution, and is made of the Eo+ anode metal higher than the Eo+ of the metal that constitutes inculating crystal layer; In electroplating solution, soak the first anode and be electrically connected to the substrate of the inculating crystal layer on it; By at inculating crystal layer and be placed on and apply voltage between the second anode in the electroplating solution and on inculating crystal layer, form electroplating film, thereby fill sunk part; And get rid of the electroplating film outside the electroplating film of in sunk part, filling and the inculating crystal layer of in sunk part, filling outside inculating crystal layer.
Brief description
Fig. 1 is the signal vertical cross section according to the electroplanting device of first embodiment.
Fig. 2 is the signal vertical cross section according to the wafer of first embodiment.
Fig. 3 shows the schema according to the electroplating technology of first embodiment.
Fig. 4 A shows synoptic diagram according to the working order of the electroplanting device of first embodiment to Fig. 4 D.
Fig. 5 A and 5B are the signal vertical cross sections according to the wafer of first embodiment.
Fig. 6 is the signal vertical cross section according to the electroplanting device of second embodiment.
Embodiment
(first embodiment)
Hereinafter, introduce first embodiment.Fig. 1 is the signal vertical cross section according to the electroplanting device of present embodiment, and Fig. 2 is the signal vertical cross section according to the wafer of present embodiment.
As shown in Figure 1, electroplanting device 1 is made of columniform electroplating solution groove 2 grades.Electroplating solution groove 2 is used for storing the electroplating solution that main component is an electrolytic solution, for example, and copper sulfate solution.
The fixer 3 of fixed wafer W (substrate) is placed on the top of electroplating solution groove 2.Fixer 3 is with the ventricumbent mode fixed wafer of what is called W, thereby makes wafer W want galvanized surface down.
In retainer body 3A, hold wafer W with following structure.Wafer W comprises interlayer dielectric 101, as shown in Figure 2.Interlayer dielectric 101 is made of low dielectric constant insulating material, for example, and SiOF, SiOC, porous silica etc.Interlayer dielectric 101 is formed on the semiconducter substrate with semiconductor element (not shown) etc.In interlayer dielectric 101, form as the via hole 101A of sunk part with as the wire laying slot 101B of sunk part.
On interlayer dielectric 101, form and be used for suppressing to constitute the barrier metal layer 102 of the metal diffusing of the electroplating film of introducing later 104 to interlayer dielectric 101.Barrier metal layer 102 is made of electro-conductive material.This electro-conductive material by, for example, metal, for example, Ta, Ti etc., or metal nitride, for example, formations such as TiN, TaN, WN have than the littler spread coefficient of metal that constitutes electroplating film 104. and incidentally, barrier metal layer 102 can be formed by the multilayer material of these metals or metal nitride.
On barrier metal layer 102, form inculating crystal layer 103, be used in wafer W, flowing through electric current.Inculating crystal layer 103 is made of metal, for example Cu.
Be used for respect to the solution surface inclination wafer W of electroplating solution and rotate the inclination of wafer W and rotating mechanism 4 attached on the fixer 3.Tilt and rotating mechanism 4 with respect to the solution surface inclination wafer W of electroplating solution and rotate fixer 3 or the like.
The raising/lowering mechanism (not shown) of lifting/decline wafer W is attached on the fixer 3.Raising/lowering mechanism lifting/decline fixer 3 etc.By starting raising/lowering mechanism, lifting/decline fixer 3 is pulled out thereby wafer W is immersed in the electroplating solution or from electroplating solution.
Substantially be placed on the bottom position of electroplating solution groove 2 for the anode 5 (second anode) of dish type.Contact 3B and anode 5 are electrically connected to power supply 6, are used for applying voltage by contact 3B between inculating crystal layer 103 and anode 5.
What can be electrically connected to inculating crystal layer 103 substantially is placed on outside by wafer W and the 5 folded zones of the anode in electroplating solution groove 2 for the sacrificial anode 7 (first anode) of bar shaped.In the present embodiment, sacrificial anode 7 is placed near the sidewall of electroplating solution groove 2.
Hereinafter, the working order of electroplanting device 1 will be introduced.Fig. 3 shows the schema according to the electroplating technology of present embodiment.Fig. 4 A shows synoptic diagram according to the working order of the electroplanting device 1 of present embodiment to Fig. 4 D, and Fig. 5 A and 5B are the signal vertical cross sections according to the wafer W of present embodiment.
Shown in Fig. 4 A, the inculating crystal layer 103 of wafer W is electrically connected with sacrificial anode 7, and wafer W is by fixer 3 fixing (step 1) simultaneously.Afterwards, start to tilt and the rotating mechanism 4 rotation wafer W and the wafer W (step 2) that tilt.
Then, start that raising/lowering mechanism is soaked wafer W and, (step 3) shown in Fig. 4 B with in the wafer W immersion plating solution.Wafer W is soaked and immersion plating solution in after, disconnect and to be electrically connected (step 4) shown in Fig. 4 C between inculating crystal layer 103 and the sacrificial anode 7.
Afterwards, start power supply 6, thereby between inculating crystal layer 103 and anode 5, apply voltage, shown in Fig. 4 D, wafer electroplating W (step 5) then.Shown in Fig. 5 A, after the electroplating film 104 that forms pre-determined thickness, stop to apply voltage, thereby stop to electroplate (step 6).At last, start raising/lowering mechanism, wafer W is pulled out electroplating solution (step 7).
Incidentally, afterwards wafer W is heat-treated (annealing), thus the crystal growth of inculating crystal layer 103 and electroplating film 104.Thus, form the wiring membrane of inculating crystal layer 103 and electroplating film 104 combinations.Then, shown in Fig. 5 B, remove the barrier metal film 102 on interlayer dielectric 101 and the redundance of wiring membrane respectively by for example chemically machinery polished (CMP), thereby in via hole 101A and wire laying slot 101B, remain with barrier metal film 102 and wiring membrane respectively.Therefore, in via hole 101A and wire laying slot 101B, form wiring 105.
In the present embodiment, since wafer W soaked and immersion plating solution in the time inculating crystal layer 103 be in status of electrically connecting with sacrificial anode 7, so can prevent because the appearance in the cavity that the dissolving of inculating crystal layer causes, and can improve the homogeneity on surface of the film thickness of electroplating film 104.Promptly, when wafer W soak and immersion plating solution in the time wafer W and sacrificial anode 7 when being in status of electrically connecting, because sacrificial anode is made of the Eo+ anode metal higher than the Eo+ of the metal that constitutes inculating crystal layer, so on inculating crystal layer 103 reduction reaction takes place, on sacrificial anode 7 oxidizing reaction takes place.Therefore, the dissolving of inculating crystal layer 103 can be suppressed, thereby the appearance in cavity can be prevented.On the other hand, on inculating crystal layer 103 reduction reaction taking place, thereby electroplates inculating crystal layer 103.But, with soak in wafer W and immersion plating solution in compare applying when electroplating essentially identical voltage condition between inculating crystal layer 103 and the anode 5, can reduce galvanized amount on wafer W.By making sacrificial anode 7 littler, can further reduce galvanized amount with the contact area of electroplating solution.Therefore, prevented when wafer W soak and immersion plating solution in the time on wafer W the ununiformity of galvanized amount, thereby can improve the homogeneity on the surface of the film thickness on electroplating film 104.
In the present embodiment since wafer W is soaked and immersion plating solution in the zone and the zone of placing sacrificial anode 7 be cut off wall 8 separately, be deposited on the wafer W so can prevent dissolved sacrificial anode 7.That is, when wafer W soak and immersion plating solution in, when simultaneously inculating crystal layer 103 was in status of electrically connecting with sacrificial anode 7, according to the constituent material of sacrificial anode 7, it can be dissolved in the electroplating solution.Here, if sacrificial anode 7 dissolvings, the dissolved material may stop wafer electroplating W.In contrast, in the present embodiment, wafer W soak and immersion plating solution in the zone and the zone of placing sacrificial anode 7 be cut off wall 8 separately, therefore, even when sacrificial anode 7 dissolves, also can avoid stoping wafer electroplating W.
In the present embodiment, because being electrically connected between inculating crystal layer 103 and sacrificial anode 7 disconnects wafer electroplating W afterwards, so can improve the homogeneity on the surface of the film thickness on electroplating film 104.That is, when coming wafer electroplating W by apply voltage between inculating crystal layer 103 and anode 5, and when inculating crystal layer 103 was in status of electrically connecting with sacrificial anode 7 simultaneously, electric field distribution may be chaotic.In contrast, in the present embodiment, because being electrically connected between inculating crystal layer 103 and sacrificial anode 7 disconnects wafer electroplating W afterwards, so can avoid the confusion of electric field distribution.Therefore, can improve the homogeneity on the surface of the film thickness on electroplating film 104.
In addition, in the present embodiment, because sacrificial anode 7 is placed on outside wafer W and the anode 5 folded zones, so when wafer electroplating W, electric field distribution does not almost have confusion.Thus, can improve the homogeneity on the surface of the film thickness on electroplating film 104.
(example)
Hereinafter, an example is described.In the present example, observe galvanized occupied state.
In the present example, use the electroplanting device of in above-mentioned first embodiment, introducing. use the electroplating solution of main component as copper sulfate solution, and the sacrificial anode that uses Zn to constitute.In addition, use the wafer of following formation.On the Si substrate, form the thick oxide film of 100nm by thermooxidizing, subsequently, on oxide film, form the thick interlayer dielectric of about 1 μ m by using chemical vapour deposition (CVD) method.In addition, by photoetching process (PEP) be etched on the interlayer dielectric and form the wide and dark wire laying slot of 300nm of 0.09 μ m.Afterwards, by the thickness that uses sputtering method to form on interlayer dielectric to be made of the Ta barrier metal layer as 15nm, and to form the thickness that is made of Cu on barrier metal layer be the inculating crystal layer of 80nm.Incidentally, these film thicknesses are the values that record on the plane of the interlayer dielectric that does not form wire laying slot.
Use above-mentioned electroplanting device and wafer etc. and with the described identical method wafer electroplating of first embodiment, thereby coating is filled into half height of wire laying slot.Observe this moment in the middle of wafer and the occupied state of edge section coating.
Incidentally, as the comparative example 1 of comparing, also observe in the middle of the wafer when in wafer immersion plating solution, between inculating crystal layer and anode, not applying voltage and the occupied state of edge section coating with this example.In addition, as a comparative example 2, in the middle of the wafer when also observing essentially identical voltage when in wafer immersion plating solution, between inculating crystal layer and anode, applying and electroplating and the occupied state of edge section coating.
Introduce observations.Table 1 and table 2 demonstrate the observations according to this example and comparative example 1 and 2.
[table 1]
| This example | Comparative example 1 | Comparative example 2 | |
| Middle | Half fills | Half fills | Half fills |
| The edge | Half fills | Half fills | Full load |
[table 2]
| This example | Comparative example 1 | Comparative example 2 | |
| Middle | There is not the cavity | The cavity is arranged | There is not the cavity |
| The edge | There is not the cavity | The cavity is arranged | The cavity is arranged |
As shown in table 1, coating is filled into half height according to the wire laying slot of the centre of the wafer of comparative example 1 and edge section.But, as shown in table 2, the cavity appears in centre and edge section according to the wafer of comparative example 1.Can expect having produced the cavity owing to the dissolving of inculating crystal layer.
In addition, as shown in table 1, coating is filled into half height according to the wire laying slot of the middle portion of the wafer of comparative example 2, and still, in the edge section of wafer, wire laying slot is filled up by coating.Simultaneously, as shown in table 2, the cavity appears in the edge section according to the wafer of comparative example 2.Can expect that the cavity is not produced by the dissolving with inculating crystal layer, but owing to when wafer immersion plating solution, under suitable filling condition, not electroplate.
In contrast, as shown in table 1, coating is filled into half height according to the wire laying slot of the centre of the wafer of this example and edge section.In addition, as shown in table 2, the cavity does not appear in centre and edge section according to the wafer of this example.
By these results, verified in wafer immersion plating solution, when inculating crystal layer and sacrificial anode are in status of electrically connecting simultaneously, than when more difficult generation of time in the state lower wafer immersion plating solution that does not apply voltage between inculating crystal layer and the sacrificial anode empty, and, can be than in wafer immersion plating solution, the situation when applying voltage simultaneously between inculating crystal layer and sacrificial anode improves the homogeneity on the surface of the film thickness on the electroplating film.
(second embodiment)
Hereinafter, introduce second embodiment.The situation of the sacrificial anode that uses carbon formation is described in the present embodiment.Fig. 6 shows the signal vertical cross section according to the electroplanting device of present embodiment.
Identical with first embodiment, sacrificial anode 7 is placed in the electroplating solution groove 2.The sacrificial anode 7 of present embodiment is made of carbon.Here, under the situation of using the sacrificial anode 7 that is made of carbon, even in wafer W immersion plating solution, when inculating crystal layer 103 was in status of electrically connecting with sacrificial anode 7 simultaneously, sacrificial anode 7 is dissolving hardly also.Therefore, when using the sacrificial anode 7 that constitutes by carbon, can remove partition wall 8, as shown in Figure 6, because dissolved sacrificial anode 7 does not disturb the plating of wafer W.
The content that the present invention is not limited to introduce in the above-described embodiments, and can the appropriate change structure in the scope that does not break away from spirit of the present invention, the arrangement of material, each parts etc.In the above-described embodiments, introduced situation about tilting with respect to anode 5 in the galvanized while wafer W of wafer W, but also can be in wafer electroplating W wafer W basic parallel with anode 5.In addition, in the above-described embodiments,, but can wherein want galvanized wafer W to face up with the supine mode fixed wafer of what is called W with ventricumbent mode fixed wafer W.
Claims (17)
1. electroplanting device comprises:
Store the electroplating solution groove of electroplating solution;
In described electroplating solution groove, fix the fixer that forms the substrate of inculating crystal layer on it;
Be placed on the first anode in the described electroplating solution groove, this first anode is made of the Eo+ anode metal higher than the Eo+ of the metal that constitutes inculating crystal layer, and is electrically connected on the inculating crystal layer by described fixer fixed substrate;
Be placed on the second anode in the described electroplating solution groove, this second anode can apply voltage between itself and the inculating crystal layer by described fixer fixed substrate; And
Be placed on partition wall or barrier film in the described electroplating solution groove, it will be separated with the zone of placing the described first anode by the zone of described fixer fixed substrate immersion plating solution.
2. according to the electroplanting device of claim 1, the wherein said first anode is made of metal, metal oxide or carbon.
3. according to the electroplanting device of claim 2, wherein inculating crystal layer is made of Cu, and the described first anode is made of Zn, Ta, their oxide compound or C.
4. according to the electroplanting device of claim 1, the wherein said first anode is placed on by described fixer fixed substrate and the folded region exterior of described second anode.
5. according to the electroplanting device of claim 1, wherein make the contact area of the contact area of the described first anode of formation and electroplating solution less than substrate and electroplating solution.
6. electro-plating method comprises:
The first anode is electrically connected to the inculating crystal layer of substrate,
Wherein the first anode is placed in the electroplating solution, and is made of the Eo+ anode metal higher than the Eo+ of the metal that constitutes inculating crystal layer;
In electroplating solution, soak substrate, separate with partition wall or the barrier film zone that will in electroplating solution, soak substrate and the zone of placing the first anode simultaneously; And
By at inculating crystal layer and be placed on and apply voltage between the second anode in the electroplating solution and electroplate substrate.
7. according to the electro-plating method of claim 6, also comprise:
The step that is electrically connected between the disconnection first anode of carrying out between the step of described step of in electroplating solution, soaking substrate and described plating substrate and inculating crystal layer.
8. according to the electro-plating method of claim 6, wherein the first anode is made of metal, metal oxide or carbon.
9. electro-plating method according to Claim 8, wherein inculating crystal layer is made of Cu, and the first anode is made of Zn, Ta, their oxide compound or C.
10. according to the electro-plating method of claim 6, wherein the first anode is placed on substrate and the folded region exterior of second anode.
11. according to the electro-plating method of claim 6, wherein the contact area of the first anode and electroplating solution is less than the contact area of substrate and electroplating solution.
12. the manufacture method of a semiconducter device comprises:
Have from the teeth outwards on the substrate of sunk part and form inculating crystal layer, thereby the part of this sunk part is filled;
The first anode is electrically connected to inculating crystal layer, and wherein the first anode is placed in the electroplating solution, and is made of the Eo+ anode metal higher than the Eo+ of the metal that constitutes inculating crystal layer;
Soak the first anode on it and be electrically connected to the substrate of inculating crystal layer in electroplating solution, the zone that will soak substrate with partition wall or barrier film in electroplating solution separates with the zone of placing the first anode simultaneously;
By at inculating crystal layer and be placed on and apply voltage between the second anode in the electroplating solution and on inculating crystal layer, form electroplating film, thereby fill sunk part; And
Get rid of the electroplating film outside the electroplating film of in sunk part, filling, and get rid of the inculating crystal layer outside the inculating crystal layer of in sunk part, filling.
13. the manufacture method according to claim 12 also comprises:
The step that is electrically connected between the disconnection first anode of carrying out between the step of described step of in electroplating solution, soaking substrate and described formation electroplating film and inculating crystal layer.
14. according to the manufacture method of claim 12, wherein the first anode is made of metal, metal oxide or carbon.
15. according to the manufacture method of claim 14, wherein inculating crystal layer is made of Cu, the first anode is made of Zn, Ta, their oxide compound or C.
16. according to the manufacture method of claim 12, wherein the first anode is placed on substrate and the folded region exterior of second anode.
17. according to the manufacture method of claim 12, wherein the contact area of the first anode and electroplating solution is less than the contact area of substrate and electroplating solution.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP401773/2003 | 2003-12-01 | ||
| JP2003401773A JP2005163080A (en) | 2003-12-01 | 2003-12-01 | Plating apparatus and plating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1624208A CN1624208A (en) | 2005-06-08 |
| CN100342062C true CN100342062C (en) | 2007-10-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100965542A Expired - Fee Related CN100342062C (en) | 2003-12-01 | 2004-11-30 | Electroplate device, electroplate method and method for manufacturing semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20050145500A1 (en) |
| JP (1) | JP2005163080A (en) |
| CN (1) | CN100342062C (en) |
| TW (1) | TWI250552B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060237319A1 (en) * | 2005-04-22 | 2006-10-26 | Akira Furuya | Planting process and manufacturing process for semiconductor device thereby, and plating apparatus |
| JP4762702B2 (en) * | 2005-12-08 | 2011-08-31 | 富士フイルム株式会社 | Plating thickness monitor device and plating stop device |
| JP4816052B2 (en) * | 2005-12-13 | 2011-11-16 | 東京エレクトロン株式会社 | Semiconductor manufacturing apparatus and semiconductor device manufacturing method |
| US8101052B2 (en) * | 2006-11-27 | 2012-01-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Adjustable anode assembly for a substrate wet processing apparatus |
| WO2022137339A1 (en) | 2020-12-22 | 2022-06-30 | 株式会社荏原製作所 | Plating device, pre-wetting treatment method, and cleaning treatment method |
| JP7194305B1 (en) * | 2022-07-01 | 2022-12-21 | 株式会社荏原製作所 | Substrate holder, plating equipment, and plating method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1229274A (en) * | 1998-02-20 | 1999-09-22 | 日本电气株式会社 | Method of manufacturing semiconductor device |
| JP2002097595A (en) * | 2000-09-25 | 2002-04-02 | Hitachi Ltd | Method for manufacturing semiconductor device |
| US6413390B1 (en) * | 2000-10-02 | 2002-07-02 | Advanced Micro Devices, Inc. | Plating system with remote secondary anode for semiconductor manufacturing |
| JP2003268591A (en) * | 2002-03-12 | 2003-09-25 | Ebara Corp | Method and apparatus for electrolytic treatment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6562204B1 (en) * | 2000-02-29 | 2003-05-13 | Novellus Systems, Inc. | Apparatus for potential controlled electroplating of fine patterns on semiconductor wafers |
| US6527920B1 (en) * | 2000-05-10 | 2003-03-04 | Novellus Systems, Inc. | Copper electroplating apparatus |
| US6425991B1 (en) * | 2000-10-02 | 2002-07-30 | Advanced Micro Devices, Inc. | Plating system with secondary ring anode for a semiconductor wafer |
-
2003
- 2003-12-01 JP JP2003401773A patent/JP2005163080A/en active Pending
-
2004
- 2004-11-25 TW TW093136334A patent/TWI250552B/en not_active IP Right Cessation
- 2004-11-30 CN CNB2004100965542A patent/CN100342062C/en not_active Expired - Fee Related
- 2004-11-30 US US10/998,970 patent/US20050145500A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1229274A (en) * | 1998-02-20 | 1999-09-22 | 日本电气株式会社 | Method of manufacturing semiconductor device |
| JP2002097595A (en) * | 2000-09-25 | 2002-04-02 | Hitachi Ltd | Method for manufacturing semiconductor device |
| US6413390B1 (en) * | 2000-10-02 | 2002-07-02 | Advanced Micro Devices, Inc. | Plating system with remote secondary anode for semiconductor manufacturing |
| JP2003268591A (en) * | 2002-03-12 | 2003-09-25 | Ebara Corp | Method and apparatus for electrolytic treatment |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200529286A (en) | 2005-09-01 |
| TWI250552B (en) | 2006-03-01 |
| US20050145500A1 (en) | 2005-07-07 |
| JP2005163080A (en) | 2005-06-23 |
| CN1624208A (en) | 2005-06-08 |
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