TW201229328A - Electroplating method - Google Patents

Electroplating method Download PDF

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TW201229328A
TW201229328A TW100145238A TW100145238A TW201229328A TW 201229328 A TW201229328 A TW 201229328A TW 100145238 A TW100145238 A TW 100145238A TW 100145238 A TW100145238 A TW 100145238A TW 201229328 A TW201229328 A TW 201229328A
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Taiwan
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substrate
plating
anode electrode
via hole
metal
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TW100145238A
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Chinese (zh)
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TWI541388B (en
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Mizuki Nagai
Yusuke Tamari
Shingo Yasuda
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Ebara Corp
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C25D21/12—Process control or regulation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/08—Electroplating with moving electrolyte e.g. jet electroplating

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Organic Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Automation & Control Theory (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

An electroplating method includes: preparing a substrate having via holes formed in a surface; immersing the substrate in a pretreatment solution to carry out pretreatment of the substrate; immersing the substrate in a plating solution without applying a voltage between the substrate and an anode, thereby replacing the pretreatment solution in the via holes with the plating solution; carrying out first-step electroplating of the substrate while controlling the voltage, applied between the substrate and the anode, to be equal to or higher than a voltage which is necessary for an electric current, appropriate to fill a plated metal into the via holes, to flow stably between the substrate and the anode; and carrying out second-step electroplating of the substrate while controlling the electric current, flowing between the substrate and the anode, at an electric current appropriate to fill the plated metal into the via holes.

Description

201229328 六、發明說明： 【發明所屬之技術領域】 本發明係關於電鍵方法，且更具體而言，係關於可用 於在基板（如半導體基板或類似基板）製造中將金屬（如銅） 填充進入介層通孔（via hole)的電鍍方法，該基板具有一 些垂直貫穿其内部之穿孔（介層栓塞），且該等穿孔可用於 所s胃的半導體晶片三維封裝。 【先前技術】 形成垂直貫穿半導體基板的金屬穿孔（如鋼）之技術 係習知用以電性半導體基板的多層堆疊的多個層的方法。 第1A圖至第1C圖係描繪在製程步驟序列中用於產生具有 垂直貫穿該基板的銅穿孔之製程。首先，如第1A圖所示， 藉由在基底（base)10(如矽晶圓）中形成複數個向上開口的 介層通孔（viahole)12(例如：利用微影/蝕刻技術）而形成 基板W，且在那之後於該基底10的整體表面（包含該介層 通孔12的内部表面）上形成（例如：藉由PVD)形成金屬阻 障層14(如鈦），並且接著在該阻障層14的表面上形成銅 晶種層（copper seed layer)16。該介層通孔12的直徑“d” 係例如2至50微米（尤其是10至20微米），且該介層通孔 U的深度“h”係例如20至150微米。 除了鈦以外，其他金屬（如组（"tantalum)與鎮 (tungsten)或上述兩者的氮化物）亦可用於作為該阻障層 14。此實施方式證實於以下說明書内容。 接下來，利用該銅晶種層16作為陰極電極（cathode) 4 323759 201229328 在該基板w的表面上實施銅電鍍，藉此將電鍍金屬（銅）18 填充進入該等介層通孔12並且將該電鍍金屬18沉積於該 銅晶種層16的表面上，如第圖所示。 在那之後，如第1C圖所示，例如藉由化學機械研磨 (CMP)移除多餘的銅晶種層16與多餘的電鍵金屬Μ。再 者，該基底10的背表面側係經研磨（例如：到達第1(：圖的 雙點鏈線所示位置），藉此曝露出嵌入該介層通孔12中的 電鍍金屬18的底面。該基板w(其中具有垂直貫穿該基板w 的銅（電鍍金屬18)穿孔）可以此方式產生。 該專介層通孔12的深寬比（aspect ratio )(亦即， 深度對直徑的比值）通常很高。此外，該介層通孔12 —般 而言具有很深的深度。為了藉由電鍍將銅（電鍍金屬）完全 填充進入此類具有深高深寬比的介層通孔12且不致產生 如位於經嵌入的電鍍金屬中的空洞之缺陷，通常必須以自 底部往上（bottom-up)的方式實施電鍍，使得墊鍍金屬較佳 地生長自該等介層通孔的底部。此類自底部往上的電鑛一 般而言係利用含有各種添加物（如作為電鍍加速劑的 SPS(一（ 3-¾酸）二硫化物）、作為抑制劑（SUppress〇r) 的PEG(聚乙二醇（p〇iyethylene glycol))、以及作為均勻 幻（level er)的 PEI(聚乙烯亞胺（p〇iyethyi eneimine))) 的電鑛溶液。基板的表面在吸收這些添加物之後，這些添 加物的效果便發揮出來。 藉由PVD所形成的薄膜的步階覆蓋率（以印coverage) 一般而言相當低。然而，為了藉由PVD在該阻障層14的表 5 323759 201229328 面上形成連續的銅晶種層16 ’必須形成具有相當厚度的銅 晶種層16，例如大約8〇〇奈米至1〇〇〇奈米。因此，也就 是說’需要形成較薄的晶種層。 在這方面，日本專利特開平編號2007-247062描述一 種方法，該方法包括藉由在鈦或類似材料的阻障層14的表 面上的共形CVD形成釕（ruthenium)的輔助金屬層（晶種 層）20(例如：藉由濺鍍於基板w的整體表面上，如第2圖 所不包含介層通孔12的内部表面）以及利用該輔助金屬層 2〇作為陰極電極實施銅電鍍以將該電鍍金屬（銅）填充進 入該介層通孔12。日本專利特開平編號2〇〇8_244298提出 額外在釕的辅助金屬層2G的表面上形成銅晶種層22，如 第3圖所示。第3圖描繚藉由共同pvD所形成且厚度為大 約100奈米至300奈米的銅晶種層22。 申請人已提供-種钱方法’該f鍍方法包括藉由在 晶種層與陽極電極之間通過電流密度4至Μ安培施2的直 流電流持續達G.1至5秒形成初始電鍍薄膜，並且接著藉 由在1晶種層與該陽極電極之間通過電流密度〇 5至5安 培/dm2的直流電流形成次要電鍛薄膜（見曰本專利編 3641372)。 申睛人也已提出在介層通孔填充钱（via_fi山呢 eleCt_ating)中施加步階電壓（電壓隨時間以步階形式 變化）於基板與陽極電極之間（見日本專利特開平編號 2005 97732)。該申請人也已提出—種電财法，關於藉由 維持該基板表面與電鑛溶液接觸達預料間而將電鑛溶液 323759 6 201229328 中的添加物吸收至基板的表面釕薄膜，且隨後實施該基板 表面的電鍍，以在該釕薄膜的表面上形成電鍍薄膜（見曰本 專利特開平編號2009-30167)。此外，日本專利編號 3780302提出一種電鍍方法，包括首先以陰極電極電流密 度5至10安培/dm2實施電鍍達10秒至5分鐘，且隨後以 陰極電極電流密度0. 5至3安培/dm2實施電鍍達15分鐘至 180分鐘。 【發明内容】 藉由電鍍所形成的電鍍金屬（電鍍薄膜）的厚度與電 鍍期間的電流密度成比例。因此，當藉由電鍍將電鍍金屬 填充進入介層通孔時，通常實際上控制電流，使得適於將 金屬填充進入該等介層通孔的電流流過陽極電極與覆蓋該 等介層通孔的晶種層之間。再者，一般而言，如上所述含 有各種添加物的電鍍溶液係用於此類介層通孔填充電鍍。 儘管使用含有添加物的電鍍溶液，但是仍然難以將電 鍍金屬（如銅）牢牢地填充進入深高深寬比的介層通孔 12(如第2圖所示覆蓋有釕的輔助金屬層（晶種層）20)而不 致產生缺陷（如位於經嵌入的電鍍金屬中的空洞）。對於覆 蓋有銅晶種層的介層通孔而言，可藉由以預定電流密度實 施電鍍而將電鍍金屬填充進入該等介層通孔且不致形成空 洞。另一方面，當實施電鍍以將電鍍金屬（銅）填充進入覆 蓋有釕的輔助金屬層之介層通孔時，可能在位於經嵌入的 電鍍金屬中形成空洞。 當例如藉由共同PVD在釕的輔助金屬層（晶種層）20的 7 323759 201229328 表面上形成厚度大約100奈米至300奈米的銅晶種層22 時’該銅晶種層22無法形成覆蓋該輔助金屬層20的整體 表面，且該釕的輔助金屬層2〇將曝露於介層通孔12的底 部，如第3圖所示。當利用該辅助金屬層2〇與該銅晶種層 22作為陰極電極實施此類基板的介層填充電鑛以將電鐘 金屬填充進入該等介層通孔12時’將在經嵌入該介層通孔 12中的電鍍金屬中形成空洞。這是因為該輔助金屬層2〇 的片電阻（sheet resistance)高於該銅晶種層22的片電 阻’且s亥電鑛金屬將不均勻地沉積於該輔助金屬層2〇的表 面上。 本發明係有鑑於上述情況所提出。因此，本發明的目 的在於提供一種電鍍方法，能夠將電鍍金屬（如銅）牢牢地 填充進入介層通孔，即便當該等介層通孔覆蓋有例如釕（具 有較銅晶種層稍差的導電性）的輔助金屬層時或者當例如 訂的辅助金屬層部份曝露於介層通孔中時，亦不致在經嵌 入的電鐘金屬中產生缺陷（如空洞）。 為了達到上述目的，本發明提供一種電鍍方法，包 括··製備基板，該基板的表面中形成有介層通孔；將該基 板浸潰於預處理溶液中，以實施該基板的預處理；將該基 板浸潰於電鍍雜巾’且未施加t壓㈣餘與陽極電^ 之間，該陽極電極係配置於該基板的對面，藉此以該電鍍 溶液取代該介層通孔中的該預處理溶液；實施該基板的^ 一步驟電鍍，同時，將施加於該基板與該陽極電極之該電 壓控制為等於或高於-電壓，該電黯得適於將電錢金屬 323759 8 201229328 填充進入該介層通孔之電流穩定地流動於該基板與該陽極 電極之間；以及實施該基板的第二步驟電鑛，同時，將流 動於該基板與該陽極電極之間的該電流控制在適於將該電 鍍金屬填充進入該介層通孔。 當實施該第一步驟電錄時，同時控制該電壓為等於或 高於適合將電鍍金屬填充進入該介層通孔之電流穩定地流 動於该基板與該陽極電極之間所需的電壓值，流動於該基 板與該陽極電極之間的電流在電鍍的初始階段暫時較高。 因此，將抑制電鍍的添加物優先吸收至例如釕的辅助金屬 層開始生長有電鍍薄膜的部份表面上。如此可有助於該輔 助金屬層尚未開始生長電鍍薄膜的部份表面上的電鍍薄膜 生長，能夠於該辅助金屬層的表面上均勻地沉積該電鍍金 屬。在開始於該辅助金屬層的表面上均勻地沉積電鍍金屬 之後，適合將該電鍍金屬填充進入該介層通孔的電流穩定 地流動於該基板與該陽極電極之間。接著，實施該第二步 驟電鍍，同時將電流控制為適合將電鍍金屬填充進入該介 層通孔之電流。該第二步驟電鑛係實施於受控制的電流 下，持續達沉積所欲電鍍量所必須的時間。此電鍍方法容 許該電鍍金屬（如銅）可優先沉積於該介層通孔的底部，亦 即，以自底部往上的方式實施，使得該電鍍金屬得以填充 進入该介層通孔，而不致在嵌入該介層通孔中的電鍍金屬 中產生缺陷（如空洞）。 該基板宜浸潰於該電鍍溶液中持續達1〇秒至6〇秒， 而不施加電壓於該基板與該陽極電極之間。倘若基板（例 323759 9 201229328 二具有覆蓋介層通孔的銅晶種層)浸潰於電鍍溶液中持續 太久，且未施加電壓於該基板與該陽極電極之間，則該銅 晶種層將收到該電鍍溶液的傷害。因此，當該基板具有小 尺寸的介層通孔（例如：1〇微米至5〇微米）時，該读 潰於電嫂溶液中且未施加電壓於該基板與該 的^較㈣情況是大約1Q秒至2Q秒，當該基板具有^ 尺寸的介層通孔（例如：抖丰〜 2〇秒至60秒。 _時，較佳的情況是大約 該第-步驟電鍍可持續實施例如達i秒至1〇分鐘。 精由實施該第-步驟電錢持續達如此時 鍍金屬可均勾地沉積於例如釕的輔助金屬層的表面上1 能夠穩定流動於該基板與崎極電極之間的電流。 之門㈣職心流㈣該基板與該陽極電極 之間的電流係以步階形式變化之方式實施。 电不 :該電鍍金屬隨著電鑛程序而逐漸沉積於 孔中時，各個介層通孔的未填充部份的深寬比逐漸變化2 =該深寬比越低，則越容易於高電流下以自㈣往上的 =穩疋生長電鐘_的方式實施通孔填充電鍍。 板與該陽極電極之間的 電飢來&㈣電鍍時間^增進產能，以 進入該等介層通孔_度變化，h 〃电㈣屬填充 填充部份的深寬比變化。亦即’各個介層通孔的未 在本發_較佳態樣中，該電鍍金屬_， 屬係曝露於該介層通孔的至少部份表面上。該非銅金屬係 323759 10 201229328 例如釕或始，或上述各者的合金。 該電鍍金屬（如銅）可填充進入該介層通孔，且釕、鈷 或其合金曝露於該介層通孔的至少部份表面上，*不致產 生如位於經嵌入的電鍍金屬中的空洞之缺陷。 本發明使得電鍍金屬（如銅）能夠牢牢地填充進入深 高深寬比的介層通孔，即便當料介層軌覆蓋有例如釘 (具有較銅晶種層稍差的導電性）的輔助金屬層時或者當例 如釕的辅助金屬層部份曝露於介層通孔中時，亦不致在經 叙入的電鑛金屬中產生如空洞之缺陷。 【實施方式】 現在將參考圖式描述本發明的較佳實施例。以下說明 書内容描述例示情形，其中’實施基板表面的銅電鍍，以 將銅（電鍵金屬）填充進入設置於該基板表面中的介層通 孔’藉此在該基板中形成銅的穿孔。 第4圖係用於實施本發明的電鍍方法的電鍍設備之總 體佈局平面圖。此電鍍設備經過設計，以便自動地以連續 的方式實施所有電鑛製程’包含基板的預處理、電鍍、以 及5亥電錢的後續處理。附接有裝甲平板（armored panel) 的設施框架（apparatus frame)l 10的内部係由分隔板112 分割成為電鍍空間116以及清潔空間114,該電鍍空間116 係用於實施基板之電鍍製程以及沾附有電鍍溶液的基板之 處理’該清潔空間114係用於實施其他製程（亦即，與電鐘 溶液並未直接相關之製程）。兩個基板支架160(見第5圖） 平行配置’且於由分隔板112(該分隔板112將電鍍空間116 11 323759 201229328 與該清潔空間114分開）所分隔的分隔部份上設置有作為 基板傳送段（substrate delivery section)之基板附接/ 分離級（substrate attachment/detachment stage)162， 用以將基板附接至各個基板支架160以及將基板分離自各 個基板支架160。負載/卸載部份丨2〇(有基板卡匣儲存基板 (substrate cassette storing substrate)接置於其上） 係連接至該清潔空間114。再者，該設施框架no具有主 控面板（console panel)121設置於其上。 在該清潔空間114中’裝設有對準器（a 1 igner) 122以 及兩個清潔/烘乾裝置124,該對準器122用於在預定方向 上對準基板的定向平面（〇rientati〇n f lat)或凹處 (notch)，該清潔/烘乾裝置124係用於清潔電鍍基板並且 而逮$疋轉S亥基板以甩乾該基板。此外，第一搬運機器手臂 128實質上係裝設於這些製程裝置（亦即，該對準器122與 該π潔/烘乾裝置124)的中央，藉此在該製程裝置122、 124、該基板附接/分離級162、以及接置於負載/卸載部份 UO上的基板卡匡之間搬運與傳送基板。 裴設於該清潔空間114中的對準器122與清潔/烘乾 裝置124係經過設計，以便以水平狀態支撐與處理基板， 其中’該基板的前面朝上。 在該電鍍空間116中，自該分隔板112開始依序裝設 有儲存器164、預處理裝置126、激活處理裝置166、第一 水清潔裝置168a、電鍍設施170、第二水清潔裝置16牝、 以及吹氣裝置172,其中，該儲存器164係用於儲存或暫 323759 12 201229328 時儲存該基板支架16 0 ’该預處理裝置12 6係用於實施預 處理（預濕處理）’利用預處理液體（如純水（DIW)或類似液 體）清潔該基板表面’並藉由預處理液體沾濕該基板表面來 增強其親水性，該激活處理裝置166係用於利用無機酸溶 液（如硫酸或鹽酸）或有機酸溶液（如擰檬酸或草酸）飯刻例 如形成於該基板表面上的晶種層上的氧化物薄膜（具有高 電阻值），以移除該氧化物薄膜’該第一水清潔裝置168a 係用於以純水清潔該基板表面’該電錢設施170係用於實 施電鍍，該吹氣裝置Π2係用於將該經電鍍的基板脫水。 兩個第二搬運機器手臂174a、174b係裝設於這些裝置旁， 以便可沿著執道176移動。其中一個第二搬運機器手臂 174a在該基板附接/分離級162與該儲存器164之間搬運 該基板支架160。另一個第二搬運機器手臂174b在儲存器 164、預處理裝置126、激活處理裝置166、第一水清潔裝 置168a、電鍍設施Π0、第二水清潔裝置168b、以及吹氣 裝置172之間搬運該基板支架160。 如第5圖所示，各該第二搬運機器手臂174a、174b 皆具有垂直延伸的本體178，以及可沿著該本體178垂直 移動且可繞著該本體178的軸心旋轉的手臂18〇。該手臂 180具有平行設置的兩個基板支架握持部份（substrate holder retaining portion)182，用於可分離地握持該基 板支架160。該基板支架160經過設計，以便在曝露出基 板的前面同時密封該基板的周圍部份的狀態下支撐基板 W，並且能夠將該基板W附接至該基板支架160以及將該基 323759 13 201229328 板W自該基板支架160分離。 儲存器164、預處理裝置126、激活處理裝置166、水 清潔裝置168a、168b、以及電鍍設施170係經設計，以便 與設置於各基板支架160兩端的向外突出部份（outwardly projecting p〇rtion)160a相接合，因而支撐該基板支架 160 ’使得該基板支架160懸掛於垂直方向上。該預處理裝 置129具有兩個預處理槽（pretreatment tank)127，用於 將預處理液體（如溶氧濃度小於例如2毫克/公升的純水 (除氧DIW)或類似液體）容置於其中。如第5圖所示，降低 該第二搬運機器手臂174b用於以垂直狀態支撐該基板支 架160(負載有該基板ψ)的手臂180，以便接合該預處理槽 127的上侧端’以懸掛的方式支撐該基板支架16〇。因此， 該預處理裝置126係經設計，使得該基板支架160與該基 板评一起浸潰於該預處理槽127中的預處理液體中，以實 施預處理（預濕處理（pre_wetting treatment))。該激活處 理裝置166具有兩個激活處理槽ι83，用於將化學液體容 置於其中。如第5圖所示，降低該第二搬運機器手臂 用於以垂直狀態支撐該基板支架160(負載有該基板W)的 手臂180 ’以便接合該激活處理槽183的上侧端，以懸掛 的方式支撐該基板支架160。因此，該激活處理裝置166 係經設計，使得該基板支架16〇與該基板w 一起浸潰於該 激活處理槽183中的化學液體中，以實施激活處理。當不 需要激活處理時，可省略該激活處理槽183。 同樣地，該水清潔裝置168a、168b具有分別容置有 14 323759 201229328 純水的兩個水清潔槽184a與兩個水清潔槽i84b，且該電 鍍設施170具有容置有電鍍溶液於其中的複數個電鍍槽 186。該水清潔裝置168a、168b與該電鍍設施170係經設 計，使得該基板支架160與該基板w 一起浸潰於該水清潔 槽184a、184b中的純水中或者該電鍍槽丨86中的電鍍溶液 中，以相同於上述的方式實施水清潔或電鍍。降低該第二 搬運機器手臂174b用於以垂直狀態支撐該基板支架 160(負載有該基板W)的手臂18〇，且向接置於該基板支架 160上的基板W喷射空氣或惰性氣體，以吹走附接於該基 板支架160與該基板W的液體，以脫水該基板w。因此， δ玄吹氣裝置172係經设計，以便實施吹氣處理（b 1 〇w i ng treatment) ° 如第6圖所示，設置於該電鍍設施i7〇中的各個電鑛 槽186係經設計，以便於其中容置有預定數量的電鍍溶液 Q。遠基板W(其係維持在曝露出前面（欲電錢表面）同時由 該基板支架160防水密封周圍部份的狀態下）係於垂直方 向上次 >貝於該電鑛槽18 6中的電鑛溶液Q中。在此實施例 中’作為該電鍍溶液Q的電鍍溶液（除了銅離子、支援電解 質（supporting electrolyte)以及齒素離子以外）含有各 種添加物（如作為電鍍加速劑的SPS(二（3~續奶>)_ 物）、作為抑制劑的PEG(聚乙二醇）、以及作為均 PEI(聚乙烯亞胺））。較佳的情況是’採用硫酸作為支援的 解質，且氯離子宜作為鹵素離子》 電 溢流槽（overf low)200係設置於該電鍍槽的 ， 323759 15 201229328 端周圍，用於容納溢流出該電鍍槽186邊緣的電鍍溶液Q。 循環管路（circulation pi ping) 204設置有栗202的一端 係連接至該溢流槽200的底部，該循環管路204的另一端 係連接至設置於該電鍍槽186底部的電鍍溶液供應入口 (supply inlet)186a。因此，該溢流槽200中的電鍵溶液 Q藉由該泵202的驅動而回到該電鍍槽186中。於該泵202 的下游，定溫單元206與過濾器208插入該循環管路204 中，該定溫單元206係用於控制該電鍍溶液Q的溫度，該 過濾器208係用於過濾出該電鐘溶液中所含有的異物 (foreign matter) ° 底板210(其中具有大量的電鍵溶液通道孔（passage hole))係安裝於該電鍍槽186的底部。因此，該底板210 將該電鍍槽186的内部分割成為上侧基板處理室214以及 下側電鍍溶液分配室212。此外，防護板216(其向下垂直 延伸）係接置於該底板210的下侧表面。 根據此電鍍設施170，藉由該泵202的驅動將該電鍍 溶液Q引進該電鍍槽186的電鍍溶液分配室212，通過設 置於該底板210中的電鍍溶液通道孔流進該基板處理室 214’大約平行於由該基板支架ι6〇所握持的基板w的表面 而垂直地流動，並接著流進該溢流槽2〇〇。 具有對應於該基板W的形狀之圓形陽極電極220係由 陽極電極支架222所握持且垂直地設置於該電鍍槽186 中。當S玄電鑛溶液Q填充於該電鍍槽186中時，由該陽極 電極支架222所握持的陽極電極220變得浸潰於該電鍍槽 16 323759 201229328 186中的電鍍溶液Q中’且面對由該基板支架i6〇所握持 的基板W，並且裝設於該電鍍槽186中。 此外，在該電鐘槽186中，調節板（regUiati〇n plate)224係裝設於該陽極電極220與欲裝設於該電鍍槽 186中預定位置的基板W之間，用於調節該電鍍槽186中 的電位（electrical potential)。在此實施例中，該調節 板224係由圓柱部伤226與矩形邊圈部份（rectangular flange portion)228所組成’且係由介電材料-聚氯乙烯 所製成。該圓柱部份226具有如此開口尺寸與軸長度，足 夠限制電場的擴大。該調節板224的邊圈部份228的下侧 端到達該底板210。 在該陽極電極220與欲裝設於該電鍵槽186中預定位 置的基板W之間，裝設有垂直延伸作為攪拌工具的授拌槳 232 ’其平行於該基板W的表面往復運動，以攪拌該基板w 與該調節板224之間的電鑛溶液Q。藉由在電鍍期間利用 5玄擾掉槳（攪:摔工具）232攢;掉該電鍛溶液Q，可將足量的銅 離子均勻地供應至該基板W的表面。 如第7圖及第8圖所示’該攪拌槳232係由類似矩形 板的組件所組成’該組件具有3毫米至5毫来的均勻厚度 “t” ’且具有定義垂直延伸的類似帶狀部份232b的複數個 平行狹缝（slit)232a。該攪拌槳232係由例如樹脂（如 PVC、PP與PTFE、以及SUS或具有鐵弗龍（Tefion)塗層的 鈦）所形成。較佳的情況是’接觸該電鑛溶液的至少部份授 拌槳232係電性隔離的。該攪拌槳232的垂直長度L與該 323759 17 201229328 狹縫232a的垂直長度L2係充分大於該基板w的垂直尺寸。 再者，該攪拌槳232係經設計，使得其側向長度H及其往 復運動距離（往復運動衝程（str〇ke))的總和充分大於該基 板W的側向尺寸。 較佳的情況是，決定該狹縫232a的寬度與數量，當 該等狹縫2 3 2 a之間的帶狀部份2 3 2 b具有能夠有效着電 鍍溶液所必須關性且（此外）料鍍溶液能夠有效地通過 該等狹縫232a時，使得各個帶狀部份23肋盡可能較窄。 該電鍍設施170設置有電錢電源250，於電鍍期間， 該電鑛電源250的正極經由導線連接至該陽極電極22〇， 而該電鍍電源250的負極經由導線連接至該基板w的表 面。該電鍍電源250係連接至控制段（c〇ntr〇1 seCti〇n)252’且基於來自該控制段252的信號控制該電鍍 設施170。 現在將描述第4圖所示電鍍設備中所實施用以將銅 (電鏟金屬）填充進入第3圖所示基板w的介層通孔12的電 鍍操作的序列。該基板W已經由以下製程所製造，包括在 基底10(如石夕晶圓）中形成向上開口的介層通孔丨2、在該基 板的整體表面上形成鈦或類似材料的阻障層、在該阻障 層14的表面上形成釕的輔助金屬層2〇、以及藉由卩仰在 該輔助金屬層20的表面上形成厚度大約1〇〇奈米至3〇〇 奈米的銅晶種層22。一般而言’由pvD所形成的薄膜的步 階覆蓋率很低。因此，當厚度大約丨〇〇奈米至3〇〇奈米的 銅bb種層22係由PVD所形成時’該銅晶種層22無法到達 323759 201229328 該介層通孔12的底部，且釕的輔助金屬層2〇係曝露於該 介層通孔12中。 首先’該基板W係以前表面（欲電錢表面）朝上的方式 放置於基板卡匣中，且該基板卡匣係接置於該負載/卸載部 份120上❶藉由該第一搬運機器手臂128將其中一個基板 W自接置於該負載/卸載部份丨2〇上的基板卡匣取出，並且 放置於該對準器122上，以於預定方向上對準該基板w的 定向平面或凹處。另一方面，藉由第二搬運機器手臂174a 將兩個基板支架16〇(其係以垂直狀態儲存於該儲存器164 中）取出，旋轉達90度，使得該基板支架16〇成為水平狀 態’並且接著平行放置於該基板附接/分離級162上。 於預定方向上對準該基板W的定向平面或凹處的基板 W係經搬運並以該基板的周圍部份經密封的狀態負载於放 置在該基板附接/分離級162上的基板支架16〇中。藉由該 第二搬運機器手臂174a將該兩個基板支架16〇同時握持、 舉起並搬運至該儲存器164。將該基板160旋轉達9〇度成 為垂直狀‘4並且降低，使得該兩個基板支架16Q以懸掛的 方式保持在（暫時儲存在）該儲存器164中。上述操^以201229328 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of electrical bonding, and more particularly to a metal (such as copper) that can be used to fill a substrate (such as a semiconductor substrate or the like). A method of electroplating a via hole having a plurality of vias (via plugs) extending vertically through the interior thereof, and the vias are used for three-dimensional packaging of a semiconductor wafer of the stomach. [Prior Art] A technique of forming a metal via (e.g., steel) perpendicularly penetrating a semiconductor substrate is a conventional method of using a plurality of layers of a multilayer stack of an electrical semiconductor substrate. 1A through 1C depict processes for producing copper vias having vertical through the substrate in a sequence of process steps. First, as shown in FIG. 1A, a plurality of open via vias 12 are formed in a substrate 10 (eg, a germanium wafer) (eg, using lithography/etching techniques). a substrate W, and thereafter formed on the entire surface of the substrate 10 (including the inner surface of the via hole 12) (for example, by PVD) to form a metal barrier layer 14 (such as titanium), and then A copper seed layer 16 is formed on the surface of the barrier layer 14. The diameter "d" of the via hole 12 is, for example, 2 to 50 μm (especially 10 to 20 μm), and the depth "h" of the via hole U is, for example, 20 to 150 μm. In addition to titanium, other metals such as a group ("tantalum) and a town (tungsten) or both of them may be used as the barrier layer 14. This embodiment is confirmed by the following description. Next, copper plating is performed on the surface of the substrate w by using the copper seed layer 16 as a cathode electrode 4 323759 201229328, thereby filling the plating metal (copper) 18 into the via holes 12 and The plated metal 18 is deposited on the surface of the copper seed layer 16, as shown in the figure. After that, as shown in Fig. 1C, the excess copper seed layer 16 and the excess key metal ruthenium are removed, for example, by chemical mechanical polishing (CMP). Furthermore, the back surface side of the substrate 10 is ground (for example, to reach the position indicated by the first dot (the double-dot chain line of the figure), thereby exposing the bottom surface of the plated metal 18 embedded in the via hole 12 The substrate w (with copper (electroplated metal 18) perforations extending perpendicularly through the substrate w) can be produced in this manner. The aspect ratio of the via layer 12 (i.e., depth to diameter ratio) In general, the via vias 12 generally have a deep depth. In order to completely fill the copper (electroplated metal) into such via vias 12 having a deep aspect ratio by electroplating and Without causing defects such as voids in the embedded plated metal, plating must typically be performed in a bottom-up manner such that the pad metallization is preferably grown from the bottom of the vias. Such an electric mine from the bottom up generally utilizes PEG containing various additives such as SPS (mono(3-3⁄4 acid) disulfide) as an electroplating accelerator and SInpress(R) as an inhibitor (Suppress®). Polyethylene glycol (p〇iyethylene glycol), and as An electric ore solution of a uniform level of PEI (polyethyleneimine). After the surface of the substrate absorbs these additives, the effect of these additives is exerted. The step coverage of the film (in print coverage) is generally quite low. However, in order to form a continuous copper seed layer 16' on the surface of the barrier layer 14 by PVD, it must be formed to have a comparable The thickness of the copper seed layer 16 is, for example, about 8 nanometers to 1 nanometer. Therefore, it means that a thinner seed layer needs to be formed. In this respect, Japanese Patent Laid-Open No. 2007-247062 A method is described comprising forming an auxiliary metal layer (seed layer) 20 of ruthenium by conformal CVD on the surface of a barrier layer 14 of titanium or the like (eg, by sputtering on a substrate) On the entire surface of w, as shown in FIG. 2, the inner surface of the via hole 12 is not included) and copper plating is performed using the auxiliary metal layer 2 as a cathode electrode to fill the plating metal (copper) into the via Hole 12. Japanese patent Kaiping No. 2〇〇8_244298 proposes to additionally form a copper seed layer 22 on the surface of the auxiliary metal layer 2G of tantalum, as shown in Fig. 3. Fig. 3 depicts a thickness of about 100 nm formed by a common pvD. Up to 300 nm of copper seed layer 22. Applicant has provided a method of money--the f-plating method consists of continuing the current through a current density of 4 to the amperage 2 between the seed layer and the anode electrode. G. 1 to 5 seconds to form an initial electroplated film, and then form a secondary electroforged film by passing a direct current of a current density of 至5 to 5 amps/dm2 between the 1 seed layer and the anode electrode (see Japanese Patent) Edited 3641372). Shen Shenren has also proposed to apply a step voltage (voltage changes in steps) between the substrate and the anode electrode in the via hole filling money (via_fi eleCt_ating) (see Japanese Patent Laid-Open No. 2005 97732). ). The applicant has also proposed an electric power method for absorbing the additive in the electromine solution 323759 6 201229328 to the surface ruthenium film of the substrate by maintaining the surface of the substrate in contact with the electromineral solution for an expected period, and then implementing The surface of the substrate is plated to form a plated film on the surface of the tantalum film (see Japanese Patent Laid-Open Publication No. 2009-30167). Further, Japanese Patent No. 3780302 proposes a plating method comprising first performing electroplating with a cathode electrode current density of 5 to 10 amps/dm 2 for 10 seconds to 5 minutes, and then performing plating with a cathode electrode current density of 0.5 to 3 amps/dm 2 . Up to 15 minutes to 180 minutes. SUMMARY OF THE INVENTION The thickness of a plating metal (electroplated film) formed by electroplating is proportional to the current density during plating. Therefore, when the plating metal is filled into the via hole by electroplating, the current is generally controlled so that a current suitable for filling the metal via holes into the via hole flows through the anode electrode and covers the via holes. Between the seed layers. Further, in general, a plating solution containing various additives as described above is used for such via via filling plating. Although a plating solution containing an additive is used, it is still difficult to firmly fill a plating metal (such as copper) into the via hole 12 of the deep high aspect ratio (as shown in Fig. 2, the auxiliary metal layer covered with germanium) The layer) 20) does not cause defects (such as voids in the embedded plated metal). For via vias covered with a copper seed layer, the plated metal can be filled into the vias without effecting voids by performing electroplating at a predetermined current density. On the other hand, when electroplating is performed to fill the plating metal (copper) into the via hole of the auxiliary metal layer covered with germanium, voids may be formed in the embedded plating metal. When the copper seed layer 22 having a thickness of about 100 nm to 300 nm is formed on the surface of 7 323759 201229328 of the auxiliary metal layer (seed layer) 20 of the crucible by, for example, a common PVD, the copper seed layer 22 cannot be formed. The entire surface of the auxiliary metal layer 20 is covered, and the auxiliary metal layer 2 of the germanium is exposed to the bottom of the via hole 12, as shown in FIG. When the auxiliary metal layer 2 is used and the copper seed layer 22 is used as a cathode electrode to perform dielectric filling of such a substrate to fill the electric gate metal into the vias 12, the embe will be embedded in the via. A void is formed in the plating metal in the layer via hole 12. This is because the sheet resistance of the auxiliary metal layer 2 高于 is higher than the sheet resistance of the copper seed layer 22 and the sigma metal will be unevenly deposited on the surface of the auxiliary metal layer 2 . The present invention has been made in view of the above circumstances. Accordingly, it is an object of the present invention to provide an electroplating method capable of firmly filling a plating metal (e.g., copper) into a via hole even when the via holes are covered with, for example, germanium (having a slightly thinner copper layer) When the auxiliary metal layer of poor conductivity is exposed, or when, for example, a portion of the auxiliary metal layer is exposed in the via hole, defects (such as voids) are not generated in the embedded metal clock metal. In order to achieve the above object, the present invention provides a plating method comprising: preparing a substrate having a via hole formed in a surface thereof; immersing the substrate in a pretreatment solution to perform pretreatment of the substrate; The substrate is immersed in the plating burr and the voltage between the t voltage and the anode is not applied. The anode electrode is disposed opposite the substrate, thereby replacing the pre-via in the via hole with the plating solution. Processing the solution; performing a step of electroplating of the substrate, and simultaneously controlling the voltage applied to the substrate and the anode electrode to be equal to or higher than a voltage, which is suitable for filling the money metal 323759 8 201229328 into The current of the via hole flows stably between the substrate and the anode electrode; and the second step of performing electroplating of the substrate, while controlling the current flowing between the substrate and the anode electrode The plating metal is filled into the via via. When performing the first step of recording, simultaneously controlling the voltage to be equal to or higher than a voltage value suitable for stably flowing a current of the plating metal into the via hole between the substrate and the anode electrode, The current flowing between the substrate and the anode electrode is temporarily higher in the initial stage of electroplating. Therefore, the plating-inhibiting additive is preferentially absorbed to a portion of the surface on which the auxiliary metal layer such as ruthenium starts to grow. This can contribute to the growth of the electroplated film on the surface of the portion of the auxiliary metal layer that has not yet begun to grow the electroplated film, and the electroplated metal can be uniformly deposited on the surface of the auxiliary metal layer. After uniformly depositing the plating metal on the surface starting from the auxiliary metal layer, a current suitable for filling the plating metal into the via hole stably flows between the substrate and the anode electrode. Next, the second step of plating is performed while controlling the current to a current suitable for filling the plating metal into the via of the via. The second step of the ore system is carried out at a controlled current for a period of time necessary to deposit the desired amount of plating. The plating method allows the plating metal (such as copper) to be preferentially deposited on the bottom of the via hole, that is, from bottom to top, so that the plating metal can be filled into the via hole without Defects (such as voids) are created in the plated metal embedded in the via. The substrate is preferably immersed in the plating solution for a period of from 1 second to 6 seconds without applying a voltage between the substrate and the anode electrode. If the substrate (example 323759 9 201229328 has a copper seed layer covering the via hole) is immersed in the plating solution for too long, and no voltage is applied between the substrate and the anode electrode, the copper seed layer Will receive the damage of the plating solution. Therefore, when the substrate has a small-sized via hole (for example, 1 〇 micrometer to 5 〇 micrometer), the readout is in the ruthenium solution and no voltage is applied to the substrate and the (4) case is about 1Q seconds to 2Q seconds, when the substrate has a via hole of a size (for example, 抖 〜 2 2 sec to 60 sec. _, it is preferable that the first step electroplating can be carried out continuously, for example, i The second to the first minute, the electroplating can be carried out so that the metal plating can be uniformly deposited on the surface of the auxiliary metal layer such as ruthenium 1 and can stably flow between the substrate and the rugged electrode. Current (4) The duty flow (4) The current between the substrate and the anode electrode is implemented in a stepwise manner. Electric: The electroplated metal is gradually deposited in the hole along with the electric ore program. The aspect ratio of the unfilled portion of the via hole is gradually changed 2 = the lower the aspect ratio is, the easier it is to perform via fill plating in a manner of (four) upwards = steady growth of the electric clock at a high current. Electrical hungry & (4) plating time between the plate and the anode electrode Energy, in order to enter the through-hole _ degree change of the dielectric layer, h 〃 electricity (4) belongs to the aspect ratio change of the filling filling portion, that is, 'the individual via holes are not in the present invention _ preferred aspect, The electroplated metal _, the genus is exposed on at least a portion of the surface of the via, the non-copper metal 323759 10 201229328 such as 钌 or the beginning, or an alloy of the above. The electroplated metal (such as copper) can be filled into the Interlayer vias, and bismuth, cobalt or alloys thereof are exposed on at least a portion of the surface of the via, * not causing defects such as voids in the embedded plating metal. The present invention enables electroplating of metals (such as copper) ) capable of firmly filling through vias of deep high aspect ratio even when the via rail is covered with an auxiliary metal layer such as a pin (having a slightly less conductive than the copper seed layer) or when When the auxiliary metal layer is partially exposed to the via hole, it does not cause defects such as voids in the described electro-mineral metal. [Embodiment] A preferred embodiment of the present invention will now be described with reference to the drawings. The description of the contents describes the situation, Performing copper plating on the surface of the substrate to fill copper (key metal) into the via hole provided in the surface of the substrate, thereby forming a via of copper in the substrate. FIG. 4 is for implementing the present invention. A general layout plan of the electroplating apparatus for the electroplating method. This electroplating apparatus is designed to automatically perform all of the electro-mineral processes 'pretreatment of the substrate, electroplating, and subsequent processing of the 5 kWh money in a continuous manner. The interior of the armored panel is divided into a plating space 116 and a cleaning space 114 by the partitioning plate 112, and the plating space 116 is used for performing the plating process of the substrate and plating the plating. Treatment of the substrate of the solution 'This cleaning space 114 is used to carry out other processes (i.e., processes that are not directly related to the clock solution). Two substrate holders 160 (see FIG. 5) are disposed in parallel and are disposed on a partition separated by a partitioning plate 112 that separates the plating space 116 11 323759 201229328 from the cleaning space 114 A substrate attachment/detachment stage 162, which is a substrate delivery section, for attaching the substrate to the respective substrate holders 160 and separating the substrates from the respective substrate holders 160. A load/unload portion 丨2〇 (with a substrate cassette storing substrate attached thereto) is connected to the cleaning space 114. Further, the facility frame no has a console panel 121 disposed thereon. An aligner 122 and two cleaning/drying devices 124 are provided in the cleaning space 114 for aligning the orientation plane of the substrate in a predetermined direction (〇rientati〇 Nf lat) or notch, the cleaning/drying device 124 is used to clean the plated substrate and capture the substrate to dry the substrate. In addition, the first transport robot arm 128 is substantially mounted in the center of the process devices (ie, the aligner 122 and the π cleaning/drying device 124), whereby the process devices 122, 124, The substrate attachment/separation stage 162 and the substrate cassette attached to the load/unload portion UO carry and transport the substrate. The aligner 122 and the cleaning/drying device 124 disposed in the cleaning space 114 are designed to support and process the substrate in a horizontal state, wherein the front side of the substrate faces upward. In the plating space 116, a reservoir 164, a pretreatment device 126, an activation processing device 166, a first water cleaning device 168a, a plating facility 170, and a second water cleaning device 16 are sequentially installed from the partition plate 112. And a gas blowing device 172, wherein the storage device 164 is used for storing or temporarily storing the substrate holder 16 0 ' at the time of 323759 12 201229328. The pretreatment device 12 6 is used for performing pretreatment (pre-wet treatment) A pretreatment liquid (such as pure water (DIW) or the like) cleans the surface of the substrate and enhances its hydrophilicity by dipping the surface of the substrate by a pretreatment liquid, the activation treatment device 166 being used to utilize a mineral acid solution (eg a sulfuric acid or hydrochloric acid) or an organic acid solution (such as citric acid or oxalic acid), for example, an oxide film (having a high resistance value) formed on a seed layer on the surface of the substrate to remove the oxide film The first water cleaning device 168a is for cleaning the surface of the substrate with pure water. The electric money facility 170 is for performing electroplating, and the air blowing device 2 is for dehydrating the electroplated substrate. Two second handling robot arms 174a, 174b are mounted adjacent to the devices for movement along the way 176. One of the second handling robot arms 174a carries the substrate holder 160 between the substrate attachment/separation stage 162 and the reservoir 164. The other second transport robot arm 174b carries the storage 164, the pretreatment device 126, the activation processing device 166, the first water cleaning device 168a, the plating facility Π0, the second water cleaning device 168b, and the air blowing device 172. Substrate holder 160. As shown in Fig. 5, each of the second transfer robot arms 174a, 174b has a vertically extending body 178 and an arm 18 垂直 vertically movable along the body 178 and rotatable about the axis of the body 178. The arm 180 has two substrate holder retaining portions 182 arranged in parallel for detachably holding the substrate holder 160. The substrate holder 160 is designed to support the substrate W in a state where the front surface of the substrate is sealed while sealing the peripheral portion of the substrate, and the substrate W can be attached to the substrate holder 160 and the substrate 323759 13 201229328 W is separated from the substrate holder 160. The reservoir 164, the pre-processing device 126, the activation processing device 166, the water cleaning devices 168a, 168b, and the plating facility 170 are designed to be outwardly projecting with the outer projecting portions of the substrate holders 160 (outwardly projecting p〇rtion) The 160a is joined, thereby supporting the substrate holder 160' such that the substrate holder 160 is suspended in the vertical direction. The pretreatment device 129 has two pretreatment tanks 127 for containing a pretreatment liquid (such as a dissolved oxygen concentration of less than, for example, 2 mg/liter of pure water (oxygenated DIW) or the like). . As shown in FIG. 5, the second transport robot arm 174b is lowered for supporting the arm 180 of the substrate holder 160 (loaded with the substrate cassette) in a vertical state so as to engage the upper end end of the pretreatment tank 127 to suspend The manner of supporting the substrate holder 16〇. Therefore, the pretreatment apparatus 126 is designed such that the substrate holder 160 is immersed in the pretreatment liquid in the pretreatment tank 127 together with the substrate to perform pretreatment (pre_wetting treatment). The activation processing device 166 has two activation processing slots ι83 for containing chemical liquid therein. As shown in FIG. 5, the second transport robot arm is used to support the arm holder 180 of the substrate holder 160 (loaded with the substrate W) in a vertical state to engage the upper end of the activation processing tank 183 for suspension. The substrate holder 160 is supported in a manner. Therefore, the activation processing means 166 is designed such that the substrate holder 16 is immersed with the substrate w in the chemical liquid in the activation processing tank 183 to carry out an activation process. The activation processing slot 183 can be omitted when the activation process is not required. Similarly, the water cleaning device 168a, 168b has two water cleaning tanks 184a and two water cleaning tanks i84b respectively accommodating 14 323759 201229328 pure water, and the plating facility 170 has a plurality of plating solutions therein. One plating bath 186. The water cleaning device 168a, 168b and the plating facility 170 are designed such that the substrate holder 160 is immersed with the substrate w in pure water in the water cleaning tank 184a, 184b or in the plating tank 86. In the solution, water cleaning or plating is carried out in the same manner as described above. Lowering the second transport robot arm 174b for supporting the arm 18 of the substrate holder 160 (loaded with the substrate W) in a vertical state, and ejecting air or inert gas to the substrate W attached to the substrate holder 160 to The liquid attached to the substrate holder 160 and the substrate W is blown away to dehydrate the substrate w. Therefore, the δ 吹 blowing device 172 is designed to perform a blow treatment (b 1 〇wi ng treatment) ° as shown in Fig. 6, each of the electric ore tanks 186 disposed in the plating facility i7〇 is It is designed so as to accommodate a predetermined number of plating solutions Q therein. The distal substrate W (which is maintained in front of the exposed surface (the surface of the money) while the substrate holder 160 is waterproofly sealed to the surrounding portion) is attached to the vertical direction last > Electrochemical solution Q. In this embodiment, 'the plating solution (except for copper ions, supporting electrolyte, and dentate ions) as the plating solution Q contains various additives (such as SPS as an electroplating accelerator). >)), PEG (polyethylene glycol) as an inhibitor, and as a PEI (polyethyleneimine). Preferably, 'sulfuric acid is used as a supported solution, and chloride ion is preferred as a halogen ion." An overflow 200 is placed in the plating bath, around the end of 323759 15 201229328, for containing overflow. The plating solution Q at the edge of the plating bath 186. A circulation pipe 204 is provided with one end of the pump 202 connected to the bottom of the overflow tank 200, and the other end of the circulation line 204 is connected to a plating solution supply inlet provided at the bottom of the plating tank 186 ( Supply inlet)186a. Therefore, the key solution Q in the overflow tank 200 is returned to the plating tank 186 by the driving of the pump 202. Downstream of the pump 202, a constant temperature unit 206 and a filter 208 are inserted into the circulation line 204 for controlling the temperature of the plating solution Q, and the filter 208 is for filtering out the electricity. Foreign matter contained in the clock solution The bottom plate 210 (having a large number of key solution passage holes therein) is attached to the bottom of the plating tank 186. Therefore, the bottom plate 210 divides the inside of the plating tank 186 into the upper substrate processing chamber 214 and the lower plating solution distribution chamber 212. Further, a shield plate 216 (which extends vertically downward) is attached to the lower side surface of the bottom plate 210. According to the plating facility 170, the plating solution Q is introduced into the plating solution distribution chamber 212 of the plating tank 186 by the driving of the pump 202, and flows into the substrate processing chamber 214' through the plating solution passage hole provided in the bottom plate 210. It flows vertically parallel to the surface of the substrate w held by the substrate holder ι6〇, and then flows into the overflow groove 2〇〇. A circular anode electrode 220 having a shape corresponding to the substrate W is held by the anode electrode holder 222 and vertically disposed in the plating tank 186. When the S Xuandian solution Q is filled in the plating bath 186, the anode electrode 220 held by the anode electrode holder 222 becomes immersed in the plating solution Q in the plating tank 16 323759 201229328 186. The substrate W held by the substrate holder i6 is mounted in the plating tank 186. In addition, in the electric clock slot 186, a regulating plate (regUia) plate 224 is disposed between the anode electrode 220 and the substrate W to be mounted in a predetermined position in the plating tank 186 for adjusting the plating The electrical potential in the slot 186. In this embodiment, the adjustment plate 224 is composed of a cylindrical portion 226 and a rectangular flange portion 228 and is made of a dielectric material - polyvinyl chloride. The cylindrical portion 226 has such an opening size and shaft length that it is sufficient to limit the expansion of the electric field. The lower end of the bezel portion 228 of the adjustment plate 224 reaches the bottom plate 210. Between the anode electrode 220 and the substrate W to be mounted in the predetermined position in the key groove 186, a mixing paddle 232 ′ vertically extending as a stirring tool is mounted to reciprocate parallel to the surface of the substrate W to stir An electric ore solution Q between the substrate w and the conditioning plate 224. A sufficient amount of copper ions can be uniformly supplied to the surface of the substrate W by utilizing 5 to remove the paddle (stirring tool) 232 在 during plating. As shown in Figures 7 and 8, the agitating paddle 232 is composed of a component similar to a rectangular plate. The assembly has a uniform thickness "t" of 3 mm to 5 mm and has a similar band defining a vertical extension. A plurality of parallel slits 232a of portion 232b. The agitating paddle 232 is formed of, for example, a resin such as PVC, PP and PTFE, and SUS or titanium having a Tefion coating. Preferably, at least a portion of the dispensing paddle 232 that is in contact with the electromineral solution is electrically isolated. The vertical length L of the paddle 232 and the vertical length L2 of the 323759 17 201229328 slit 232a are sufficiently larger than the vertical dimension of the substrate w. Further, the agitating paddle 232 is designed such that the sum of its lateral length H and its reciprocating distance (reciprocating stroke) is sufficiently larger than the lateral dimension of the substrate W. Preferably, the width and the number of the slits 232a are determined. When the strip portions 2 3 2 b between the slits 2 3 2 a have the necessary properties for effectively plating the solution and (in addition) When the plating solution can effectively pass through the slits 232a, the ribs of the respective strip portions 23 are as narrow as possible. The electroplating facility 170 is provided with a battery power source 250. During electroplating, the positive electrode of the electrowinning power source 250 is connected to the anode electrode 22A via a wire, and the negative electrode of the plating power source 250 is connected to the surface of the substrate w via a wire. The electroplating power source 250 is coupled to a control section (c〇ntr〇1 seCti〇n) 252' and controls the electroplating facility 170 based on signals from the control section 252. A sequence of an electroplating operation performed in the plating apparatus shown in Fig. 4 to fill copper (scrabble metal) into the via hole 12 of the substrate w shown in Fig. 3 will now be described. The substrate W has been manufactured by the following processes, including forming an open via via in the substrate 10 (such as a Shihwa wafer), forming a barrier layer of titanium or the like on the entire surface of the substrate, An auxiliary metal layer 2〇 formed on the surface of the barrier layer 14 and a copper seed having a thickness of about 1 nm to 3 nm on the surface of the auxiliary metal layer 20 Layer 22. In general, the film formed by pvD has a very low step coverage. Therefore, when the copper bb seed layer 22 having a thickness of about 丨〇〇 nanometer to 3 nanometers is formed of PVD, the copper seed layer 22 cannot reach the bottom of the via hole 12 of 323759 201229328, and 钌The auxiliary metal layer 2 is exposed to the via hole 12 of the via. First, the substrate W is placed in the substrate cassette with the front surface (the surface of the money surface) facing upward, and the substrate cassette is attached to the load/unloading portion 120 by the first handling machine. The arm 128 picks up one of the substrates W from the substrate placed on the load/unloading portion 2 and places it on the aligner 122 to align the orientation plane of the substrate w in a predetermined direction. Or a recess. On the other hand, the two substrate holders 16A (which are stored in the reservoir 164 in a vertical state) are taken out by the second transport robot arm 174a, and rotated by 90 degrees so that the substrate holder 16 is horizontally And then placed in parallel on the substrate attachment/separation stage 162. The substrate W aligned in an orientation plane or recess of the substrate W in a predetermined direction is transported and loaded on the substrate holder 16 placed on the substrate attachment/separation stage 162 in a sealed state with the peripheral portion of the substrate. In the middle. The two substrate holders 16 are held simultaneously by the second transfer robot arm 174a, lifted, and transported to the reservoir 164. The substrate 160 is rotated up to 9 degrees to become '4 and lowered vertically so that the two substrate holders 16Q are held (temporarily stored) in the reservoir 164 in a suspended manner. The above operation

签败且于燏存於該儲存器164 至該預處理裝置126。各該基板 323759 19 201229328 w係浸潰在容置於該預處理槽127中的預處理液體（如純水 (DIW))中’藉此實施預處理（預濕處理）。較佳的情況是， 利用真空除氣器（vacuum deaerator)或引進惰性氣體將用 以作為預處理液體的純水的溶氧濃度宜控制在小於2毫 克/公升。接著，以如上所述的相同方式將該兩個基板支架 16〇(各負載有基板W)搬運至該激活處理裝置，其中，該基 板W係浸潰於該激活處理槽ι83所容置的無機酸溶液（如硫 酸或鹽酸）或有機酸溶液（如檸檬酸或草酸）中，以將具有高 電阻的氧化物薄膜自該晶種層的表面蝕刻移除，藉此曝露 出清潔的金屬表面。利用使用於上述預處理中的純水，可 控制激活處理中所使用的酸溶液中的溶氧濃度。在該激活 處理之後’以如上所述的相同方式將該等基板支架16〇(各 負載有該基板W)搬運至該第一水清潔裝置168a，其中，該 基板W的表面係由容置於該第一水清潔槽184a中的純水所 清潔。 在以水清潔之後，以如上所述的相同方式將該兩個基 板支架160 (各負載有該基板w)搬運至該電艘設施17Q的電 鍍槽186上方。該電鍍槽186已經填充有預定數量且具有 預定成分的電鍍溶液q，該電鍍溶液Q係透過該循環系統 (eiixulation system)進行循環。接著降低該基板支架 160’以將該基板支架16〇所握持的基板W浸潰於該電鍍槽 186中的電鍍溶液q中。各該基板w係裝設於該電鍍溶液卩 中面對由該陽極電極支架222所握持的陽極電極22〇的位 置。各陽極電極220係透過該陽極電極支架⑽連接至該 323759 20 201229328 電鍍電源250。 如第9A圖與第9B圖所示，該基板W係持續浸潰於該 電鍍溶液Q中達預定時間（tl_t2)，且it未在該陽極電極22〇 與位於該基板表面上的銅晶種層（及輔助金屬層20)之間 施加電壓，藉此以該電鍍溶液q取代該介層通孔12中的預 處理溶液。因此，利用該電鍍溶液q取代該介層通孔12 中的預處理雜’可避免該介層通孔12底部的銅離子與添 加物變得稀釋。如此-來’可避免電鍍金屬不正常地沉積， 藉此防止«人1¾介層軌12中㈣鍍金射產生缺陷 (如空洞）。 倘若該基板w(其具有覆蓋該介層通孔12的銅晶種層 2雷2 料钱雜^巾料長日㈣且未於該陽極 =銅ί種層22之間施加電壓，則該銅晶種層 寸的二、Γ丨的損害。因此，當該基板具有小尺 該電链溶液"且未於該陽極; 之間施加電壓的較佳時間係10秒 =,與該二種層22 ρ主20秒，而當該基板具 二二1通孔(例如:刚微米)時，該基^的較 住仏貝砰間係2〇秒至6〇秒。 連接錢開始時間t2時，該電鍍電源250的正極係 ==極22〇,且該電錢電源25〇的負極係連接 至該基板W的鋼晶種層22(以及該 ==續實施達預定時間(“)，屬同二 銅曰曰種層22(以及辅助金屬糊與該陽極電讎之間的 323759 21 201229328 電壓控制在使得（適合將電鍍金屬填充進入介層通孔12的） 電流Ci穩定流動於該銅晶種層22(以及該辅助金屬層2〇) 與該陽極電極220之間所需的電壓v,(cv模式）。本文中所 明適合將電鍍金屬填充進入介層通孔12的電流，，係意指 月b夠使彳于電錢金屬填充進入介層通孔12而不至形成空洞 的電流。能夠達到無空洞介層通孔填充電鍍的電流範圍取 決於介層通孔的直徑與深度。所可能使用的最高電流係取 决於因縮減電錄時間而造成產能增加的觀點。 # (不同於第9A圖所示在經控制的電壓下實施第一步 驟電鍍之方法）持續對該基板W實施電鍍以將電鍍金屬填 充進入該介層通孔12達預定時間（t2_t4)時，同時將流動 於該銅晶種層22(以及該辅助金屬層2〇)與該陽極電極22〇 之間的電流控制在如第10B圖所示適合將電鍍金屬填充進 入該介層通孔12的電流GbGXCC模式）時，施加於該銅 晶種層22(以及該辅助金屬層2〇)與該陽極電極22〇之間的 電壓初始採取較低數值並且逐漸增加且在經過某時間區間 之後到達大約固定的電壓值V2,如第1〇A圖所示。於本實 施例中，此電壓V2係用以作為cv模式進入電壓（entry voltage)Vi(V2)。 當如第10B圖所示在經控制的電壓下實施介層通孔填 充電鍍時為什麼採取較低數值的初始電壓之原因也許是因 為電鍍薄膜並未均勻地生長於該辅助金屬層2〇的表面 上，且電流僅局部地流動於該辅助金屬層2〇的表面已開始 生長電鍍薄膜的部份。該電壓隨著電鍍的進展時間而逐漸 323759 22 201229328 增加，且倘若電鍍薄膜開始均勻地生長於該介層通孔中， 則該電壓達到固定數值。然而，由於該電鍍薄膜並未均勻 且精確地生長，故嵌入該介層通孔中的電鍍金屬中將存在 有空洞。 另一方面，當實施該第一步驟電鍍時，同時將施加於 該銅晶種層22(及輔助金屬層20)與該陽極電極220之間的 電壓控制在使電流CK其適合將電鍍金屬填充進入該介層 通孔12)如第9A圖所示穩定地流動於該銅晶種層22(及該 輔助金屬層20)與該陽極電極220之間所必須的電壓Vi(CV 模式），流動於該銅晶種層22與該陽極電極220之間的電 流於電鍍的初始階段暫時較高，如第9B圖所示。因此，用 於抑制電鍍的添加物係優先吸收至輔助金屬層20開始生 長有電鍍薄膜的部份表面上。如此可有助於該輔助金屬層 20尚未開始生長電鍍薄膜的部份表面上的電鍍薄膜生 長，能夠於釕的輔助金屬層20的表面上均勻地沉積該電鍍 金屬。在開始於釕的輔助金屬層20的表面上均勻地沉積電 鍍金屬（銅）之後，適合將該電鍍金屬填充進入該介層通孔 12的電流匕穩定地流動於該銅晶種層22(以及該輔助金屬 層2 0 )與該陽極電極2 2 0之間。 在此實施例中，於第一步驟電鍍期間的電壓係經過選 定與控制，使得適合將該電鍍金屬填充進入該介層通孔12 的電流G穩定地流動。如此一來，可避免電流變得太低而 使得電鍍時間變得太長，或者避免電流變得太高而在嵌入 該介層通孔12中的電鍍金屬中形成空洞。在此實施例的第 23 323759 201229328 -階段電針’即便電流在電鑛開始之後明顯變化，電流 仍成為適合介層通孔填充電鍍的固定電流G。因此，即使 當電鑛作用於輔助金屬層（其表面氧化狀態可於基板中或 多個基板之間發生變異）上時，仍可將㈣基板巾或多個基 板之間的電鍍變異最小化。 舉例而言，第一步驟電鍍的電鍍時間係丨秒至1〇分 鐘。藉由持續實施第一步驟電鍍達上述時間，可將電鍍金 屬均勻地沉積在釕的輔助金屬層2〇的表面上，且能夠穩定 流動於該銅晶種層22(及該輔助金屬；| 2Q)與該陽極電極 220之間的電流。 接著，實施第二步驟電鍍達預定時間（t3_t4)，同時將 流動於該銅晶種層22(及該輔助金屬層2〇)與該陽極電極 220之間的電流控制在適合將電鍍金屬填充進入介層通孔 12的電流dCCC模式）’如第9B圖所示。在此實施例的電 鑛方法中，月b夠谷許在第一步驟電錢的初始階段（cv模式 電鍍）有高電流流動於該銅晶種層22(及該輔助金屬層20) 與該陽極電極220之間，且該高電流接著迅速地變化為適 &將電鍍金屬填充進入介層通孔12的電流c,。該第二步 驟電鍍（cc模式電鍍）係實施於經控制的固定電流Ci持續 達沉積所欲電鍍量所必須的時間。此電鍍方法容許電鍍金 屬（鋼）優先沉積於該介層通孔12的底部，亦即，以自底部 往上的方式，使得該電鍍金屬得以填充進入該介層通孔 12 ’而不致在嵌入的電鍍金屬中產生缺陷（如空洞）。 於自該基板W浸潰於電鍍溶液Q中直到完成電鍍的期 323759 24 201229328 間，該擾拌槳232平行於該基板W的表面進行往復運動，（當 必要時）攪拌該調節板224與該基板W之間的電鍍溶液Q。 倘若在已縮減該介層通孔的深寬比至電鍍溶液能夠輕易到 達電鍍金屬表面的程度之後持續劇烈撥拌該電鍵溶液，則 電鍍薄膜的生長可能減慢且可能耗用更長的時間以完成介 層通孔填充電鍍。在此情況下，較佳的是，當電鍍已進展 至某種程度時，宜降低該電鍍溶液的攪拌強度。在完成電 鍍之後，停止在該陽極電極220與該基板w的銅晶種層 22(以及該輔助金屬層2〇)之間施加電壓。在此之後，再度 由該第二搬運機器手臂174b握持該兩個基板支架16〇(各 負载有基板W)，並且將其自該電鍍槽186撤離。 接著以如上所述的相同方式將該兩個基板支架搬 運至該第二水清潔裝置168b，其中，係藉由將該基板浸潰 在該水清潔槽184b所容置的純水中來清潔該基板的表 面。在那之後，負載有該基板的基板支架160係以如上所 述的相同方式搬運至吹氣裝置（bl〇wing deviceuu，其 中，藉由吹氣或惰性氣體至該基板支架160，以將電鍍液 "災/商自該基板支架16〇移除。在那之後，將負載有基 的基板支* 回歸該儲存器164，並分別經懸掛及握 持於該儲存器164中的預定位置。 該第二搬運機器手冑174b依序重複上述操作，以依 健存-^鍍之後各負載有基板的）基板支架則回歸至該 該儲存請m，並且將該基板支架160懸掛於 力—方面’在電鍍之後負載有基板且已 323759 25 201229328 回歸至該儲存器164的兩個基板支架160同時為該第二搬 運機器手臂174b所鉗制，並且以如上所述的相同方式放置 於該基板附接/分離級162上。 裝設於該清潔空間114中的第一搬運機器手臂128自 該基板附接/分離級162上的基板支架160取出該基板，並 將其搬運至其中一個清潔/烘乾裝置124。在該清潔/烘乾 裝置124中，以例如純水清潔該基板（其保持在前面朝上的 水平位置），並且接著藉由高速旋轉將其甩乾。在那之後， 藉由該第一搬運機器手臂128將該基板回歸至接置於負載 /卸載部份120上的基板卡匣，藉此完成電鍍操作。 實施該第一步驟電鍍的同時也能夠將施加於該銅晶 種層22(以及輔助金屬層20)與該陽極電極220之間的電壓 控制在使得（適合將電鍍金屬填充進入介層通孔12的）電 流穩定流動於該銅晶種層2 2 (以及該輔助金屬層2 0)與該 陽極電極220之間所需的電壓Vi(CV模式），該電壓Vi高於 電壓 VKVAVO。 第11A圖與第11B圖描繪根據本發明另一實施例的電 鍍方法。在此實施例中，基板W首先浸潰於電鍍溶液Q中 達預定時間（t5-t〇而未施加電壓於該陽極電極220與該基 板W的銅晶種層22(以及該輔助金屬層20)之間。接下來， 持續實施該基板W的第一步驟電鍍達預定時間（t6-t7)，同 時將施加於該銅晶種層22(以及該輔助金屬層20)與該陽 極電極22 0之間控制在電壓V3 (CV模式）’該電壓V3係使適 合將電鍍金屬填充進入該介層通孔12的電流C3穩定地流 26 323759 201229328 動於該銅晶種層22(及該輔助金屬層2Q)與該陽極電極22〇 之間所必須的電壓。接下來’實施該基板w的c c模式第二 步驟電鍍’同時將流動於該銅晶種層22(及該輔助金屬^ 20)與該陽極電極220之間的電流控制在步階增加電^ (stepwise increasing current) ： # 〇* n , * 爪 a/ 、 屬歲C3持續達預定時 電流Μ續達預定時間（t8_t9)以及電心持續The signature is lost and stored in the storage 164 to the pre-processing device 126. Each of the substrates 323759 19 201229328 w is impregnated in a pretreatment liquid (e.g., pure water (DIW)) accommodated in the pretreatment tank 127, whereby pretreatment (pre-wet treatment) is carried out. Preferably, the dissolved oxygen concentration of the pure water used as the pretreatment liquid is controlled to be less than 2 mg/liter using a vacuum deaerator or introduction of an inert gas. Next, the two substrate holders 16 (each loaded with the substrate W) are conveyed to the activation processing apparatus in the same manner as described above, wherein the substrate W is impregnated with the inorganic contained in the activation processing tank ι83. An acid solution (such as sulfuric acid or hydrochloric acid) or an organic acid solution (such as citric acid or oxalic acid) is used to etch away an oxide film having high electrical resistance from the surface of the seed layer, thereby exposing a clean metal surface. With the pure water used in the above pretreatment, the dissolved oxygen concentration in the acid solution used in the activation treatment can be controlled. After the activation process, the substrate holders 16 (each loaded with the substrate W) are transported to the first water cleaning device 168a in the same manner as described above, wherein the surface of the substrate W is accommodated The pure water in the first water cleaning tank 184a is cleaned. After cleaning with water, the two substrate holders 160 (each loaded with the substrate w) are carried over the plating bath 186 of the electric boat facility 17Q in the same manner as described above. The plating bath 186 has been filled with a predetermined number of plating solutions q having a predetermined composition, and the plating solution Q is circulated through the eiixulation system. The substrate holder 160' is then lowered to immerse the substrate W held by the substrate holder 16 in the plating solution q in the plating bath 186. Each of the substrates w is disposed in the plating solution 面对 at a position facing the anode electrode 22A held by the anode electrode holder 222. Each anode electrode 220 is connected to the 323759 20 201229328 electroplating power source 250 through the anode electrode holder (10). As shown in FIGS. 9A and 9B, the substrate W is continuously immersed in the plating solution Q for a predetermined time (tl_t2), and it is not at the anode electrode 22 and the copper seed crystal located on the surface of the substrate. A voltage is applied between the layers (and the auxiliary metal layer 20), whereby the pretreatment solution in the via hole 12 is replaced with the plating solution q. Therefore, replacing the pretreatment impurity in the via hole 12 with the plating solution q can prevent the copper ions and the additive at the bottom of the via hole 12 from becoming diluted. In this way, the plating metal is prevented from being deposited abnormally, thereby preventing defects (such as voids) in the (4) gold plating of the human 13⁄4 interlayer track 12. If the substrate w has a copper seed layer 2 covering the via hole 12, and the voltage is applied between the anode and the copper layer 22, the copper is not applied between the anode and the copper layer 22 The damage of the seed layer is two, Γ丨. Therefore, when the substrate has a small rule, the electric chain solution " and not the anode; the preferred time for applying a voltage is 10 seconds =, and the two layers 22 ρ main 20 seconds, and when the substrate has 22 holes (for example: just micron), the base is between 2 sec and 6 〇 seconds. When the money starts at time t2, The positive electrode of the electroplating power source 250 is == 22 〇, and the negative electrode of the electric money source 25 连接 is connected to the steel seed layer 22 of the substrate W (and the == continued for a predetermined time ("), which is the same The bismuth copper layer 22 (and the 323759 21 201229328 voltage between the auxiliary metal paste and the anode electrode is controlled such that a current Ci suitable for filling the plating metal into the via hole 12 is stably flown to the copper seed The required voltage v between the layer 22 (and the auxiliary metal layer 2A) and the anode electrode 220, (cv mode). It is suitable for filling the plated metal into the present invention. The current of the layer via hole 12 means that the current of the moon b is enough to fill the via hole 12 into the via hole 12 without forming a cavity. The current range of the hole-free via filling plating depends on The diameter and depth of the vias. The highest current that can be used depends on the viewpoint of increased capacity due to reduced recording time. # (Different from the first step of plating at a controlled voltage as shown in Figure 9A) The method of continuously performing electroplating on the substrate W to fill the via metal into the via hole 12 for a predetermined time (t2_t4) while flowing to the copper seed layer 22 (and the auxiliary metal layer 2) The current between the anode electrode 22A is controlled to be applied to the copper seed layer 22 (and the auxiliary metal layer) when the current GbGXCC mode suitable for filling the via hole 12 into the via hole 12 as shown in FIG. 10B is controlled. The voltage between the anode electrode 22 and the anode electrode 22 初始 initially takes a lower value and gradually increases and reaches a fixed voltage value V2 after a certain period of time has elapsed, as shown in FIG. 1A. In this embodiment , this voltage V2 Used as the cv mode entry voltage Vi(V2). The reason why a lower value initial voltage is used when performing via via fill plating at a controlled voltage as shown in Fig. 10B is probably because The plating film is not uniformly grown on the surface of the auxiliary metal layer 2, and the current flows only locally to the portion of the surface of the auxiliary metal layer 2 which has begun to grow the plating film. The voltage progresses with the progress of the plating. Gradually 323759 22 201229328 is added, and if the plating film starts to grow uniformly in the via hole, the voltage reaches a fixed value. However, since the plated film is not uniformly and accurately grown, there will be voids in the plated metal embedded in the via hole. On the other hand, when performing the first step of electroplating, the voltage applied between the copper seed layer 22 (and the auxiliary metal layer 20) and the anode electrode 220 is simultaneously controlled so that the current CK is suitable for filling the plating metal. Entering the via hole 12) as shown in FIG. 9A, the voltage Vi (CV mode) necessary to stably flow between the copper seed layer 22 (and the auxiliary metal layer 20) and the anode electrode 220, flowing The current between the copper seed layer 22 and the anode electrode 220 is temporarily higher in the initial stage of electroplating, as shown in Fig. 9B. Therefore, the additive for suppressing electroplating is preferentially absorbed to the surface of the portion where the auxiliary metal layer 20 starts to grow with the electroplated film. This can contribute to the growth of the electroplated film on the surface of the auxiliary metal layer 20 which has not yet begun to grow the electroplated film, and can uniformly deposit the electroplated metal on the surface of the auxiliary metal layer 20 of the crucible. After uniformly depositing a plating metal (copper) on the surface of the auxiliary metal layer 20 starting from the crucible, a current suitable for filling the plating metal into the via hole 12 is stably flowing to the copper seed layer 22 (and The auxiliary metal layer 20) is between the anode electrode 220. In this embodiment, the voltage during the first step of plating is selected and controlled such that the current G suitable for filling the plating metal into the via hole 12 is stably flowed. In this way, it is possible to prevent the current from becoming too low to make the plating time too long, or to prevent the current from becoming too high to form a void in the plating metal embedded in the via hole 12. In the 23rd 323759 201229328 - Stage Electro-Needle of this embodiment, even if the current changes significantly after the start of the electric ore, the current becomes a fixed current G suitable for the via-hole filling plating. Therefore, even when the electric ore acts on the auxiliary metal layer whose surface oxidation state can be mutated in the substrate or between the plurality of substrates, the plating variation between the (4) substrate towel or the plurality of substrates can be minimized. For example, the plating time of the first step plating is from leap seconds to 1 minute. By continuously performing the first step of plating for the above time, the plating metal can be uniformly deposited on the surface of the auxiliary metal layer 2 of the crucible, and can stably flow to the copper seed layer 22 (and the auxiliary metal; | 2Q And the current between the anode electrode 220. Then, the second step of plating is performed for a predetermined time (t3_t4), while the current flowing between the copper seed layer 22 (and the auxiliary metal layer 2) and the anode electrode 220 is controlled to be suitable for filling the plating metal into The current dCCC mode of the via hole 12 is as shown in FIG. 9B. In the electric ore method of this embodiment, the monthly b is sufficient to have a high current flowing in the initial stage of the first step of electricity (cv mode plating) to the copper seed layer 22 (and the auxiliary metal layer 20) and the Between the anode electrodes 220, and the high current then rapidly changes to a current c that fills the vias 12 with the plating metal. This second step of electroplating (cc mode plating) is carried out for a period of time necessary for the controlled fixed current Ci to continue to deposit the desired amount of plating. This plating method allows the plating metal (steel) to be preferentially deposited on the bottom of the via hole 12, that is, in a manner from the bottom up, so that the plating metal can be filled into the via hole 12' without being embedded. Defects (such as voids) in the electroplated metal. Between the substrate W being immersed in the plating solution Q until the completion of the plating period 323759 24 201229328, the scrambled paddle 232 reciprocates parallel to the surface of the substrate W, and when necessary, agitates the adjustment plate 224 A plating solution Q between the substrates W. If the aspect ratio of the via hole has been reduced until the plating solution can easily reach the level of the plated metal surface, the plating solution may be vigorously mixed, and the growth of the plating film may be slowed down and may take longer. The via via fill plating is completed. In this case, it is preferred that when the electroplating has progressed to some extent, the stirring strength of the plating solution is preferably lowered. After the plating is completed, a voltage is applied between the anode electrode 220 and the copper seed layer 22 (and the auxiliary metal layer 2) of the substrate w. Thereafter, the two substrate holders 16b (each loaded with the substrate W) are again held by the second transfer robot arm 174b, and are evacuated from the plating tank 186. The two substrate holders are then transported to the second water cleaning device 168b in the same manner as described above, wherein the substrate is cleaned by dipping the substrate in pure water contained in the water cleaning tank 184b. The surface of the substrate. After that, the substrate holder 160 loaded with the substrate is transported to the air blowing device in the same manner as described above, wherein the plating solution is blown by inert gas or inert gas to the substrate holder 160. " Disaster/commercial removal from the substrate holder 16A. After that, the substrate-loaded substrate support* is returned to the reservoir 164 and suspended and held in a predetermined position in the reservoir 164, respectively. The second transfer robot hand 174b repeats the above operation in sequence, so that the substrate holders loaded with the substrate after the plating is returned to the storage m, and the substrate holder 160 is suspended in the force-side' The two substrate holders 160 loaded with the substrate after plating and having returned to the reservoir 164 have been clamped for the second handling robot 174b and placed on the substrate in the same manner as described above/ Separation stage 162. The first transfer robot arm 128 mounted in the cleaning space 114 takes the substrate from the substrate holder 160 on the substrate attachment/separation stage 162 and carries it to one of the cleaning/drying devices 124. In the cleaning/drying device 124, the substrate is cleaned with, for example, pure water (which is held in a horizontal position facing upward), and then dried by high-speed rotation. After that, the substrate is returned to the substrate cassette attached to the load/unload portion 120 by the first transfer robot arm 128, thereby completing the plating operation. Performing the first step of electroplating can also control the voltage applied between the copper seed layer 22 (and the auxiliary metal layer 20) and the anode electrode 220 such that it is suitable for filling the plating metal into the via hole 12 The current flows stably between the copper seed layer 2 2 (and the auxiliary metal layer 20) and the anode electrode 220 at a desired voltage Vi (CV mode), which is higher than the voltage VKVAVO. 11A and 11B depict an electroplating method in accordance with another embodiment of the present invention. In this embodiment, the substrate W is first immersed in the plating solution Q for a predetermined time (t5-t 〇 without applying a voltage to the anode electrode 220 and the copper seed layer 22 of the substrate W (and the auxiliary metal layer 20). Next, the first step of the substrate W is continuously performed for a predetermined time (t6-t7) while being applied to the copper seed layer 22 (and the auxiliary metal layer 20) and the anode electrode 22 0 . Controlled between voltage V3 (CV mode), the voltage V3 is such that the current C3 suitable for filling the plating metal into the via hole 12 is stably flowed 26 323759 201229328 to the copper seed layer 22 (and the auxiliary metal) The voltage required between layer 2Q) and the anode electrode 22A. Next, 'the cc mode second step plating of the substrate w is performed' while flowing to the copper seed layer 22 (and the auxiliary metal ^ 20) The current between the anode electrodes 220 is controlled by a stepwise increasing current: # 〇* n , * the claw a / , the current C3 continues to reach a predetermined time, the current continues for a predetermined time (t8_t9), and the core continued

達預疋時間（ts-tl。）。該電流（：4與C 充進入該介層通孔12。 、C5亦適合將電鑛金屬填 中時當!進展而逐漸沉積於介層… 中時各,1層通孔12未經填充部份 減）。深寬比越低，介層通孔填充 寬比逐漸改交（縮 定地以自底部往上的方以ί又越容易在高電流下穩 改變（增加）流動於該基^該膜。因此，藉由步階 電鍵時間並且增加產能，以^應電2間的電流可縮減 通孔12的程度變化（亦即，各：；:金屬填充進入該介層 寬比的變化^ 層通孔未經填充部份的深 19者在如第2圖所7^基板具有形成於覆蓋包含介層 内部表面的整體基板表面之阻障層14上的(釕的) ==層2〇的情況下’可藉由本發明的電鑛方法將電鍍 由吝4進入該；1層通孔12而不至在經欲入的電鍍金屬 料箱^工/同的缺陷。具體而言’首先藉由將該基板浸潰 於^處理溶液中使該基板經過上述的預處理。在預處理 w _ ^基板―於電鑛溶液中’且未施加電壓於該基板 助金屬層20與位於該基板對面的陽極電極220之 323759 27 201229328 間，藉此以電鍍溶液取代該介層通孔12中的預處理溶液。 接下來，實施該基板W的第一步驟電鍍，同時將施加於該 基板W的輔助金屬層20與該陽極電極220之間的電壓（CV 模式）控制為等於或高於使（適合將電鍍金屬填充進入介層 通孔12的）電流穩定地流動於該基板W與該陽極電極220 之間所必須的電壓。接下來，實施該基板W的第二步驟電 鍍，同時將流動於該基板W與該陽極電極220之間的電流 (CC模式）控制在適合將電鍍金屬填充進入介層通孔12的 電流。 當（不同於第9A圖所示在經控制的電壓下實施第一步 驟電鍍之方法）持續對該基板W實施電鍍以將電鍍金屬填 充進入該介層通孔12達預定時間（tu-ti2)時，同時將流動 於該輔助金屬層20與該陽極電極220之間的電流控制在如 第12B圖所示適合將電鍍金屬填充進入該介層通孔12的電 流Ce (CC模式）時，施加於該輔助金屬層2 0與該陽極電極 220之間的電壓初始採取較低數值並且逐漸增加，且在經 過某時間區間之後到達大約固定的電壓值V6,如第12A圖 的實線所示。因此，採用等於或高於此電壓V6的電壓作為 CV模式進入電壓。 相較於上述情況（如第12A圖的虛線所示，其中，該 CC模式電鍍實施於具有形成輔助金屬層20上的銅晶種層 22的基板上），本實施例所施加的電壓耗費較長時間到達 固定電壓V6。這是因為相較於銅晶種層22部份覆蓋該介 層通孔12中的輔助金屬層20(如第2圖及第3圖所示）的 28 323759 201229328 膏开/本實〜例具有面積較大的輔助金屬層20。另一方 面：可藉由持續實施⑺模式第一步驟電鍍達更長時間，以 將電錢金屬均勻地沉積於第2圖所示的輔助金屬層上。 在電錢金屬_均勻地沉積在該卿金屬層2的表面上之 後’適合將電鍍金屬填充進人齡層通孔 流動於該辅助金屬層2。與該陽極電極22〇之間。‘疋也 上藉由在第一步驟電鍍之後實施第二步驟電鍍，同時控 制該電流（α料）’钱金屬最終可填充進人該介層通孔 2且不致於經'^人的電錢金屬中產生如空洞之缺陷。 且非意圖以任何方 以下範例進一步詳細描述本發明， 式限制本發明。 [範例1] 。基板樣本係由以下製程所製造，該製程包括：在石夕晶 圓表面形成直# 7微米且深度85微米的介層通孔；藉由 在整體aa圓表面（包含該介層通孔的内部表面）上形成 厚度100奈米的鈦阻障層；藉由CVD在該阻障層的表面上 3成厚度1〇奈米的釕層作為辅助金屬層；以及藉由pVD 在該輔助金屬層的表面上形成厚度奈米的銅晶種層。 ^該樣本係浸潰於溶氧濃度小於2毫克/公升的純水（除 氧DIW)中持續i至1〇分鐘’以實施該樣本的預處理（預濕 處理）。在預處理之後，將該樣本浸潰於電鍍溶液中達30 各且未轭加電壓於陽極電極與該樣本的鋼晶種層（以及輔 助金屬層）之間。該電鍍溶液具有下列成分：200公克/公 升的五水硫酸銅（copper sulfate pentahydrate) ; 50 公 323759 29 201229328 克/公升的硫酸（sulfuric acid) ; 50毫克/公升的氣 (chlorine) ’以及適1添加物。接著，在維持該樣本浸潰 於該電鍍溶液中的同時，在該陽極電極與該樣本的銅晶種 層（及輔助金屬層）之間施加0.3伏特的電壓持續達2分 鐘，以在CV模式下實施第一步驟電鍍。在第一步驟電鍍之 後，藉由在該陽極電極與該樣本的銅晶種層（及輔助金屬層） 之間通過0.3安培/dra2(ASD)的電流持續達12〇分鐘以在 CC模式下實施第二步驟電鍍。 [範例2] 基板樣本係由以下製程所製造，該製程包括··在矽晶 圓表面形成直徑7微米且深度85微米的介層通孔；藉由 PVD在整體晶圓表面（包含該介層通孔的内部表面）上形成 厚度100奈米的鈦阻障層；以及藉由CVD在該阻障層的表 面上形成厚度10奈米的釕層作為輔助金屬層。 該樣本係浸潰於溶氧濃度小於2毫克/公升的純水（除 氧DIW)中持續1至1〇分鐘，以實施該樣本的預處理（預濕 處理）。在預處理之後，將該樣本浸潰於如範例丨所使用的 電鍍溶液中達30秒且未施加電壓於陽極電極與該樣本的 輔助金屬層之間。接著，在維持該樣本浸潰於該電鍍溶液 中的同時，在該陽極電極與該樣本的銅晶種層（及輔助金屬 層）之間施加〇. 3伏特的電壓持續達5分鐘，以在cv模式 下實施第一步驟電鍍。在第一步驟電鍍之後，藉由在該陽 極電極與該樣本的輔助金屬層之間通過〇. 3安培/dm2(ASD) 的電流持續達120分鐘以在cc模式下實施第二步驟電鍍。 30 323759 201229328 [對照範例1] 9 / 1錢㈣相同基板樣本係浸潰於溶氧濃度小 f 太么升的純水(除氧DW中持續1至10分鐘，以 太^於^預處理（預濕處理）。在預處理之後，將該樣 r :晤/乾例1所使用的電鍍溶液中達30秒且未施加電 :二，二電極與該樣本的銅晶種層(及辅助金屬層)之間。 >者料雜本浸潰於該電鍍溶液中的同時，藉由在 «亥陽，電極與該樣本的銅晶種層（及輔助金屬層）之間通過 0.3安培/dm2(ASD)的電流持續達120分鐘以在cc模式下 實施電鍍。 [對照範例2] 如範例2所使用的相同基板樣本係浸潰於溶氧濃度小 於2宅克/公升的純水（除氧刚）中持續i至ι〇分鐘，以 實施該樣本的賴理（預祕理）。在财狀後，將該樣 本賴於如範例丨所❹的電麟液中達3()秒且未施加電 壓於陽極電極與該樣本的輔助金屬層之間。接著，在維持 該樣本浸潰於該钱溶液中的同時，藉由在該陽極電極與 該樣本的輔助金制之間通過〇.3安培—⑽）的電流 持續達120分鐘以在CC模式下實施電鍍。 第13圖顯示自範例i與範例2以及對照範例i斑對 照範例2職察㈣的時間與施一該陽㈣極和該基板 樣本之間的電壓之間的關係。第14圖顯示自範例ι盘範例 2以及對照範例i與對照範例2所觀察得到的時間盘流動 於該陽極電極和該基板樣本之間的電流之間的關係。如第 323759 31 201229328 13圖所示’在對照範例1與對照範例2中，需要較長的時 間以達到穩定的電壓。尤其在對照範例2中，係於該釕層 上實施電鍍’需要相當長的時間以達到穩定的電壓。如第 14圖所示’在範例1與範例2中，於電鍍初始階段的高電 流迅速降低至適合介層通孔填充電鍍的電流。 第15圖與第16圖分別描繪範例1與範例2中基板樣 本的介層通孔在將電鍍金屬（銅）填充進入介層通孔後之圖 式；以及第17圖與第18圖分別描繪對照範例1與對照範 例2中基板樣本的介層通孔在將電鍍金屬（銅）填充進入介 層通孔後之圖式。 如第15圖與第16圖所示，在範例1與範例2中，沒 有缺陷（如空洞）的電鍍金屬（銅）3〇4係嵌入設置於該基板 樣本300中的介層通孔302中。相較之下，如第17圖所示， 在對照範例1中，空洞V係形成於嵌入該基板樣本300的 介層通孔302中的電鍍金屬（銅）304的底部。再者，如第 18圖所示，在對照範例2中，空洞V係形成於嵌入該基板 樣本300的介層通孔302中的電鍍金屬（銅）304的令間。 上述結果係囊整於下表1。 電鍍條件 經嵌入的電鍍金屬之狀態 範例1 無空洞 範例2 無空洞 對照範例1 空洞形成於介層通孔的底部 對照範例2 空洞形成於介層通孔的中間 [表1] 32 323759 201229328 儘官已參考較佳實施例對本發明進行描述，且可理解 到本發明並未限定於上述實施例，但是本發明的各種變化 與變更皆涵蓋於本制書所傳達的發明概念之範嘴内。 【圖式簡單說明】 第1A至1C圖係以製程步驟序列描繪用於產生具有鋼 穿孔的基板之製程，該銅穿孔垂直地貫穿該基板； 第2圖係描繪在阻障層上形成輔助金屬層之剖面圖， 該阻障層覆蓋基板的整體表面（包含介層通孔的表面）； 第3圖係描繪在阻障層上連續形成輔助金屬層與鋼晶 種層之剖面圖，該阻障層覆蓋基板的整體表面（包含介層通 孔的表面）； 第4圖係用於實施本發明的電鑛方法的電鍍設備之總 體佈局平面圖； 第5圖係設置於第4圖所示的電鍍設備中的第二搬運 機器手臂之示意圖； 第6圖係設置於第4圖所示的電鍍設備中的電鍍設施 之示意剖面圖； 第7圖係設置於第6圖所示的電鍍設施中的攪拌槳 (攪拌工具）之平面圖； 一 第8圖係沿著第7圖的線A-A之剖面圖； 第9A圖係顯示時間以及施加在陽極電極與基板之間 的電壓之間的關係，該關係係根據本發明的實施例實施電 鍍而觀察得到； 323759 33 201229328 第9B圖係顯示時間以及流動於該陽極電極與該基板 之間的電流之間的關係’該關係是根據本發明的實施例實 施電鍍而觀察得到； 第10A圖係顯示時間以及施加在陽極電極與基板之間 的電壓之間的關係’該關係係在受控制電流下實施第3圖 所示的基板表面的電鍍而觀察得到； 第10B圖係顯示時間以及流動於該陽極電極與該基板 之間的電流之間的關係’該關係係在受控制電流下實施第 3圖所示的基板表面的電鍍而觀察得到； 第11A圖係顯示時間以及施加在陽極電極與基板之間 的電壓之間的關係，該關係係根據本發明的另一實施例實 施電鍍而觀察得到； 第11 β圖係顯示時間以及流動於該陽極電極與該基板 之間的電流之間的關係，該關係係根據本發明的另一實施 例實施電鍍而觀察得到； 第12Α圖係顯示時間以及施加在陽極電極與基板之間 的電壓之間的關係，該關係係在受控制電流下實施第2圖 所示的基板表面的電鍍而觀察得到； 第12Β圖係顯示時間以及流動於該陽極電極與該基板 之間的電流之間的關係’該關係係在受控制電流下實施第 2圖所示的基板表面的電鍍而觀察得到； 第13圖係顯示自範例1與範例2以及對照範例1與 對照範例2所觀察得到的時間與施加在陽極電極和基板樣 本之間的電壓之間的關係； 323759 34 201229328 第14圖係顯示自範例1與範例2以及對照範例1與 對照範例2所觀察得到的時間與流動於該陽極電極和該基 板樣本之間的電流之間的關係； 第15圖係插繪範例1中基板樣本的介層通孔在將電 錢金屬（銅）填充進入介層通孔後之圖式； 第16圖係插繪範例2中基板樣本的介層通孔在將電 鍍金屬（銅）填充進入介層通孔後之圖式； 圖係私'纟會對照範例1中基板樣本的介廣通孔在 第18圖係描繪對照範例 _鑛·金屬（鋼）填充道 【主要元件符號說明】 將電㈣屬（銅）填充進入介層通孔後之圖式·，以及 第 18 圖值 te： a . . _ . ^ . 10 14 18 22 112 116 121 124 127 160 162 166 基底 阻障層 電鍍金屬 鋼晶種層 分隔板 電鍍空間 主控面板 清潔/烘乾震置 預處理槽 基板支架 基板附接/分離級 激活處理裝置 通孔後之圖式。 12 介層通孔 16 銅晶種層 20 輔助金屬層 110 設施框架 114 清潔空間 120 負载/卸載部份 122 對準器 126 預處理裴置 128 第一搬運機器^ 160a 向外突出部份 164 儲存器 168a 第一水清潔裴】 323759 35 201229328 168b 第二水清潔裝置 170 電鍍設施 172 吹氣裝置 174a 第二搬運機器手臂 174b 第二搬運機器手臂 176 執道 178 本體 180 手臂 182 基板支架握持部份 183 激活處理槽 184a 水清潔槽 184b 水清潔槽 186 電鍍槽 186a 電鍍溶液供應入口 200 溢流槽 202 泵 204 循環管路 206 定溫單元 208 過濾器 210 底板 212 下側電鍍溶液分配室 214 上側基板處理室 216 防護板 220 陽極電極 222 陽極電極支架 224 調節板 226 圓柱部份 228 矩形邊圈部份 232 攪拌槳 232a 狹縫 232b 帶狀部份 250 電鍍電源 252 控制段 300 基板樣本 302 介層通孔 304 電鍍金屬 d 直徑 h 深度 H 側向長度 Li 垂直長度 l2 垂直長度 Q 電鍍溶液 t 厚度 V 空洞 w 基板 36 323759Pre-emptive time (ts-tl.). The current (: 4 and C are charged into the via hole 12. C5 is also suitable for filling the electric ore metal when it is filled! When it is gradually deposited in the interlayer... each layer, the through hole 12 is not filled. Subtraction). The lower the aspect ratio, the more the via fill-to-width ratio is gradually changed (the shrinkage is from the bottom up, and the easier it is to change (increase) at high current to flow to the substrate. By stepping the key time and increasing the capacity, the current between the two electrodes can reduce the degree of change of the through hole 12 (that is, each:;: the filling of the metal into the width ratio of the interlayer) The depth 19 of the filled portion is in the case where the substrate of Fig. 2 has a (钌) == layer 2〇 formed on the barrier layer 14 covering the surface of the entire substrate including the inner surface of the interlayer. The electroplating method of the present invention can be used to electroplate from the crucible 4; the 1 layer of vias 12 and not to the defects in the electroplated metal bins to be infused. Specifically, 'first by using the substrate Immersing in the treatment solution causes the substrate to undergo the above pretreatment. In the pretreatment w _ ^ substrate - in the electromine solution ' and no voltage is applied to the substrate metallization layer 20 and the anode electrode 220 opposite the substrate Between 323759 27 and 201229328, the pretreatment solution in the via hole 12 is replaced by a plating solution. Next, the first step of plating of the substrate W is performed while controlling the voltage (CV mode) between the auxiliary metal layer 20 applied to the substrate W and the anode electrode 220 to be equal to or higher than (suitable for The current of the plating metal filling into the via hole 12 stably flows between the substrate W and the anode electrode 220. Next, the second step of performing the substrate W is performed while flowing on the substrate. The current between W and the anode electrode 220 (CC mode) is controlled at a current suitable to fill the plated metal into the via via 12. When (different from Figure 9A, the first step of plating is performed at a controlled voltage) The method of continuously plating the substrate W to fill the via metal into the via hole 12 for a predetermined time (tu-ti2) while flowing current between the auxiliary metal layer 20 and the anode electrode 220 When the current Ce (CC mode) suitable for filling the plating metal into the via hole 12 as shown in FIG. 12B is controlled, the voltage applied between the auxiliary metal layer 20 and the anode electrode 220 is initially taken lower. number And gradually increasing, and after reaching a certain time interval, reaching a fixed voltage value V6, as shown by the solid line in Fig. 12A. Therefore, a voltage equal to or higher than this voltage V6 is used as the CV mode input voltage. In the above case (as shown by the broken line in Fig. 12A, wherein the CC mode plating is performed on the substrate having the copper seed layer 22 formed on the auxiliary metal layer 20), the voltage applied in this embodiment takes a long time to arrive. The voltage V6 is fixed. This is because the copper metal layer 22 partially covers the auxiliary metal layer 20 in the via hole 12 (as shown in FIGS. 2 and 3). 28 323759 201229328 Paste/Ben The solid example has an auxiliary metal layer 20 having a large area. On the other hand, it can be electroplated for a longer period of time by continuously performing the (7) mode first step to uniformly deposit the money metal on the auxiliary metal layer shown in Fig. 2. After the electric money metal _ is uniformly deposited on the surface of the enamel metal layer 2, it is suitable to fill the electroplated metal into the through hole of the aged layer to flow to the auxiliary metal layer 2. Between the anode electrode 22 and the anode electrode. '疋 also by performing the second step of electroplating after the first step of electroplating, while controlling the current (α material) 'money metal can finally be filled into the via hole 2 and not to pass the '^ person's electricity money Defects such as voids in the metal. The invention is not intended to be described in further detail by any of the following examples, which are intended to limit the invention. [Example 1]. The substrate sample is manufactured by the following process: forming a via hole of a thickness of #7 μm and a depth of 85 μm on the surface of the stone wafer; by the inner aa circular surface (including the inside of the via hole) a titanium barrier layer having a thickness of 100 nm is formed on the surface; a tantalum layer having a thickness of 1 nm on the surface of the barrier layer is used as an auxiliary metal layer by CVD; and a pVD is in the auxiliary metal layer A copper seed layer of a thickness of nanometer is formed on the surface. ^ The sample was immersed in pure water (deoxygenated DIW) having a dissolved oxygen concentration of less than 2 mg/liter for i to 1 Torr to carry out pretreatment (pre-wet treatment) of the sample. After pretreatment, the sample was immersed in a plating solution for up to 30 and yoke was applied between the anode electrode and the steel seed layer (and the auxiliary metal layer) of the sample. The plating solution has the following composition: 200 g / liter of copper sulfate pentahydrate; 50 g 323759 29 201229328 g / liter of sulfuric acid; 50 mg / liter of chlorine ' and 1 Additives. Next, while maintaining the sample immersed in the plating solution, a voltage of 0.3 volts is applied between the anode electrode and the copper seed layer (and the auxiliary metal layer) of the sample for 2 minutes to be in the CV mode. The first step of electroplating is carried out. After the first step of electroplating, the current is carried out in CC mode by passing an electric current of 0.3 amps/dra2 (ASD) between the anode electrode and the copper seed layer (and the auxiliary metal layer) of the sample for 12 〇 minutes. The second step is electroplating. [Example 2] The substrate sample was fabricated by a process comprising: forming a via hole having a diameter of 7 μm and a depth of 85 μm on the surface of the germanium wafer; and covering the entire wafer surface by PVD (including the via layer) A titanium barrier layer having a thickness of 100 nm is formed on the inner surface of the through hole; and a tantalum layer having a thickness of 10 nm is formed on the surface of the barrier layer by CVD as an auxiliary metal layer. The sample was immersed in pure water (deoxygenated DIW) having a dissolved oxygen concentration of less than 2 mg/liter for 1 to 1 minute to carry out pretreatment (pre-wet treatment) of the sample. After pretreatment, the sample was immersed in the plating solution as used in the example 达 for 30 seconds and no voltage was applied between the anode electrode and the auxiliary metal layer of the sample. Next, while maintaining the sample immersed in the plating solution, a voltage of 〇3 volts is applied between the anode electrode and the copper seed layer (and the auxiliary metal layer) of the sample for 5 minutes to The first step of electroplating is carried out in the cv mode. After the first step of electroplating, the second step of electroplating is performed in cc mode by passing an electric current of 安3 amps/dm2 (ASD) between the anode electrode and the auxiliary metal layer of the sample for 120 minutes. 30 323759 201229328 [Control Example 1] 9 / 1 money (4) The same substrate sample is impregnated with pure water with a small dissolved oxygen concentration of too much (except oxygen DW for 1 to 10 minutes, ether ^ ^ ^ pretreatment (pre Wet treatment). After pretreatment, the sample r was used in the plating solution used in Example 1 for 30 seconds and no electricity was applied: two, two electrodes and the copper seed layer of the sample (and the auxiliary metal layer) Between the > the material is impregnated in the plating solution, by passing 0.3 amp/dm2 between the electrode and the copper seed layer (and the auxiliary metal layer) of the sample. The current of ASD) lasted for 120 minutes to perform electroplating in cc mode. [Comparative Example 2] The same substrate sample as used in Example 2 was impregnated with pure water having a dissolved oxygen concentration of less than 2 dg/L. In the middle of i to ι〇 minutes to implement the sample (pre-clinical). After the financial situation, the sample was placed in the electric fluid for example for 3 () seconds and was not applied. a voltage between the anode electrode and the auxiliary metal layer of the sample. Next, while maintaining the sample immersed in the money solution, Between the anode electrode and the auxiliary gold through the sample 〇.3 ampere -⑽) current for 120 minutes to carry out plating CC mode. Figure 13 shows the relationship between the time between the example i and the example 2 and the comparative example i spot contrast example 2 (4) and the voltage between the positive (four) pole and the substrate sample. Fig. 14 is a graph showing the relationship between the current flowing from the sample disk 2 and the control sample 2 and the control sample 2 flowing between the anode electrode and the substrate sample. As shown in Fig. 323759 31 201229328, in the comparative example 1 and the comparative example 2, it takes a long time to reach a stable voltage. Especially in Comparative Example 2, it takes a considerable time to perform plating on the tantalum layer to achieve a stable voltage. As shown in Fig. 14, in Examples 1 and 2, the high current in the initial stage of electroplating is rapidly reduced to a current suitable for via via filling plating. FIGS. 15 and 16 respectively depict patterns of via holes of the substrate samples in Examples 1 and 2 after filling the plated metal (copper) into the via holes; and FIGS. 17 and 18 respectively depict The via holes of the substrate samples of Comparative Example 1 and Comparative Example 2 were patterned after filling the plating metal (copper) into the via holes. As shown in FIGS. 15 and 16, in the examples 1 and 2, the plated metal (copper) 3〇4 having no defects (such as voids) is embedded in the via hole 302 provided in the substrate sample 300. . In contrast, as shown in Fig. 17, in Comparative Example 1, a void V is formed at the bottom of the plating metal (copper) 304 embedded in the via hole 302 of the substrate sample 300. Further, as shown in Fig. 18, in Comparative Example 2, the void V is formed between the plating metal (copper) 304 embedded in the via hole 302 of the substrate sample 300. The above results are encapsulated in Table 1 below. Plating conditions: state of embedded metal plating Example 1 voidless example 2 voidless control example 1 void formed at the bottom of the via hole comparison example 2 void formed in the middle of the via hole [Table 1] 32 323759 201229328 The present invention has been described with reference to the preferred embodiments thereof, and it is understood that the invention is not limited to the above-described embodiments, but various changes and modifications of the present invention are included in the scope of the inventive concepts disclosed in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are diagrams depicting a process for producing a substrate having a steel perforation through a substrate in a process sequence sequence, the copper perforations extending vertically through the substrate; and FIG. 2 depicting formation of an auxiliary metal on the barrier layer a cross-sectional view of the layer, the barrier layer covering the entire surface of the substrate (the surface including the via hole); FIG. 3 is a cross-sectional view showing the continuous formation of the auxiliary metal layer and the steel seed layer on the barrier layer, the resistance The barrier layer covers the entire surface of the substrate (the surface including the via hole); FIG. 4 is a general layout plan view of the plating apparatus for implementing the electric ore method of the present invention; FIG. 5 is set as shown in FIG. Schematic diagram of the second transfer robot in the electroplating apparatus; Fig. 6 is a schematic cross-sectional view of the electroplating facility provided in the electroplating apparatus shown in Fig. 4; Fig. 7 is set in the electroplating facility shown in Fig. 6. A plan view of a stirring paddle (stirring tool); an eighth drawing is a sectional view taken along line AA of Fig. 7; and Fig. 9A shows a relationship between time and a voltage applied between the anode electrode and the substrate, Relationship according to this An embodiment of the invention is observed by performing electroplating; 323759 33 201229328 Figure 9B shows the relationship between time and current flowing between the anode electrode and the substrate 'this relationship is observed by performing electroplating according to an embodiment of the present invention Figure 10A shows the relationship between the time and the voltage applied between the anode electrode and the substrate. This relationship is observed by electroplating the surface of the substrate shown in Fig. 3 under controlled current; Figure 10B The relationship between the display time and the current flowing between the anode electrode and the substrate is observed. This relationship is observed by performing electroplating on the surface of the substrate shown in FIG. 3 under a controlled current; FIG. 11A shows the time And a relationship between a voltage applied between the anode electrode and the substrate, the relationship being observed by performing electroplating according to another embodiment of the present invention; the 11th phase diagram showing time and flowing between the anode electrode and the substrate The relationship between the currents, which is observed by performing electroplating according to another embodiment of the present invention; And a relationship between a voltage applied between the anode electrode and the substrate, the relationship being observed by performing electroplating on the surface of the substrate shown in FIG. 2 under a controlled current; the 12th panel showing time and flowing to the anode The relationship between the current between the electrode and the substrate' is observed by electroplating the surface of the substrate shown in Fig. 2 under controlled current; Fig. 13 shows examples 1 and 2 and comparative examples. 1 and the relationship between the time observed in Comparative Example 2 and the voltage applied between the anode electrode and the substrate sample; 323759 34 201229328 Figure 14 shows the results from Example 1 and Example 2 and Comparative Example 1 and Comparative Example 2 The relationship between the observed time and the current flowing between the anode electrode and the substrate sample; FIG. 15 is a mesoporous hole in the substrate sample in the interpolating example 1 in which the electric money metal (copper) is filled into the medium. Figure 16 is a diagram of the layer after the via hole; Figure 16 is a diagram of the via hole of the substrate sample in Example 2 after filling the plated metal (copper) into the via hole; The through-hole of the substrate sample in Example 1 is depicted in Figure 18. The comparison example_mine·metal (steel) filling channel [main component symbol description] The pattern after filling the electric (four) genus (copper) into the via hole ·, and Figure 18 value te: a . . _ . ^ . 10 14 18 22 112 116 121 124 127 160 162 166 base barrier layer plating metal steel seed layer separator plate plating space main control panel cleaning / drying The pattern of the pre-treatment groove substrate support substrate attachment/separation stage activation processing device after the through hole is shocked. 12 vias 16 copper seed layer 20 auxiliary metal layer 110 facility frame 114 clean space 120 load / unload portion 122 aligner 126 pre-processing device 128 first handling machine ^ 160a outward protruding portion 164 storage 168a First water cleaning machine 323759 35 201229328 168b Second water cleaning device 170 Electroplating facility 172 Air blowing device 174a Second handling robot arm 174b Second handling robot arm 176 Road 178 Body 180 Arm 182 Substrate holder holding portion 183 Activation treatment tank 184a Water cleaning tank 184b Water cleaning tank 186 Plating tank 186a Plating solution supply inlet 200 Overflow tank 202 Pump 204 Circulation line 206 Temperature unit 208 Filter 210 Base plate 212 Lower plating solution distribution chamber 214 Upper substrate processing chamber 216 Shield 220 Anode electrode 222 Anode electrode holder 224 Adjustment plate 226 Cylindrical portion 228 Rectangular rim portion 232 Stirring paddle 232a Slot 232b Band portion 250 Plating power supply 252 Control section 300 Substrate sample 302 Via through hole 304 Plating Metal d diameter h depth H lateral length Li vertical length l2 vertical length Degree Q plating solution t thickness V cavity w substrate 36 323759

Claims (1)

201229328 七、申請專利範圍： 1· 一種電鍍方法，包括： 製備基板，該基板的表面中形成有介層通孔； 將該基板浸潰於預處理溶液中，以實施該基板的 預處理； j 將該基板浸潰於電鍍溶液中，且未施加電屋於該 基板與陽極電極之間，該陽極電極係配置於該基板的 對稭此以該電鑛溶液取代該介層通孔中的該預處 理 >谷液； 實施該基板的第-步驟電鍵，同時’將施加於古亥 基板與該陽極電極之該電壓控制為等於或高於電壓， X 使得適於將電鍍金屬填充進入該介層通孔之電 k穩疋地流動於該基板與該陽極電極之間；以及 實施該基板的第二步驟電鑛，同時，’ 基板與該陽極電極之間的該電流控制在適於ς該電^ 金屬填充進入該介層通孔。 2. 如申請專利範圍第】項所述之電錢方法， 板係浸漬於電鍍溶液中㈣10秒至60Γ 電壓於該基板與該陽極電極之間。 禾知加 3. 如申請專利範園第！項所述之電鑛方法，並中， 一步驟電鍍係實施持續1秒至H)分鐘。 以第 4. 如申請專利範圍第！項所述之電錢方法，其中 二步驟電鍍係經實施吏 〇Λ 亥基板與該陽— 極之間的該電流以步階形式變化。 323759 1 201229328 5. 汝申π專利範圍第1項所述之電鑛方法，其中，該電 鍍金屬係鋼，且非銅金屬係曝露於該介層通孔的至少 部份表面上。 6. 如申請專利範圍第5項所述之電錢方法 鋼金屬係釘或鈷、或兩者的合金。 其中，該非 323759 2201229328 VII. Patent application scope: 1. A plating method comprising: preparing a substrate, wherein a via hole is formed in a surface of the substrate; and dipping the substrate into the pretreatment solution to perform pretreatment of the substrate; The substrate is immersed in the plating solution, and no electricity is applied between the substrate and the anode electrode, and the anode electrode is disposed on the substrate, and the electroplating solution is substituted for the via hole in the via hole. Pretreatment > Valley Liquid; performing the first step of the substrate while simultaneously controlling the voltage applied to the Guhai substrate and the anode electrode to be equal to or higher than the voltage, X making it suitable for filling the plating metal into the dielectric a layer of via holes electrically flowing between the substrate and the anode electrode; and a second step of electroforming the substrate, while the current between the substrate and the anode electrode is adapted to The metal is filled into the via of the via. 2. The method of claim 1, wherein the plate is immersed in the plating solution (iv) between 10 seconds and 60 Torr between the substrate and the anode electrode. He Zhijia 3. If you apply for a patent Fanyuan! In the electromineral method described, the one-step electroplating system is carried out for 1 second to H) minutes. Take the fourth paragraph, such as the scope of patent application! The method of claim 1 wherein the two-step electroplating is performed in a stepwise manner by the current between the substrate and the anode. The electric ore method according to the first aspect of the invention, wherein the electroplated metal-based steel is exposed to at least a part of a surface of the via hole of the via. 6. The method of claim 5, wherein the steel metal nail or cobalt, or an alloy of the two. Among them, the non-323759 2
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