TW200524267A - Hyper-ring oscillator - Google Patents

Abstract

A ring oscillator has a first logic circuit forming a first loop. The ring oscillator also has a second logic circuit forming a second loop, such that phase interpolation occurs at a node common to the first and second loops. The phase interpolation results in an output signal with a high frequency.

Description

200524267 IX. Description of the Invention: This application claims the priority of Korean Patent Application No. P2003-64241 filed on September 16, 2003, which is incorporated herein by reference. [Technical Field to which the Invention belongs] The present invention relates to a ring oscillator and related methods. [Prior art] Electric materials that require an internal clock can use a clock generator to generate a periodic signal as a clock. Alternatively, a counter or other component can be used to divide the frequency ' to convert the periodic signal generated by the clock generator into a slower clock. In another application, the clock generator may be used as a phase locked loop of the clock generator of a memory device. [Summary of the Invention] For example, the dynamic memory needs to update signals to ensure that the leakage of electricity in the memory units will not cause the memory units to lose pot data. The clock generator can be used to generate a periodic update signal. In some examples, the cycle signal can be fed to a counter, and after a preset number of counts, the counter can output an update signal. One of the circuits that can be used to generate a 6-h period signal is a ring oscillator. U.S. Patent No. 6,100,763, which was filed on April 4, 2000 as an example, and the phase ratio of the work, which was filed on the 1M5 date of the year 94876.doc 1

Examples of these vibrator types can be found in No. 1. Generally speaking, J 2 says that these methods are all combined in the circuit. &# '—When a single signal consisting of an odd number of inverters is returned to the input of the loop, the output signal of 200524267 will be reversed, which will produce a high-pass signal. A signal that changes between a signal and a low signal. This results in a periodic signal with a well-defined and stable cycle. By increasing the power, the period of the output signal can be reduced, and the frequency can be increased. This method can be used with adjustable frequency. Another way is in r A Novel, published by S.J. Lee in February 1997 in IEEE J0urnai 〇f SolidState Circuits, pages 289-291.

High-Speed Ring Oscillator for Multiphase Clock Generation using Negative Skewed Delay Scheme. " Lee uses a skew delay technique to apply signals of different phases to produce a polyphase signal. However, the signal generated by this method is not significantly faster than the signal generated by the prior art. With the evolution of memory and other technologies, tasks such as updating signals, system clocks, and phase-locked loops need to oscillate clock signals more quickly. The above solutions, as well as other solutions provided by the current technology, are not high enough to match the novel circuit technology. [Embodiment] FIG. 1 is a schematic diagram of a prior art embodiment of a ring oscillator. It can be seen from the figure that the output Vosc will be sent back to the inverter η, so that the signal will have a two-state thixotropy between the high and low levels. The period of this signal corresponds to the delay caused by the special inverter to process the Xun #. The <RTIgt; < / RTI > shown in Fig. 1 is an alternative embodiment of a prior art ring oscillator, which uses a differential amplifier instead of an inverter. Regardless of their design (for example, using an inverter or a differential amplifier), these components will be referred to as a reverse stage. Each specific embodiment in the figures and ^ has three reverse stages. The total period of the bi-state thixotropy between high signal and low signal 94876.doc 200524267 depends on the number of stages and the delay at each stage. Pay attention to the nodes A, in any of the graphs la and lb. We can determine the number of input signals and output signals at each node. Figure 2 is a node analysis diagram, which shows that each node has an input signal and an output signal. Phase mixing between different signals can be used to generate a chirp with a period of far less ring vibration. However, in the specific embodiment of the prior art, there is no phase mixing at any of these nodes, and the period of the output signal is fixed by the number of inverse stages between the input signal and the output signal. FIG. 3 is a timing diagram corresponding to the prior art specific embodiment of these oscillators. When the width / length of each inverter is the same, the delay time D between the falling edge of the input signal and the rising edge of the output signal between nodes A and B will be substantially equal to the rising edge of the input signal between nodes. The delay time De between the falling edge of the output signal 3 and the delay time 4 between these nodes is almost the same. This produces a periodic output signal with the limitations discussed above. FIG. 4 is a specific embodiment of the present invention, which performs phase mixing on the output signal to generate a signal with a shorter period and a higher frequency, but does not significantly increase the complexity of the circuit. FIG. 5 is an alternative specific embodiment of the present invention. The specific embodiment in FIG. 4 uses an inverter as a reverse stage, and the specific embodiment in FIG. 5 uses a differential amplifier as a reverse stage. The special components as the reverse stage are not limited to these examples, but are common and can explain the components of the present invention more clearly. 94876.doc 200524267 This circuit has two circuit loops, the first circuit loop is the inverters η, 12 and 13 ′ and the second circuit loop is the inverter ^. The signals from and two loops are mixed at node A. At this node, the output signal originating from node C has passed through two reverse stages of the second loop, and only passed through one reverse stage of the first loop. Due to the 2 series of the difference between these signals at node A, phase mixing will occur. As used herein, phase mixing means the mixing of signals of at least two different phases at the same node. FIG. 6 is a node analysis of the specific embodiments of FIGS. 4 and 5. It can be seen from the figure that nodes B and D each have one input and one output. Node B will output the number to node C and receive an input signal from node eight. Node 0 will receive-output signals from node C and provide-input signals to node a. Different from the previous technology, node C will provide two output signals, one for node A and one for node D, and it will receive an input signal from node B. Also different from the previous technology, node A will receive two input signals, one

One from Lang point D and one from node C. Light B recognizes I 丨 U + that is point L and will output an output signal to node B. Receiving two input signals with different phases will cause phase mixing at node A: The generated signal timing diagram is shown in Figure ~. The delay time D between the falling edge of the input 4 slogan between the nodes and the rising edge of the output j is equal to the delay time between the rising edge of the input signal and the falling edge of the output signal between nodes B and C. The delay time d between the rise times is smaller than the delay time because the input signals Aι and A " are interpolated at this node. The signal A 'is a reverse signal of the signal D passing through the inverter 15, and the signal of "" is a reverse signal of the signal C passing through the inverter n. When using at least two loops 94876.doc 200524267 to design a ring oscillator, different values of each node can be used to control the delay time between nodes. Observing the timing diagram of the signals at each node shown in Figure 7b makes it easier to understand the results of the node analysis. When the signal from node C is at a high level, the signal at node A will go to a low level through the first loop after a delay. The signal at node D is also at a low level. The signal at node A goes high via inverter 15. The interpolation signal at node A is shown on the last line. It can be seen between the two dashed lines that the period of the interpolation signal is short. Figure 8a is an alternative embodiment of the invention. The graph center has three loops. As in the embodiment of Fig. 6, the first circuit loop has an odd number of reverse stages, and the second circuit loop has an even number of reverse stages. The total generated reverse series should usually be an odd number in order to generate the necessary vibration signal. In the embodiment shown in the figure, a third loop with an odd number of reverse stages is added. In this specific embodiment, the first circuit loop is composed of three reverse stages n, 12 and 13. The second circuit loop is composed of four inverters 14,15 ,. With 13. The third circuit loop is composed of three reverse stages 13, 14 and 16 between nodes B, c, D and B. In this specific embodiment, a phase interpolation phenomenon occurs at nodes a and B. At node A, the two input signals are from inverter II and inverter 15. The node sighs that these two input signals come from the inverter 12 and the inverter 10. The resulting output pulse frequency will be faster than before. It can be seen from the analysis of the node in Fig. 8b that both nodes will receive two input signals. Similarly, the timing diagram in Figure 8c shows the signal generated by the interpolation at the two nodes. The rise time and fall time of the oscillating pulses at each of nodes eight and 3 are faster than one of the oscillating pulses at nodes C and D. The reason why the frequency of the output pulse is faster is because of the short delay between the two nodes. The resulting output signal will be faster than before. The system shown in Fig. 9a is another embodiment, which uses the phase interpolation phenomenon at all nodes. In any of the specific embodiments shown herein, the frequency of the output pulse is the fastest. Unless high-speed pulses are not needed, phase mixing at all / = points seems to be the most satisfactory way for us. The design trade-off result between speed and circuit ^ will make interpolation below all nodes a more satisfactory way, as long as the frequency of the output pulses generated by the interpolation result is sufficient to meet the needs of the system . However, in general, the input signal with the highest frequency will be considered a more satisfactory result. The node analysis of the circuit of Figure 9a is shown in the figure. It can be seen from the figure that there are two points in the two jacks that will receive two input signals and generate two output signals. Phase interpolation or mixing occurs in the two input signals at each node. These output signals are usually not designed as two actual outputs. These output signals are usually the earlier output signals that are intended to be sent to two lines. For example, the output of inverter 114 is an output signal ' which will only be provided to the inputs of inverters 115 and 118, so it will be referred to as two output signals. At this point, phase mixing consists of two signals at a particular node. In the specific embodiment of FIG. 1 () a, the phase mixing is caused by four input signals. For example, the 'node has four input signals received at each of the four inverters at 94876.doc 200524267 125, 13 0, 132, and 133. The four input signals are used in the interpolation phenomenon, and the four input signals are phase-mixed to generate a high-frequency output signal. In this way, phase mixing can produce faster output signals that can be used in many different applications. For example, a memory system may use the high-frequency output signal as a phase-locked loop in a clock generator, so as to generate the internal clock of an output buffer or renew the memory or perform Clock addressing or data access to this memory. An example of such a system is shown in Figure 丨 丨. The clock generator 10 has a pulse generator 12 and a phase-locked loop 14. The phase-locked loop uses a ring oscillator 16 according to any specific embodiment of the present invention above. FIG. 12 shows an alternative embodiment of the system. In FIG. 12, the ring oscillator is made of DRAM devices 19a and 19b, which are part of the internal memory module 20, as ring oscillators 16a and 16b. The memory module 20 may include a plurality of memory devices 19a and 19b. In this specific embodiment, the ρχ is located in a memory device for exposing the §memory module 20. A DLL (Delay Locked Loop) located at the memory device may also contain a framed oscillator according to the present invention. The generated clock signal can then be sent to the memory controller 18 and the memory module 20, and the generated PLL (or dll) clock signal can be sent to the output at the memory device buffer. Although the principle of the specific embodiment of the present invention has been illustrated and described, those skilled in the art will readily understand that the configuration and details of the present invention can be modified without departing from these principles. This article claims all modifications that fall within the spirit and scope of the scope of the accompanying patent application. 94876.doc -11-200524267 [Brief description of the drawings] The foregoing and other objects, features, and advantages of the present invention will be easily understood from the detailed description of the specific embodiments with reference to the following drawings. Figures 1a-b show a prior art embodiment of a ring oscillator. Fig. 2 is a relationship diagram of input / output signals at the nodes of the prior art embodiment of the ring oscillator. FIG. 3 is a timing diagram of a prior art embodiment of a ring oscillator. FIG. 4 is a schematic diagram of a specific embodiment of a ring oscillator. FIG. 5 is a schematic diagram of an alternative embodiment of a ring oscillator. Fig. 6 is a relationship diagram of input / output signals at the nodes of the prior art embodiment of the ring oscillator. Figures 7a-7b are timing diagrams of the signals at the nodes of the ring oscillator. 8a-c are schematic diagrams of alternative embodiments of a ring oscillator, an input / output signal relationship diagram, and a timing diagram. Figures 9a and 9b are alternative embodiments of a ring oscillator and a corresponding input / output signal relationship diagram. Figures 10a and 9b are alternative embodiments of a ring oscillator and a corresponding input / output signal relationship diagram. Fig. 11 is a schematic diagram of a specific embodiment of a system having a clock generator, which uses a -ring oscillator as a -phase locked loop. Fig. 12 is a schematic diagram of an alternative embodiment of a system having a ring oscillator. [Description of Symbols of Main Components] II Inverter 94876.doc] 2 · 200524267 12 Inverter 13 Inverter 14 Inverter 15 Inverter 16 Inverter 110 Inverter 111 Inverter 112 Inverter 113 Inverter 114 Inverter 115 Inverter 116 Inverter 117 Inverter 118 Inverter 119 Inverter 120 Inverter 121 Inverter 122 Inverter 123 Inverter 124 Inverter 125 Inverter 126 Inverter 127 Inverter 128 Inverter

94876.doc -13- 200524267 129 Inverter 130 Inverter 131 Inverter 132 Inverter 133 Inverter 134 Inverter DAI Differential amplifier DA2 Differential amplifier DA3 Differential amplifier DA4 Differential amplifier DA5 Differential Amplifier 10 Clock generator 12 Pulse generator 14 Phase locked loop 16 Ring oscillator 16a Ring oscillator 16b Ring oscillator 18 Memory controller 19a DRAM device 19b DRAM device 20 Memory module

94876.doc 14

Claims (1)

200524267 X. Patent application scope · A ring vibrator including: two first logic circuits' for forming a first loop; and a circuit for forming a second loop, so that Phase interpolation occurs at the common nodes of the second and second loops. As a ring oscillator, the first logic circuit further includes at least one circuit element shared with the first logic circuit. 3. If the ring oscillator of claim 2 is specified, the circuit element is composed of an inverter or a differential amplifier. In the ring oscillator of Month Seeker 1, the first logic circuit further includes an odd number of reverse stages, and the second logic circuit further includes an even number of reverse stages. 5. If the ring oscillator of claim 4 is specified, the inverter stages further include a plurality of inverters. 6 · If the ring oscillator of claim 4 is specified, the inverting stages further include a plurality of difference amplifiers. 7. A ring oscillator comprising: a first logic circuit for forming a first loop with a first odd number of reverse stages; and a first logic circuit for forming a second loop so that Phase interpolation will occur at the first common nodes of the first and second loops; one or two logic circuits 'used to form a first loop with a second odd number of reverse stages' cause Phase interpolation will occur at the second nodes shared by the second and second loops. 94876.doc 200524267 8. A ring oscillator similar to claim 7 includes at least two loops. The loops are configured to interpolate at least three different nodes. 9. The ring oscillator of claim 7 including a phase locked loop. ίο · —a ring oscillator, which includes the first and second circuit loops; and a node common to the first and second circuit loops, where phase interpolation occurs at the node, The first oscillating signal is used for generating a high frequency, and its frequency is higher than the oscillating signal provided by the first loop alone. 11. The ring oscillator of claim 10, further comprising a third loop and a second node where phase interpolation occurs, the oscillator generating an oscillation signal having a frequency higher than the first oscillation signal. 12. The ring oscillator of claim 10, further comprising at least two additional circuit loops, the oscillator generating an oscillator signal having a frequency higher than the first oscillation signal. 13. A ring oscillator comprising: a first node located at a common output of the first and second circuit loops; a second node located at a reverse stage in front of the first node; A third node 'is located at a reverse level behind the first node; and a fourth node' is located at least two circuit loops in common, causing phase interpolation to occur at the fourth Lang point Make up. 14. The ring oscillator of claim 13, the first circuit loop further includes at least one circuit element shared with the 94876.doc -2-200524267 second circuit loop. 15. The ring oscillator of claim 13, further comprising a third circuit loop configured to make the second node common to the second and third circuit loops' and to be at the node Phase interpolation occurs everywhere. 16. The ring vibrator of claim 13, further comprising at least two external circuit loops, which are configured so that at least three nodes are common to at least two such loops, and Wait for phase interpolation of each node of the three nodes. 17. A method, comprising: generating a puppet at a first node-generating a first output signal at the first node at the -th node; interpolating at the first node, and ranking: : The second round of output signals; the first "recognition and the second phase, used to generate--output signal two ::. 'The output frequency of the output signal is higher than the method described in clause 18. If the method of claim 17, this method It further includes that the second node generates a third output signal with a third phase, and the third output signal and the first one are at least C out of the number of the first output signal-that is, the point Interpolation is used to generate a first-output signal, the frequency of the round-out signal ^ the first-first-generation input I9. A system that includes ... " Younger generation of the round-out signal. Two devices are used to generate A plurality of commands and address signals; a plurality of commands and address signals of the physical control; 94876.doc 200524267 each such memory device for storing data includes: a plurality of memories for storing the data Body unit; a ring oscillator that operates against a phase-locked loop, The ring oscillator includes: a first logic circuit to form a first loop; and a first logic circuit to form a second loop, so that a common node at the common nodes of the first and second loop Phenomenon of phase interpolation occurs. 20. As in the system of claim 19, the memory device further includes one selected from the group consisting of: static random access memory, dynamic random access memory, And read-only memory. 21 · If the system seeks the item 9 explicitly, the first logic circuit further includes an odd number of reverse stages. 22. If the system of claim 19 'the second logic circuit further includes an even number of steps Reverse stage. 23. If the system of claim 21, the reverse stages further include a plurality of inverters. 24. If the system of claim 21, the reverse stages further include a plurality of differential amplifiers. 25. If the system of item 22 is requested, the inversion stages further include a plurality of inverters. 26. If the system of item 22 is requested, the 5 go-to-go, warehouse stop a, the Han-Xun stage further includes a plurality of differential amplifiers 2 7 · -A system comprising:-a memory controller 'for generating a plurality of command and address signals, 94876.doc 200524267 and receiving a first clock signal;-a memory module comprising a plurality of memory devices And receive the plurality of commands and address signals from the memory controller; a clock generator for generating the first clock signal and transmitting the first clock signal to the memory control The clock generator includes a clock source and a phase-locked loop including a ring oscillator; the ring oscillator includes: a first logic circuit for forming a first loop; and a second logic circuit , Used to form a second loop, causing phase interpolation to occur at the common node of the first and second loops. 28. The system of claim 27, wherein the clock generator is mounted directly on the motherboard. 94876.doc