JP2002184864A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a semiconductor device operating in synchronism with an external clock signal that current consumption must be reduced under each operating state but it is difficult to suppress current consumption while satisfying the operational stability and high speed operation under each operating state. SOLUTION: A circuit for generating an internal clock signal based on an external clock signal is activated for a specified period when a clock synchronization circuit is inactive.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit that operates based on an external clock signal.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been developed in response to the development of information devices. In particular, small-size, low power consumption, low voltage High-speed operation is required.
However, it is not easy to satisfy the two requirements of high-speed operation and low consumption, and various technical developments are being made.
In particular, dynamic random access memory (hereinafter DRAM)
), Various technical developments have been made,
In recent years, synchronous DRAMs (hereinafter referred to as SDRAMs) that can operate in synchronization with an external high-speed clock signal having a frequency exceeding 100 MHz have been developed.

[0003] Furthermore, instead of data input / output corresponding to the rising edge of the clock signal, a DDR (Double Data Rate) SDRAM for inputting / outputting data at both the rising edge and the falling edge of the clock signal has been developed. Has also been.

In order to realize a DDR SDRAM, it is necessary to suppress a timing shift due to an external factor such as a change in a temperature of a semiconductor device, a power supply voltage, and a process variation.
In particular, it is important to suppress the occurrence of jitter and frequency fluctuations for internal clock signals used inside the semiconductor device in synchronization with an external clock signal.
ed Loop) circuit has been introduced. The DLL circuit adjusts the delay amount of the internal clock signal, thereby making the time difference from the external clock signal constant and enabling data output at the rising and falling edges of the high-speed clock signal.

[0005]

As described above, the DDR SRAM has been described as an example. However, although high-speed technology is advanced, in order to support portable devices, etc., it operates not only in SDRAM but also in synchronization with an external clock signal. The current consumption must be reduced in each operating state of the semiconductor device. However, in each operation state, it is difficult to suppress current consumption in order to satisfy operation stability and high speed operation. In particular, in DDR SDRAM in particular, although there are a plurality of operating states, there is a strong demand in recent years for a reduction in current consumption in a power down mode in which a command is not input by a combination of external control signals. But,
Even in the power-down mode, the internal voltage-down circuit, substrate bias circuit, word Wire boost circuit,
Various circuits such as a refresh circuit and a DLL circuit perform a certain operation. For this reason, it has been difficult to suppress current consumption in the power down mode. However, considering the compatibility with portable devices and the like, in DDR SDRAM and the like, suppressing the current consumption in the power down mode has been an important issue.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problem, and can reduce current consumption while satisfying conditions such as operation stability in a specific operation state. A semiconductor device is provided.
Furthermore, in power down mode such as DDR SDRAM,
An object of the present invention is to provide a semiconductor device capable of reducing current consumption while satisfying conditions such as operation stability.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a clock generation circuit for generating an internal clock signal based on an external clock signal; and a clock synchronization circuit operating in synchronization with the internal clock signal. And a control circuit for activating the clock generation circuit for a specific period when the clock synchronization circuit is in an inactive state. Second
In the semiconductor device according to the invention, the control circuit uses a signal generated based on a signal input from the outside as an input signal,
A control signal for activating or deactivating the clock generation circuit in accordance with an input signal is generated. In the semiconductor device according to the third invention, when the clock synchronization circuit is in an inactive state, a control signal for activating the clock generation circuit is generated based on a pulse signal input from the outside. In a semiconductor device according to a fourth aspect, the control circuit includes:
A first pulse signal generated based on a pulse signal input from the outside is used as an input signal, and a second pulse signal obtained by delaying the rise or fall of the first pulse signal activates a clock generation circuit. This is a control signal.

In the semiconductor device according to a fifth aspect of the present invention, the start of the second pulse signal is based on a change in the first pulse signal, and the end of the second pulse signal is changed to the first pulse signal. This is based on the fact that the third pulse signal generated in the control circuit reaches a certain number of pulses. In the semiconductor device according to the sixth aspect, the start of the second pulse signal is based on the fact that the third pulse signal generated in the control circuit based on the first pulse signal reaches the first pulse number. And the end of the second pulse signal is based on the third pulse reaching a second pulse number greater than the first pulse number. In the semiconductor device according to the seventh aspect, when the third pulse signal reaches a third pulse number greater than the second pulse number, the pulse number of the third pulse signal is reset, and the third pulse signal is returned again. Is increased, and the second pulse signal is periodically generated by reaching the first and second pulse numbers. In a semiconductor device according to an eighth aspect, the control circuit includes a ring oscillator that generates a third pulse signal, and a counter that counts the number of pulses of the third pulse signal.

A ninth aspect of the present invention is a semiconductor device, wherein the control circuit includes a ring oscillator for generating a third pulse signal;
A counter for counting the number of pulses of the third pulse signal, and a signal for instructing the start of the second pulse signal when the counter reaches the first pulse number, and outputting a second pulse when the counter reaches the second pulse number. A logic circuit that outputs a signal indicating the end of the signal. In the semiconductor device according to a tenth aspect, the control circuit further receives another internal clock signal generated based on the external clock signal, and the second pulse signal starts at the first pulse signal. The change is based on the change, and the end of the second pulse signal is based on the other internal clock signal reaching a certain number of pulses. In a semiconductor device according to an eleventh aspect, the control circuit includes a counter that counts the number of pulses of another internal clock signal. In a semiconductor device according to a twelfth aspect, the control circuit includes a shift register controlled by another internal clock signal generated based on an external clock signal, and the start of the second pulse signal is
The end of the second pulse signal is based on the change in the first pulse signal, and the end of the second pulse signal is based on the first pulse signal passed through the shift register.

In the semiconductor device according to a thirteenth aspect, the clock generation circuit includes a DLL (Delay Locked Loop) circuit. In a semiconductor device according to a fourteenth aspect, the clock generation circuit includes a DLL (Delay Locked Loop) circuit. In a semiconductor device according to a fifteenth aspect, an input signal of a DLL circuit is a fixed signal before and after a clock generation circuit is activated for a specific period. In a semiconductor device according to a sixteenth aspect, an input signal of a DLL circuit is a fixed signal before and after a clock generation circuit is activated for a specific period.

In a semiconductor device according to a seventeenth aspect, the semiconductor device includes a dynamic random access memory, and the clock synchronization circuit includes a read data output circuit of the dynamic random access memory. Eighteenth
In the semiconductor device according to the present invention, the input signal generated based on a signal input from the outside in the control circuit is a clock enable signal for instructing input of an external signal for controlling the operation of the dynamic random access memory. In the semiconductor device according to the nineteenth aspect, the inactive state of the read data output circuit is a power down mode of the dynamic random access memory. In the semiconductor device according to the twentieth aspect, the specific period in which the clock generation circuit is activated includes a time when the dynamic random access memory is auto-refreshed.

In a semiconductor device according to a twenty-first aspect, an input signal generated based on an externally input signal in a control circuit is an auto-refresh instruction signal. In a semiconductor device according to a twenty-second aspect, an input signal generated based on a signal input from outside in a control circuit includes:
This signal activates the read operation. In the semiconductor device according to a twenty-third aspect, the specific period for activating the clock generation circuit is set to be 10% or less of the power down mode period.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1. FIG. 1 is a schematic diagram showing the overall configuration of a 128 Mbit DDR SDRAM of Embodiment 1. In FIG. 1, reference numeral 1 denotes a DDR SDRAM which is a semiconductor device.
A memory array unit 2 having a plurality of banks each having a fixed number of memory cells arranged in an array as a unit, and receiving complementary external clock signals CLKe and / CLKe from outside which determine the operation timing of the semiconductor device. An internal clock signal CLKi which is a basic clock signal for determining an internal operation timing of the semiconductor device, and a DLL output signal CLKd1 which controls one of the internal clock signals by controlling the timing of the output data during the read operation of the DDR SDRAM 1. And a clock generator 3 for generating CLKd2.

Further, a clock enable signal CKE for instructing the input of a control signal to the DDR SDRAM, a row address strobe signal / RAS as one of the control signals, a column address strobe signal / CAS as one of the control signals, One of these signals is a write enable signal / WE, a control signal / RAS, / CAS, and a chip select signal / CS that identifies whether the command input that is a combination of / WE is valid, and an external input The reference voltage Vref used to compare the L / H level of the signal is captured, and the internal clock enable signal CK
A control signal input buffer circuit 5 for generating an internal control signal such as Ei.

Further, an address signal Ai (i = 0 to 11), a bank address signal BAi (i = 0 to 1), and a reference voltage Vref
And an input / output data signal DQi (i = 0 to 15) and a data strobe signal DQSi (i = 0, 1) for controlling the input / output data signal input timing. ), The input / output buffer circuit 7 that outputs the input / output data signal DQi (i = 0 to 15) in synchronization with the DLL output signals CLKd1 and CLKd2 from the clock generator 3, and the control signal input buffer circuit 5 A command decode / internal control circuit for decoding an internal control signal to determine a designated operation mode and generating an internal operation mode instruction signal in synchronization with the internal clock signal CLKi;
Further, it receives an internal address signal from address input buffer circuit 6 and generates an internal row / column address signal in accordance with a control signal from command decode / internal control circuit 8, and writes write data as input data. A data bus 10 for transferring data from the input / output buffer 7 to the memory array unit 2 and transferring read data as output data from the memory array unit 2 to the input / output buffer 7, and an internal clock enable from the control input signal buffer circuit 5; And a DLL control circuit 12 that receives the signal CKEi and outputs a DLL control signal DLLA for controlling activation of the clock generator 3.

FIG. 2 is a diagram showing a configuration of the buffer section 5a included in the control signal input buffer circuit 5 shown in FIG. The buffer unit 5a includes external control signals / RAS, / CAS,
Each is provided corresponding to / WE and / CS. Here, these external control signals are EXT. The buffer 5a is controlled by an internal clock enable signal CKEi generated according to the clock enable signal CKE, compares the external control signal EXT with the reference voltage Vref, and according to the comparison result, the internal control signals INT and / INT
Generate

In FIG. 2, an external control signal EXT is input to the gate of the NMOS transistor NQ1, and a reference voltage Vref is input to the gate of the NMOS transistor NQ2. Further, the gate of the PMOS transistor PQ2 is connected to the drain of the PMOS transistor PQ1 and the drain of the NMOS transistor NQ1, and the node N
5a is formed, and the gate of the PMOS transistor PQ1 is connected to the drain of the PMOS transistor PQ2 and the drain of the NMOS transistor NQ2 to form a node N5b. Node N5b
Outputs an internal control signal / INT via an inverter INV1, and outputs an internal signal INT via an inverter INV2. An NMOS transistor NQ3 is provided between the sources of the NMOS transistors NQ1 and NQ2 and the ground line GND, and a PMOS transistor PQ3 is provided between the node N5b and the power supply voltage line Vcc.
And an internal clock enable signal CKEi is input to each gate. Note that, specifically, an external control signal / C input to the control input signal buffer circuit 5
Generates / CSi, / RASi, / CASi, / WEi corresponding to internal control signal INT and CSi, RASi, CASi, WEi corresponding to internal control signal / INT according to S, / RAS, / CAS, / WE Is done.

Next, an outline of the operation of the buffer 5a will be described. When the internal clock enable signal CKEi is at the H level, a current flows through the NMOS transistor NQ3, and the internal control signals INT and / INT are changed by an external control signal EXT. When the internal clock enable signal CKEi is at the L level, no current flows through the NMOS transistor NQ3,
The transistor PQ3 causes the node N5b to go high, and the internal control signals INT and / INT go high and low, respectively. As described above, the buffer 5a of the control input signal buffer circuit 5
However, the address input buffer circuit 6 is also provided with a similar buffer 5a.

FIG. 3 is a diagram showing a configuration of the buffer 5b corresponding to the clock enable signal CKE included in the control signal input buffer circuit 5 shown in FIG. The clock enable signal CKE and the activation signal / CE1 generated inside the DDR SDRAM1 are input to the NOR circuit NOR1, and the inverter INV1
To INV3 to generate an internal clock enable signal CKEi and inverters INV1 and INV2 to generate an internal clock enable signal / CKEi.

In the command decode / internal control circuit 8 shown in FIG. 1, a combination of control signals serving as a command is input to the control input signal buffer circuit 5 when the external clock signal CLKe rises, and the operation specified according to this input is performed. Generate a mode instruction signal. For example, when a row access instruction command for instructing row selection is input to the control input signal buffer 5, the command decode / internal control circuit 8
Outputs a row access activation signal ROWA, and outputs a column access activation signal COLA when a column access instruction command instructing column selection is input. When the clock enable signal CKE is at the H level and the external clock signal CLKe rises, the control signals / CAS and / CS are set to the low level.
When the level and the control signals / RAS and / WE are set to H level,
The read operation activation signal READ for activating the read operation is output. When / WE is at L level and other signals are the same as described above, a write operation activation signal WRITE for activating a write operation is output.

Further, in a state where the H level is input as the clock enable signal CKE, when the external clock signal CLKe rises, the control signals / RAS, / CAS and / CS are set to L level.
When the level and / WE are input to the H level, a refresh mode called an auto refresh is set, and a refresh operation is performed based on an address of a refresh address counter in the internal address generation circuit 9 described later. As shown in FIG. 4, the command decode / internal control circuit 8
Is the internal control signal CS from the control input signal buffer circuit 5.
i, RASi, CASi, / WEi as input and NAND circuit 8a
The inverter INV4 connected to the circuit 8a and the inverter INV4
, And an inverter INV5 connected to the NAND circuit 8b. The four internal control signals are input, and the internal clock signal is input to the clocked NAND circuit 8b.
The timing is controlled by CLKi, and an auto refresh instruction signal ARF for instructing auto refresh is output.

FIG. 5 schematically shows the structure of internal address generating circuit 9 shown in FIG. In FIG.
An internal address generating circuit 9 is an address latch that latches internal data Ai (i = 0 to 11) supplied from the address input buffer circuit 6 in accordance with activation signals ROWA and COLA from the command decode / internal control circuit 8 to address data. 9a and the bank address signal BAi supplied from the address input buffer circuit 6 are activated by the activation signals ROWA and COLA.
, A refresh address counter 9c for counting refresh addresses in response to an auto-refresh instruction signal ARF from the command decode / internal control circuit 8, and outputting an address signal, and a refresh address counter 9c. Or, it includes a multiplexer (MUX) 9d for selecting one of the row address signals of the address latch 9a. Similarly, a multiplexer (MUX) 9e for selecting all banks or one bank address signal corresponding to the bank address
And the multiplexers (MUX) 9d and 9e receive an auto-refresh instruction signal, which is controlled at the time of auto-refresh.

Address latch 9a latches a given address signal as a row address signal when row access activation signal ROWA is activated. Address latch 9a latches a given address signal as a column address signal when column access activation signal COLA is activated. Bank address latch 9b latches a given bank address signal when row access activation signal ROWA or column address activation signal COLA is activated.

The memory array unit 2 shown in FIG.
Upon receiving an operation mode instruction signal from the command decode / internal control circuit 8 and an address signal (including a bank address signal) from the internal address generation circuit 9, the specified operation is performed on the addressed bank.

FIG. 6 schematically shows the structure of the input / output buffer 7 shown in FIG. 6, an input / output buffer circuit 7 includes an input circuit 7a and an output circuit 7b for an input / output data signal DQi (i = 0 to 15), and an input section 7c for a data strobe signal DQiS which is a timing signal for the input / output signal DQi.
And an output unit 7d. The data strobe signal DQSi is input to the input section 7c as an input signal during a write operation, and outputs the internal data strobe signal DQSj to the input circuit 7a for the input / output data signal DQi. On the other hand, the output unit 7d outputs the DLL output signals CLKd1 and CLd from the clock generator 3 during the read operation.
Outputs a signal in synchronization with Kd2. The input circuit 7a receives a write operation activation signal from the command decode / internal control circuit 8.
Activated by WRITE. Write operation activation signal WRITE
Is an activation signal, the input / output data signal DQi is taken in by the input circuit 7a in synchronization with the internal data strobe signal DQSj, sent to the DB and / DB of the data bus 10 as a complementary signal, and Conveyed to. After that, data is written to the memory cell according to the address selected by the memory array unit 2. Also, the write operation activation signal WRITE
Is an inactivation signal, the input circuit 7a is in an inactive state, and no data is input. On the other hand, the output circuit 7b is activated by the read operation activation signal READ from the command decode / internal control circuit 8. Read operation activation signal
When READ is an activation signal, data is read from the memory cell at the address selected by the memory array unit 2, transmitted to the output circuit 7b from DB and / DB of the data bus 10, and synchronized with the DLL output signal CLKd1 or CLKd2. And output as an output data signal. Therefore, the output circuit 7b outputs the DLL output signal CLK.
It can be said that the clock synchronization circuit is synchronized with the clock signals d1 and CLKd2. When the read operation activation signal READ is an inactivation signal, the output circuit 7b is in an inactive state, and no data is output.

FIG. 7 schematically shows the structure of the DLL control circuit 12 shown in FIG. 7, an internal clock enable signal CKEi is input to a DLL control circuit 12, and a DLL control signal DLLA is output via inverters 12a and 12b.

FIG. 8 schematically shows the structure of the clock generator 3 shown in FIG. 8, a clock generator 3 is provided with a DLL control signal DLLA from a DLL control circuit 12.
And comparators 3a and 3b which compare external clock signals CLKe and / CLKe to generate DLL input signals DLLi1 and DLLi2, respectively, and external clock signals CLKe and / CLK
Comparator 3c that compares e and generates an internal clock signal CLKi
And a DLL circuit 3d that is one of the clock generation circuits that generates the DLL output signal CLKd1 from the DLL input signal DLLi1 and a DLL circuit 3e that generates the DLL output signal CLKd2 from the DLL input signal DLLi2. The comparators 3a to 3c differ from the circuit shown in FIG. 2 in that the inverter INV2 is not provided, but the other configurations are the same. For example, in the case of the comparator 3a, EXT is / CLKe, Vref is CLKe, / INT
Corresponds to DLLi1. However, only in 3c, the power supply voltage line Vcc is input instead of the internal clock enable signal CKEi.
Therefore, 3c operates constantly. The DLL circuit 3d outputs a DLL input signal.
The DLLi1 is delayed to generate a DLL output signal CLKd1 having a constant time difference from the DLL input signal DLLi1. Similarly, the DLL circuit 3e
The LL input signal DLLi2 is delayed to generate a DLL output signal CLKd2 having a constant time difference from the DLL input signal DLLi2.

FIG. 9 schematically shows the configuration of the DLL circuit 3d shown in FIG. The DLL circuit 3e is a DLL circuit.
It has the same configuration as 3d except that the input signal and the output signal are different, and the DLL circuit 3d will be described below as a representative. DLL circuit 3d
A control clock generation circuit 110, a phase comparator 120,
It includes a filter 130, a counter control circuit 140, a counter 150, a fine delay circuit 160, a coarse delay circuit 170, and a replica circuit 180. The control clock generation circuit 110 generates a clock for controlling the entire DLL circuit, and outputs the first control clock signal CNT1 to the counter control circuit 14 based on the DLL input signal DLLi1.
And outputs the second control clock signal CNT2 to the counter 150. The replica circuit 180 receives the external clock signals CLKe and / CLKe shown in FIG.
The delay amount is the same as the sum of the signal delay amount until the DLL output signal CLKd1 is input as the DLL input signal DLLi1 and the signal delay amount until the DLL output signal CLKd1 transmits the signal from the DLL circuit 3e to the output circuit 7b shown in FIG. The DLL circuit receives the DLL output signal CLKd1 and delays it to produce a replica delay signal C.
Outputs LKdd. The phase comparator 120 receives the DLL input signal DLL
The phase of i1 is compared with the phase of replica delay signal CLKdd, and comparison result signal CR is output to filter 130.

The filter 130 determines the fluctuation of the comparison result signal CR from the phase comparator 120 for a certain period in synchronization with the DLL input signal DLLi1, and if the comparison result signal CR is constant, the final comparison result signal The FCR is output to the counter control circuit 140. The counter control circuit 140 outputs a count instruction signal COUNT to the counter 150 based on the final comparison result signal FCR from the filter 130 in synchronization with the first control clock signal CNT1. The counter 150 counts up or down based on a count instruction signal COUNT from the counter control circuit 140 in synchronization with the second control clock signal CNT2. The count up is performed by the fine delay circuit 160 and the coarse delay circuit 17.
The delay amount at 0 is increased, and the countdown decreases the delay amount.

The counter 150 outputs count data a0 to a2 and a3 to a5 as count results to the fine delay circuit 160 and the coarse delay circuit 170, respectively.
Note that the least significant bit of the count data is a0 and the most significant bit is a5. Also, the count data is all a0 to a5
The case of L level is the minimum value of the count number, the delay amount in the fine delay circuit 160 and the coarse delay circuit 170 is the minimum, and the case where all of a0 to a5 are H level is the maximum value of the count number. The delay amount in the delay circuit 160 and the coarse delay circuit 170 is maximized.
The fine delay circuit 160 is a delay circuit whose delay amount is changed by a smaller amount than the coarse delay circuit 170. The fine delay circuit 160 selects a delay amount based on the count data a0 to a2, delays the DLL input signal DLLi1, and outputs a fine delay signal DLLf to the coarse delay circuit 170.

The course delay circuit 170 stores the count data
The delay amount is selected based on a3 to a5, and a fine delay signal
DLLf is delayed to output a DLL output signal CLKd1. The DLL output signal DLKd1 is an output signal of the DLL circuit 3d,
This is an input signal of the replica circuit 180. As described above, the DLL output signal CLKd1 is fed back to the replica circuit 180 to adjust the delay amount. For details of the DLL circuits 3d and 3e, refer to Japanese Patent Application No.
No. -160078.

Next, the operation of the DDR SDRAM 1 of the embodiment will be described. FIG. 10 is a diagram showing main operation timings of the DDR SDRAM of FIG. In FIG. 10, complementary external clock signals CLKe and / CLK are supplied from outside at regular intervals.
e has been entered. Note that, here, as shown in FIG. 10, from the intersection where the external clock signal CLKe changes from the L level to the H level and the external clock signal / CLKe changes from the H level to the L level, to the next similar intersection. Is one cycle. In the period A of FIG. 10, since the clock enable signal CKE is at the L level, the apparatus is in the power-down mode in which a command based on a combination of external control signals is not input. At this time, since the clock enable signal CKE is at the L level, the internal clock enable signal CKEi is also at the L level. Further, in response to this, a DLL control signal DL which is an output signal of the DLL control circuit 12 of FIG.
LA is also at L level. Therefore, the comparators 3a and 3b in the clock generator 3 in FIG. 8 are inactive, the DLL input signals DLLi1 and DLLi2 are fixed at L level, and the DLL circuit
3d and 3e are also inactive. This makes the DLL output signal C
LKd1 and CLKd2 are also at L level, and the external clock signal CL
Does not generate a clock signal corresponding to Ke and / CLKe.

Next, the operation from time B to time C in FIG. 10 will be described. In the time B + 1 cycle, the chip select signal / CS, the control signals / RAS, / CAS are at the L level, and the control signal / WE is at the H level.
Since this is the level, the state is that the auto refresh command has been input. In response, the internal clock enable signal CKEi changes to H level, and the DLL control signal DL
LA also changes to H level. As a result, the comparators 3a and 3b in the clock generator 3 in FIG. 8 are activated, and the DLL input signals DLLi1 and DLLi2 change the external clock signals CLKe and
It becomes a clock signal corresponding to / CLKe. As a result, the DLL circuits 3d and 3e are also activated, and the clock enable signal CKE becomes high.
External clock signal from one cycle after the level
DLL output signals CLKd1 and CLKd2 depending on CLKe and / CLKe
Are sequentially output. When the DLL circuits 3d and 3e are activated, the delay amount is adjusted during this period.

Next, after time C in FIG. 10, since the clock enable signal CKE is at the L level at time C, the power down mode is set again. In response, the internal clock enable signal CKEi changes to L level, and the DLL control signal DLLA also changes to L level. For this reason,
The comparators 3a and 3b in the clock generator 3 in FIG. 8 are deactivated, and the DLL input signals DLLi1 and DLLi2 are fixed at the L level. As a result, the DLL circuits 3d and 3e are also deactivated, and the DLL output signals CLKd1 and CLKd2 are fixed to the L level in accordance with the external clock signals CLKe and / CLKe one cycle after the clock enable signal CKE has changed to the L level. And no longer generates a clock signal. In both the power down mode and the auto refresh mode, the write operation activating signal WRITE and the read operation activating signal READ from the command decode / internal control circuit 8 are inactive, and the input / output buffer circuit 7 Input circuit 7a and output circuit 7b are inactive.

Although the power down mode and the auto refresh mode are shown in FIG. 10, the clock enable signal CKE is at the H level in a read or write operation (not shown), so that the DLL control signal DLLA is at the H level. Level. Therefore, the DLL circuit is in an activated state, and outputs DLL output signals CLKd1 and CLKd2 in accordance with the external clock signals CLKe and / CLKe. For example, during a read operation, the DLL output signal CLKd is output from the output circuit 7b of FIG.
An input / output signal DQi is output according to d1 and CLKd2. Therefore, the read and write operations are the same as in the conventional case.

FIG. 11 is a timing chart schematically showing the operation of the present embodiment for a period longer than that of FIG.
The operation of the clock enable signal CKE and the DLL control signal DLLA is shown. X1 and X2 during which the clock enable signal CKE is continuously at the H level are in the active state, the DLL control signal DLLA is at the H level, and the DLL circuit is in the active state. On the other hand, the period Y in which the clock enable signal CKE is at the L level and the clock enable signal CKE is at the H level in a pulsed manner by an auto-refresh command input as a control signal every predetermined period T is a power down mode, and The DLL control signal DLLA is at the H level in the pulse state for each period T, and the DLL circuit is in the active state while the DLL control signal DLLA is at the L level during other periods.
The DLL circuit becomes inactive.

Next, the inactive state of the DLL circuit 3d when the DLL input signal DLLi1 becomes L level will be described. As shown in FIG. 9, when the DLL input signal DLLi1 goes to L level, the clock signal is not input to the control clock generation circuit 110, so that the operation is stopped, the first and second control signals are also kept constant, and the counter control circuit 140 and the counter stop operating. The DLL input signal DLLi1 passes through the fine delay circuit 160 and the coarse delay circuit 170,
The DLL output signal CLKd1 becomes L level, and the replica circuit 18
The 0 output signal CLKdd is also at the L level. In addition, since the phase comparator 120 also receives the L level signal for the two input signals, the operation is stopped because no clock signal is input.
Further, the operation of the filter 130 is stopped because the input signal DLLi1 of the DLL serving as the control signal is at the L level. As a result, the operation of each part in the DLL circuit 3d is stopped, so that the operating current due to the clock signal does not flow. Further, even if each signal of the DLL circuit is not externally fixed, by fixing DLLi1 and DLLi2 which are input signals of the DLL circuit to L level, the DLL circuit is inactivated and current consumption is suppressed.

As described above, in the present embodiment, the DLL control circuit 12 performs the operation based on the clock enable signal CKE.
A DLL control signal DLLA is generated, and an input signal DL of the DLL circuits 3d and 3e is generated.
By controlling Li1 and DLLi2, the activation of the DLL circuits 3d and 3e is controlled. With this configuration, the DLL circuit is inactivated in the power down mode, and the DLL circuit is activated in the auto refresh. As a result, the current consumption can be significantly reduced by inactivating the DLL circuit in the power down mode. Also,
By operating the DLL circuit at the time of auto-refresh, the delay amount of the internal clock signal can be adjusted at specific intervals.

Incidentally, it has been conceived to control the DLL circuit in the power-down and the auto-refresh. Among the many DRAM circuits that operate in power-down mode, I noticed that the DLL circuit, which is important for timing adjustment in high-speed operation, has a significant effect on power consumption in power-down mode. For example,
128M DDR (Double Dtata Rate) SDRAM with built-in DLL circuit
As a result of the circuit simulation, the power consumption in the power-down mode showed a difference of 9 mA between the activation and inactivation of the DLL circuit. This accounts for a very large proportion of the current consumption value of 10 mA obtained in the simulation of the entire semiconductor device in the power down mode. One possible cause of the high current consumption is that the DLL circuit operates with a high-frequency clock signal, so that charging and discharging are performed one after another in a short time, and the time required for the charge to be accumulated at the nodes in each DLL circuit is relatively short. It is presumed that a large amount of charge flows in a short time from the power supply line to the ground line.

However, the reason for introducing the DLL circuit is to suppress the occurrence of jitter and frequency fluctuation of the internal clock signal caused by external factors such as temperature and power supply voltage fluctuations and process fluctuations of the semiconductor device. Therefore, in order to cope with the case where external factors change every moment,
Conventionally, it is necessary to keep the DLL circuit active even in the power down mode, and it has been difficult to suppress the current consumption in the power down mode. Therefore, as in the present embodiment, in the power down mode, the DLL circuit is temporarily activated by an auto-refresh command input in a specific period as a trigger while inactivating the DLL circuit to reduce current consumption. We have devised the idea of suppressing the jitter of the internal clock signal by adjusting the amount of delay by the DLL circuit in response to the instantaneous change of the external factor at regular intervals. For example, if the external clock signals CLKe and / CLKe operate at 133 MHz and the width of one cycle is 7.5 nsec, if the period during which the DLL circuit is activated is, for example, four cycles, one DLL The operation time of the circuit is 30 nsec. On the other hand, since the period T between refreshes shown in FIG. 11 is 15.6 μsec, the DLL operation period in the power down mode is about 0.2%, and the problem of current consumption is greatly improved. Further, in the present embodiment, the internal clock enable signal CKEi generated based on the signal input from the outside is used as the input signal of the DLL control circuit 12, so that the activation and deactivation of the DLL circuit are performed by the external signal. Can be controlled. The specific period
In order to activate the DLL circuit, a special control signal may be input from outside instead of a combination of the signal and the control signal input to the existing DDR SRAM. However, by using the auto-refresh as in this embodiment, the DLL circuit can be easily activated in a specific period.
Further, since the internal clock enable signal CKEi generated based on the signal input from the outside is a pulse signal, the specific period can be adjusted according to the pulse width from the outside.

Embodiment 2 FIG. 12 shows Embodiment 2 of the present invention.
1 shows the DLL control circuit 12 of FIG. In FIG. 12, the internal clock enable signal CKEi and a signal obtained by delaying the internal clock enable signal CKEi by the delay unit 12c are ORed.
It is input to the circuit 12d and outputs a DLL control signal DLLA.
The DLL control circuit 12 of the second embodiment immediately responds to the rising edge of the internal clock enable signal CKEi by
Although the L control signal DLLA rises, the fall of the DLL control signal DLLA with respect to the fall signal of the internal clock enable signal CKEi is delayed according to the delay amount in the delay unit 12c. The delay unit 12c includes, for example, a unit in which a plurality of inverters are connected, and a unit in which a capacitor and an inverter are combined. Here, it is assumed that the delay amount of the delay unit 12c is two cycles of the external clock signals CLKe and / CLKe assuming a certain clock frequency, and an inverter or the like is configured to delay the fall of the DLL control signal DLLA. .

Next, the DLL control circuit 12 of the second embodiment
The operation of the DDR SDRAM 1 when the DDR SDRAM is used will be described with reference to FIG. 13 which is an operation timing chart of the second embodiment. It should be noted that in FIG.
FIG. 13 in which the second cycle of LKe and / CLKe is time D is different from FIG. 10 in that DLL control signals DLLA and DL after time C are different.
L input signals DLLi1 and DLLi2, DLL output signals CLKd1 and C
LKd2. In FIG. 10, the clock enable signal CKEi
Changes from H level to L level near time C, the DLL control signal DLLA also changes from H level to L level. However, in FIG. 13, the DLL control signal DLLA maintains the H level until around the time D, and thereafter changes from the H level to the L level. Accordingly, the DLL input signals DLLi1 and DLLi2, DLL
The period during which the output signals CLKd1 and CLKd2 also become clock signals for two cycles of the external clock signals CLKe and / CLKe is extended.

FIG. 14 is a block diagram of the second embodiment shown in FIG.
FIG. 3 is a timing chart schematically showing an operation for a long period as in FIG. The difference from FIG. 11 is that the DLL control signal DLLA is set as a pulse signal at H every fixed period T in the power down mode Y.
This is that the period during which the signal is at the level is longer than the period during which the clock enable signal CKE is at the H level as a pulse signal.

As described above, in the present embodiment, the falling signal of the DLL control signal DLLA which is the output signal of the DLL control circuit is delayed. As a result, the DLL circuit can be activated not only during the period when the clock enable signal CKE is at the H level at the time of the auto-refresh but also for a longer period. Therefore, Embodiment 1
Therefore, if the DLL circuit is deactivated in the power down mode, the DLL circuit operation based on the clock enable signal CKE during short-term auto-refresh may not be able to sufficiently adjust the delay amount to external factors. However, using the delay unit 12c as in the present embodiment, D
By adjusting the activation time of the LL circuit, the periodic DL
Even in the operation of the L circuit, the delay amount can be sufficiently adjusted to the external factor.

In the present embodiment, the activation period of the DLL circuit is extended by two cycles of the external clock signals CLKe and / CLKe. However, the extension period is appropriately adjusted by adjusting the delay unit or the like according to the conditions of the DLL circuit. You can choose. Further, it is necessary to determine the amount of extension of the operation period of the DLL in relation to the current consumption of the DLL circuit. However, since the period T between refreshes shown in FIG. 14 is 15.6 μsec, about 10% It is expected that there is no problem even if the DLL circuit is operated for 1.5 μsec. As described in the first embodiment, according to the simulation, the current of 9 mA is conventionally consumed by the DLL circuit. However, when the operation period becomes about 10% as described above, the current becomes 0.9 mA, and other circuit parts are consumed. Is about the same as 1 mA.

Embodiment 3 FIG. 15 shows Embodiment 3 of the present invention.
1 shows the DLL control circuit 12 of FIG. In FIG. 15, 121a to 121e are inverters, 122a is an AND circuit, and 123a to 1
23c is a NAND circuit, 124a and 124b are OR circuits, and 125a is a delay unit. Reference numeral 126a denotes a ring oscillator, which oscillates when the output signal N1 of the AND circuit 122a goes high. The output signal N2 of the ring oscillator 126a is a pulse signal and an octal counter
The pulse signal is input to 127a and counted. The octal counter 127a outputs the signal from the least significant bit Q0 to the most significant bit Q2.
Counts a maximum of 8 pulses and outputs a signal. Also,
8 when the internal clock enable signal CKEi goes high
The binary counter 127a is reset. The NAND circuit 123a receives the output signal Q0 via the inverter 121d and outputs the output signal Q0.
Q1 and Q2 are directly input, and when 6 are counted, the output signal N3 becomes L level.

A flip-flop is formed by the NAND circuits 123b and 123c, and the output signal N5 of the NAND circuit 123c is
The output of the OR circuit is a DLL control signal DLLA, and is also input to the AND circuit 122a.
The inverter 121e, the delay unit 125a, and the OR circuit 124a output an L-side one-shot pulse to the output signal N4 in response to the rising edge of the internal clock enable signal CKEi, which is an input signal, and change the output signal N5 of the NAND circuit 123c to H To level. FIG.
FIG. 6 shows the configuration of the ring oscillator 126a. It is formed of a NAND circuit 123d, an even number of inverters 121f, and an output inverter 121g, and an input signal of the output inverter 121g is also input to the NAND circuit 123d. Inverter 121f
May be selected as appropriate according to the pulse width.

Next, the operation of the third embodiment will be described. FIG. 17 is a timing chart of main signals. First, a pulse signal of the internal clock enable signal CKEi is input. In response to the rise of the internal clock enable signal CKEi, the DLL which is the output signal of the OR circuit 124b
The control signal DLLA becomes H level. This is the DLL control signal DL
This means that LA has risen as a pulse signal, that is, the start of the pulse signal, and the DLL circuits 3d and 3e are activated. In addition, the NOR circuit 124 has the width of the delay amount of the delay unit 125a.
The output signal N4 of a becomes L level. With this, the NAND circuit
The output signal N5 of 123c is high regardless of the other input of the NAND circuit.
Level. Also, the internal clock enable signal CKEi
Is at the H level, the octal counter 127a is reset. Next, the falling of the internal clock enable signal CKEi causes the two input signals of the AND circuit 122a to go high, so that the output signal N1 goes high. This causes the ring oscillator 126a to oscillate, and the output signal of the octal counter becomes Q0 =
When L, Q1 = H, Q2 = H, the output signal N of the NAND circuit 123a
3 goes low, and the output signal of the NAND circuit 123b goes high, so that the output signal N5 of the NAND circuit 123c goes low and the DLL control signal DLLA goes low. this is,
This means that the DLL control signal DLLA has fallen as a pulse signal, that is, the end of the pulse signal, and the DLL circuit 3
d and 3e are deactivated. As a result, the output signal N1 of the AND circuit 122a becomes L level, and the oscillation of the ring oscillator 126a stops.

As described above, in the third embodiment, the pulse signal is generated in the DLL control circuit and is used by using the pulse signal.
The end of the pulse signal of the DLL control signal DLLA has been delayed.
Thus, the end of the pulse signal can be easily delayed as compared with the case where the delay section is formed only by the inverter and the resistor. In addition, the generation of pulse signals in the DLL control circuit is performed by a ring oscillator, and the end of the pulse signal of the DLL control signal DLLA is reached by a counter that counts the number of pulses of the pulse signal of the ring oscillator. It was based on. By using the ring oscillator and the counter, a pulse signal having a long pulse width can be accurately used as the DLL control signal DLLA. In this embodiment, an octal counter is used as the counter, but the counter can be changed as appropriate. Further, unlike the present embodiment, it is not necessary to use the maximum count number as the output of the counter, and it is sufficient to select an appropriate value. Here, since the internal clock enable signal CKEi had a certain width, six counts were used.

Embodiment 4 FIG. 18 shows Embodiment 4 of the present invention.
1 is a schematic diagram showing an overall configuration of a DDR SDRAM 1 of FIG. FIG.
1 in that the internal clock signal CLKi from the clock oscillator 3 is input to the DLL control circuit 12. FIG. 19 shows the DLL control circuit 12 according to the fourth embodiment. FIG. 19 differs from FIG.
Inverter 121a, AND circuit 122a, ring oscillator 126
a, and the input of the octal counter 127a is output from the output signal N2 of the ring oscillator 126a to the internal clock signal CLKi.
It is a point that has changed.

Next, the operation of the fourth embodiment will be described. FIG. 20 shows a timing chart of main signals. The operation is almost the same as that of the third embodiment, except that the internal clock signal CLKi always generates a pulse signal. However, the counting operation of the octal counter 127a starts when the internal clock enable signal CKEi, which is a reset signal, changes from the H level to the L level. Operate.

As described above, the pulse signal counted by the octal counter 127a is used in the third embodiment of FIG.
What is generated by the ring oscillator 126a inside the DDR SDRAM 1 is different from the DDR SDRAM 1 in the fourth embodiment shown in FIG.
This is changed to an internal clock signal CLKi formed from an external clock signal CLK which is a signal external to the SDRAM 1.
In the fourth embodiment, since a signal generated from an external signal is used, a pulse oscillator such as the ring oscillator 126a is not required, and the DLL control circuit 12 having a small area can be realized. Further, since a signal generated from an external signal is used, the signal can be synchronized with an external signal, and the pulse width of the DLL control signal DLLA can be adjusted according to the external signal.

Embodiment 5 FIG. 21 shows Embodiment 5 of the present invention.
1 shows the DLL control circuit 12 of FIG. In FIG. 21, 128a to 128c are commonly used D (Delayed) flip-flops. When a pulse signal is applied to the pulse input CLK of the D flip-flop, the input is applied to the input D of the D flip-flop. The signal is output to the output circuit Q of the D flip-flop. Also, the reset section ZRESET
When an L level signal is input to the output circuit Q, a reset state occurs, and an H level signal is output to the output circuit Q. The internal clock signal CLKi is input to the pulse input section CLK of each D flip-flop, the internal clock enable signal CKEi is input to the input section D of the D flip-flop 128a, and the signal N1 is output from the output circuit Q. D flip-flop
The signal N1 is input to the input unit D of 128b, the signal N2 is output from the output circuit Q, the signal N2 is input to the input unit D of the D flip-flop 128c, and the signal N3 is output from the output circuit Q.
Further, the DLL control circuit 12 of the fifth embodiment includes inverters 124f and 124g and a NAND circuit 123e. The shift register 129a is composed of the D flip-flops 128a to 128c and the inverter 124f. Note that the DD of the fifth embodiment
The overall configuration of the R SDRAM 1 is the same as in FIG.

Next, the operation of the fifth embodiment will be described. FIG. 22 shows a timing chart of main signals. In FIG. 22, the internal clock enable signal CK
When Ei goes high, a low-level signal is input to the ZRESET section of each of the D flip-flops 128a to 128c via the inverter 124f, the D flip-flops 128a to 128c are reset, and the output circuit Q goes high. Becomes Further, since the output signal of the inverter 124f is input to the NAND circuit 123e, the DLL control signal DLLA, which is the output signal of the NAND circuit, goes high. Next, the internal clock enable signal CKEi goes low.
At the level, each D flip-flop 128a-128c
The internal clock signal CLKi operates in accordance with the internal clock signal CLKi. First, at the first pulse of the internal clock signal CLKi after the internal clock enable signal CKEi is at L level, the L level is input to the input section D of the D flip-flop 128a. From that
The output signal N1 becomes L level. At this time, the output signal N
2, N3 remains at H level.

Subsequently, at the second pulse of the internal clock signal CLKi, the input D of the D flip-flops 128a and 128b is
Since the L level is input, the output signals N1 and N
2 becomes L level. At this time, the output signal N3 remains at the H level. Subsequently, the third internal clock signal CLKi
At the pulse, the input D of each of the D flip-flops 128a to 128c
Output signal N1 to N3
Becomes L level. For this reason, since the signal via the inverter 124g and the inverter 124f becomes H level, the NAND
The DLL control signal DLLA, which is the output signal of the circuit 123d, goes low. Here, an example in which the L-level signal moves through the three D flip-flops 128a to 128c has been described. However, the number of D flip-flops may be adjusted as appropriate, and a logic is used to move the H-level signal. Circuits and the like may be combined.

As described above, in the fifth embodiment, the DLL
A shift register was used as a circuit for setting the control signal DLLA to the H level for a certain period. In the case of using a counter as in the fourth embodiment, when a counter that counts a large number of pulses is used, when the output Qi of the counter changes from the lower bit to the upper bit, the upper bit sequentially changes based on the lower bit. Therefore, signal transmission in the counter may take time. On the other hand, the shift register moves data from the preceding stage to the next stage D flip-flop, and therefore can operate at high speed even with a multistage D flip-flop. Further, since the signal is synchronized with the internal clock signal CLKi generated by an external signal, the pulse width of the DLL control signal DLLA can be adjusted according to the external signal.

Embodiment 6 FIG. 23 shows Embodiment 6 of the present invention.
1 shows the DLL control circuit 12 of FIG. In FIG. 23, there are four main differences from FIG. 15 of the third embodiment. First, the AND circuit 122a of FIG.
Is directly input to the ring oscillator 126a.
Second, a NAND circuit 123f is newly added, and its output signal N6
Is input to the NAND circuit 123c, and the NAND 123c becomes a three-input NAND circuit. Third, the input signal N5 of the OR circuit 124b is
This means that the output signal of the NAND circuit 123c has changed to the output signal of the NAND circuit 123b. Fourth, the output signal Q0 of the octal counter 127a, the inverted signal of the output signal Q1, and the output signal Q2 are input to the NAND circuit 123a, and the output signals Q0 to Q2 are input to the NAND circuit 123f. is there.

Next, the operation of the sixth embodiment will be described. FIG. 24 shows a timing chart of main signals. In FIG. 24, the internal clock enable signal CK
When Ei becomes H level, DLL which is the output signal of the OR circuit 124b
The control signal DLLA becomes H level. Next, when the internal clock enable signal CKEi goes low, the DLL control signal DLLA, which is the output signal of the OR circuit 124b, goes low. As a result, the DLL circuit is activated while the internal clock enable signal CKEi is at the H level.

The internal clock enable signal CKEi
In response to the change from the H level to the L level, the ring oscillator 126a starts oscillating, and when the number of pulses reaches 5, the output signal Q0 of the octal counter 127a is at the H level, Q1 is at the L level, and Q2 is
Since it is at H level (not shown), the output signal N3 of the NAND circuit 123a is at L level. In response, the output signal N5 of the NAND circuit 123b goes high. Further, the DLL control signal DLLA output from the OR circuit 124b goes high.

Thereafter, when the pulse number of the ring oscillator 126a becomes 7, the output signals Q0 to Q2 of the octal counter 127a become H
Level (not shown), so that the output signal N6 of the NAND circuit 123f becomes L level. As a result, the signal which is the output of the NAND circuit 123c and the input of the NAND circuit 123b becomes H level. Further, since the output signal N3 of the NAND circuit 123a is also at the H level, the output signal N5 of the NAND circuit 123b is at the L level.
In response, the DLL control signal D, which is the output signal of the OR circuit 124b,
LLA also becomes L level. Therefore, while the number of pulses of the ring oscillator 126a is 5 to 7, the DLL control signal DLLA is at the H level.

Next, when the pulse number of the ring oscillator 126a exceeds 8, the octal counter 127a returns the count number to 0, and sequentially counts the pulse number of the ring oscillator 126a again. For this reason, the octal counter periodically
During the counting of 7, the DLL control signal DLLA is at the H level.

As described above, in the sixth embodiment, the DLL
After the second pulse signal of the control signal DLLA, the start and end of the pulse signal of the DLL control signal DLLA are determined based on the pulse signal generated in the DLL control circuit. For this reason, the DLL control signal DLLA can easily be a pulse signal having a constant width. In addition, since the ring oscillator is continuously oscillated and a logic circuit is used in which the DLL control signal DLLA becomes a pulse signal for each fixed count according to the combination of the output signals of the counter, the DLL control circuit requires an external start-up signal. If you give a trigger of DL
The L circuit can be activated. Although the example in which the pulse signal is oscillated by the ring oscillator in the DLL control circuit has been described, the same applies to the case where the clock signal generated based on the external clock signal of the fourth and fifth embodiments is used as the pulse signal. It can be carried out.

Embodiment 7 FIG. 25 shows one of Embodiments 7 of the present invention.
FIG. 1 is a schematic diagram showing the overall configuration of a 28 Mbit DDR SDRAM. 25 differs from FIG. 1 in that the signal input to the DLL control circuit 12 is the output signal of the command decode / internal control circuit 8 from the internal clock enable signal CKEi which is the output signal of the control input signal buffer circuit 5. This is a point that has changed to the auto refresh instruction signal ARF.

Next, the operation of the seventh embodiment will be described. Here, the DLL control circuit 12 has the same configuration as that of FIG. 12 of the second embodiment, and the delay amount of the delay unit 12c in FIG. 12 is 1.5 cycles of the external clock signals CLKe and / CLKe. It is assumed that an inverter or the like is configured to delay the fall of the control signal DLLA. FIG. 26 shows FIG.
3 is a diagram showing main operation timings of the DDR SDRAM of FIG. From the command decode / internal control circuit 8 shown in FIG. 4, when the external control signals / CS, / RAS, / CAS are at L level, / WE is at H level and the internal clock signal CLKi is at H level, Refresh instruction signal ARF attains H level. In response, DLL control signal DLLA attains an H level for two cycles of external clock signals CLKe and / CLKe.
In response, the DLL input signals DLLi1 and
DLLi2 and DLL output signals CLKd1 and CLKd2 change (not shown in FIG. 26).

As described above, the clock enable signal CK
Instead of using E, the DLL control signal DLLA may be formed using the auto-refresh instruction signal ARF. By forming the DLL control signal DLLA based on a plurality of control signals, it is possible to prevent malfunction due to a single signal of only the clock enable signal CKE. Specifically, even if noise or the like appears on the clock enable signal CKE, the DLL circuit is not activated unless the auto-refresh instructing signal ARF goes high, so that malfunction due to noise or the like can be prevented.

Eighth Embodiment In the first to seventh embodiments, in the power down mode, the DLL circuit is deactivated and the DLL circuit is activated based on the signal at the time of the auto refresh. Is also applicable. For example, since the DLL circuit controls output data at the time of a read operation, the activation of the DLL circuit is not performed at the time of the read operation, for example, at the time of the write operation, unless jitter of the internal clock occurs due to an external factor. Not required. However, unlike auto-refresh, a signal is not always input from the outside during a specific period. Therefore, it is necessary to periodically generate a control signal for activating a DLL circuit inside the DRAM. For this reason, when not in the read operation, it is necessary to use a circuit for periodically operating the DLL circuit as in the sixth embodiment. In this case, for example, a read operation activation signal READ from the command decode / internal control circuit 8 may be used instead of the internal clock enable signal CKEi in FIG. That is, any signal for activating the read operation may be used. It is also possible to use an inverted signal of the write operation activating signal WRITE which is a direct signal of the write operation which is the same signal as the signal for activating the read operation. As described above, in the eighth embodiment, the DLL circuit is periodically operated when not in the read operation, so that current consumption when not in the read operation can be suppressed.

In the above embodiment, the semiconductor device
Although a DDR SDRAM is shown as an example, the same applies to a semiconductor device using a DLL circuit. When a circuit operating in synchronization with an output signal of the DLL circuit is in an inactive state, the DLL circuit is activated for a specific period. As a result, the delay amount can be adjusted, and the current consumption can be suppressed. Further, when the circuit operating in synchronization with the output signal of the DLL circuit is in the active state, the delay amount is appropriately adjusted, so that it can be applied to high-speed operation. Furthermore, not only a DLL circuit but also a clock generation circuit that generates an internal clock signal based on an external clock signal can be similarly applied. For example, when applied to a PLL (Phase Locked Loop) circuit, current consumption is small, It is possible to suppress a phase error and operate in synchronization with a high-speed external clock. Further, in the first to eighth embodiments, the case where each pulse signal is at the H level is almost in the active state, but the pulse signal at the L level may be made active by appropriately changing the logic. For example, the DLL control signal DLLA may be activated when it is at the L level. In this case, the DLL control signal D
By delaying the rise of the LLA, the activation period of the DLL circuit is lengthened.

[0068]

As described above, according to the semiconductor device of the first aspect of the present invention, when the clock synchronization circuit is inactive, the control circuit for activating the clock generation circuit for a specific period is provided. When in the inactive state, the clock generation circuit can suppress current consumption during periods other than the specific period. Second
According to the semiconductor device of the present invention, since the control signal for activating or deactivating the clock generation circuit is generated based on the signal input from the outside, the activation and deactivation can be determined by the external signal. According to the semiconductor device of the third aspect, when the clock synchronization circuit is in an inactive state, the control signal for activating the clock generation circuit is generated based on a pulse signal input from the outside. The activation period can be adjusted by the width. According to the semiconductor device of the fourth aspect, the clock generation circuit activates the second pulse signal generated by delaying the rise or fall of the first pulse signal generated based on the pulse signal input from the outside. Therefore, the activation can be made longer than the width of the pulse signal input from the outside. According to the semiconductor device of the fifth aspect, the start of the second pulse signal is based on the change of the first pulse signal, and the end of the second pulse signal is based on the third signal generated in the control circuit. Therefore, the second pulse signal having a fixed length can be easily formed.

According to the semiconductor device of the sixth aspect, since the start and end of the second pulse signal are determined by the third pulse number, the second pulse signal having a fixed length can be easily formed. it can. According to the semiconductor device of the seventh invention, the second
Are generated periodically, so that the clock generation circuit can be easily and periodically activated. According to the semiconductor device of the eighth aspect, since the control circuit includes the ring oscillator that generates the pulse signal and the counter that counts the number of pulses, it is possible to easily generate the pulse signal and count the number of pulse signals. According to the semiconductor device of the ninth aspect, when the counter reaches the first pulse number, it outputs a signal indicating the start of the second pulse signal, and when the counter reaches the second pulse number, the counter outputs the second pulse signal. Since a logic circuit for outputting a signal indicating the end is provided, the width of the second pulse signal is automatically determined. According to the semiconductor device of the tenth aspect, since the start and end of the second pulse signal are determined by another internal clock signal generated based on the external clock signal, the third pulse signal is stored in the control circuit. And a control circuit having a small area can be realized without the need for a circuit for generating the signal.

According to the semiconductor device of the eleventh aspect, since the control circuit has the counter for counting the number of pulses, the first pulse signal can be easily counted. According to the semiconductor device of the twelfth aspect, the control circuit includes the shift register controlled by another internal clock signal generated based on the external clock signal. 2 pulse signals can be generated. According to the semiconductor devices of the thirteenth and fourteenth aspects, the clock generation circuit includes the DLL (Delay Locked Loop) circuit, so that the current consumption of the DLL circuit can be suppressed when the clock synchronization circuit is in the inactive state. The amount of delay can be adjusted by activating a specific period. According to the semiconductor devices of the fifteenth and sixteenth aspects, the input signal of the DLL circuit is a fixed signal in the inactive state of the clock generation circuit, so that the operation of the DLL circuit can be easily stopped.

According to the semiconductor device of the seventeenth aspect, since the clock synchronization circuit is applied to a dynamic random access memory and is a circuit for outputting read data of the dynamic random access memory, a stable read operation can be performed with low current consumption. It becomes a dynamic random access memory. According to the semiconductor device of the eighteenth aspect, the input signal of the control circuit is based on the clock enable signal for instructing the input of an external signal for controlling the operation of the dynamic random access memory. Thus, the DLL circuit can be activated for a specific period. According to the semiconductor device of the nineteenth aspect, since the read data output circuit is in the inactive state in the power down mode, current consumption in the power down mode can be suppressed. According to the semiconductor device of the twentieth aspect, since the specific period during which the clock generation circuit is activated includes the time of auto-refresh of the dynamic random access memory, the clock generation circuit can be activated in accordance with the refresh.

According to the semiconductor device of the twenty-first aspect, since the input signal generated based on the signal input from the outside in the control circuit is the auto-refresh instruction signal, the input signal is generated based on a plurality of external signals. It is strong against noise etc. According to the semiconductor device of the twenty-second aspect, since the input signal generated based on the signal input from the outside in the control circuit is a signal for activating the read operation, the current consumption can be suppressed except for the read operation. Can be. According to the semiconductor device of the twenty-third aspect, the specific period for activating the clock generation circuit is set to 10% or less of the power down mode period, so that the current consumption can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is an overall schematic diagram of a DDR SDRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a control input buffer circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a control input buffer circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a command decoding and a decoding according to the first embodiment of the present invention;
It is a circuit diagram of an internal control circuit.

FIG. 5 is a circuit diagram of an internal address generating circuit according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram of the input / output buffer circuit according to the first embodiment of the present invention;

FIG. 7 is a circuit diagram of a DLL control circuit according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram of the clock generator according to the first embodiment of the present invention.

FIG. 9 is a circuit diagram of a DLL circuit according to the first embodiment of the present invention.

FIG. 10 is an operation timing chart of the DDR SDRAM according to the first embodiment of the present invention;

FIG. 11 is an operation timing chart of the DDR SDRAM according to the first embodiment of the present invention;

FIG. 12 is a circuit diagram of a DLL control circuit according to a second embodiment of the present invention.

FIG. 13 is an operation timing chart of the DDR SDRAM according to the second embodiment of the present invention;

FIG. 14 is an operation timing chart of the DDR SDRAM according to the second embodiment of the present invention;

FIG. 15 is a circuit diagram of a DLL control circuit according to Embodiment 3 of the present invention.

FIG. 16 is a circuit diagram of a ring oscillator according to a third embodiment of the present invention.

FIG. 17 is an operation timing chart of the DLL control circuit according to the third embodiment of the present invention;

FIG. 18 is an overall schematic diagram of a DDR SDRAM according to a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram of a DLL control circuit according to a fourth embodiment of the present invention.

FIG. 20 is an operation timing chart of the DLL control circuit according to the fourth embodiment of the present invention;

FIG. 21 is a circuit diagram of a DLL control circuit according to a fifth embodiment of the present invention.

FIG. 22 is an operation timing chart of the DLL control circuit according to the fifth embodiment of the present invention;

FIG. 23 is a circuit diagram of a DLL control circuit according to Embodiment 6 of the present invention.

FIG. 24 is an operation timing chart of the DLL control circuit according to the sixth embodiment of the present invention;

FIG. 25 is an overall schematic diagram of a DDR SDRAM according to a seventh embodiment of the present invention.

FIG. 26 is an operation timing chart of the DLL control circuit according to the seventh embodiment of the present invention.

[Explanation of symbols]

 1 DDR SDRAM 3 Clock generator 3d, 3e DLL circuit 7 I / O buffer circuit 7b Output circuit 12 DLL control circuit 126a Ring oscillator 127a Octal counter 129a Shift register ARF Auto refresh instruction signal CLKe, / CLKe External clock signal CLKi Internal clock signal CKE clock enable signal CKEi internal clock enable signal CLKd1, CLKd2 DLL output signal DLLA DLL control signal DLLi1, DLLi2 DLL input signal

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) JJ03 JJ32 JJ38 KK18 PP01 PP02 PP03 PP07

Claims (23)

[Claims] A clock generation circuit that generates an internal clock signal based on an external clock signal; a clock synchronization circuit that operates in synchronization with the internal clock signal; and when the clock synchronization circuit is in an inactive state. And a control circuit for activating the clock generation circuit for a specific period. 2. The control circuit according to claim 1, wherein a signal generated based on a signal input from the outside is used as an input signal, and a control signal for activating or deactivating a clock generation circuit is generated according to the input signal. Item 2. The semiconductor device according to item 1. 3. When the clock synchronization circuit is inactive,
3. The semiconductor device according to claim 2, wherein the control signal for activating the clock generation circuit is generated based on a pulse signal input from outside. 4. A control circuit, wherein a first pulse signal generated based on a pulse signal input from the outside is used as an input signal, and a second pulse obtained by delaying a rise or a fall of the first pulse signal is provided. 4. The semiconductor device according to claim 3, wherein the pulse signal is a control signal for activating a clock generation circuit. 5. The start of the second pulse signal is based on a change in the first pulse signal, and the end of the second pulse signal is generated in the control circuit based on the first pulse signal. 5. The semiconductor device according to claim 4, wherein the third pulse signal is based on reaching a certain number of pulses. 6. The beginning of the second pulse signal is based on a third pulse signal generated in the control circuit based on the first pulse signal reaching a first number of pulses,
5. The semiconductor device according to claim 4, wherein the end of the second pulse signal is based on the third pulse reaching a second pulse number greater than the first pulse number. 7. When the third pulse signal reaches a third pulse number greater than the second pulse number, the pulse number of the third pulse signal is reset, and the pulse number of the third pulse signal is reset again. Increases, and the second pulse signal is periodically generated by reaching the first and second pulse numbers.
3. The semiconductor device according to claim 1. 8. The semiconductor device according to claim 5, wherein the control circuit includes a ring oscillator that generates a third pulse signal, and a counter that counts the number of pulses of the third pulse signal. 9. A control circuit comprising: a ring oscillator for generating a third pulse signal; a counter for counting the number of pulses of the third pulse signal; and a second pulse signal when the counter reaches the first pulse number. 8. A semiconductor device according to claim 6, further comprising: a logic circuit that outputs a signal indicating the start of the second pulse signal, and outputs a signal indicating the end of the second pulse signal when the number of pulses reaches the second pulse number. 10. The control circuit further receives another internal clock signal generated based on an external clock signal, and the start of the second pulse signal is based on a change in the first pulse signal. 5. The semiconductor device according to claim 4, wherein the end of the second pulse signal is based on the other internal clock signal reaching a certain number of pulses. 11. The semiconductor device according to claim 10, wherein the control circuit includes a counter for counting the number of pulses of another internal clock signal. 12. The control circuit includes a shift register controlled by another internal clock signal generated based on an external clock signal, wherein the start of the second pulse signal is a change of the first pulse signal. 5. The semiconductor device according to claim 4, wherein the end of the second pulse signal is based on the first pulse signal passed through the shift register. 13. The clock generation circuit may be a DLL (Delay Loc).
The semiconductor device according to claim 1, further comprising a (ked Loop) circuit. 14. A clock generation circuit comprising a DLL (Delay Loc)
The semiconductor device according to claim 2, further comprising a (ked Loop) circuit. 15. The semiconductor device according to claim 13, wherein the clock generation circuit sets the input signal of the DLL circuit to a fixed signal before and after being activated for a specific period. 16. The semiconductor device according to claim 14, wherein the clock generation circuit sets the input signal of the DLL circuit to a fixed signal before and after being activated for a specific period. 17. The semiconductor device according to claim 16, wherein the semiconductor device includes a dynamic random access memory, and the clock synchronization circuit includes a read data output circuit of the dynamic random access memory. 18. The control circuit according to claim 17, wherein the input signal generated based on an externally input signal is a clock enable signal for instructing input of an external signal for controlling operation of the dynamic random access memory.
3. The semiconductor device according to claim 1. 19. The semiconductor device according to claim 17, wherein the inactive state of the read data output circuit is a power down mode of the dynamic random access memory. 20. The semiconductor device according to claim 19, wherein the specific period in which the clock generation circuit is activated includes a time of an automatic refresh of the dynamic random access memory. 21. The semiconductor device according to claim 17, wherein the input signal generated based on an externally input signal in the control circuit is an auto refresh instruction signal. 22. The semiconductor device according to claim 17, wherein the input signal generated based on an externally input signal in the control circuit is a signal for activating a read operation. 23. The semiconductor device according to claim 18, wherein the specific period for activating the clock generation circuit is set to 10% or less of the power down mode period.