JP2022050172A - Oscillation circuit of multiple phases - Google Patents

Abstract

To provide an oscillation circuit capable of generating various pulses.SOLUTION: An oscillation circuit is equipped with a main ring circuit 20 in which an odd-number of inverters are connected in a rind-shape, and a plurality of output circuits connecting two inverters in series. An output terminal is provided at a contact point between the respective inverters configuring the main ring circuit 20. Among the add-number of inverters configuring the main ring circuit, in the two output terminals across the number of inverters that is a predetermined divisor of the odd-number, a space between a cathode at a tip end of one output terminal and the contact point of the inverters of the other output terminal is provided as a first output portion, and a space between the contact point of the inverters of the one output terminal and a cathode at a tip end of the other output terminal is provided as a second output portion.SELECTED DRAWING: Figure 1

Description

The present invention relates to a multi-phase oscillator circuit.

An oscillator is an oscillator that has an odd number of inverters connected to form a closed circuit. Such circuits are commonly known as ring oscillators.

Further, Patent Document 1 discloses a ring oscillator for realizing a higher oscillation frequency.
The ring oscillator of Patent Document 1 uses a square main loop circuit consisting of four inverters (even number of inverters) and a triangular loop circuit consisting of three inverters (odd number of inverters) as an excitation circuit. We have adopted a configuration in which multiple units are provided.

In Patent Document 2, a plurality of ring-shaped main rings composed of three inverters are provided, a phase coupling ring in which a plurality of inverters are connected in a ring shape is provided, and the connection node of each main ring is phase-coupled. Described is an oscillator circuit connected to a second connection node having a different ring and connected between the second connection nodes of the phase coupling ring by a resistor which is a second phase coupling element.

Japanese Unexamined Patent Publication No. 2010-50591 Japanese Unexamined Patent Publication No. 2011-19053

In the conventional oscillator described above, it is possible to oscillate at high speed, but it is simply possible to generate a plurality of pulses having different phases.
However, the present inventor says that if it is possible to change not only the phase but also the pulse period and output various pulses, it will be possible to execute many parallel processes in a computer or the like, which will lead to an improvement in processing speed. Thought.

Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide an oscillation circuit capable of generating various pulses.

According to the multi-phase oscillation circuit according to the present invention, the main ring circuit in which an odd number of inverters are connected in a ring shape and a plurality of output circuits in which two inverters are connected in series are provided. The anode side of the output circuit is connected to the connection point between the inverters constituting the ring circuit to be provided as an output terminal, and among the odd number of inverters constituting the main ring circuit, the odd number is a predetermined reduction. One of the output terminals in a plurality of output terminals among n output terminals (n is a natural number of 1 or more and the quotient obtained by dividing the odd number by the predetermined fraction) across a certain number of inverters. An output section is provided between the connection point between the inverters and the cathode at the tip of the adjacent output terminal straddling the output terminal and the predetermined number of inverters, and the cathode at the tip is one end of the output section. The connection point between the inverters of the output terminals and the cathode at the tip of the adjacent output terminals straddling the output terminal and the predetermined number of inverters is provided as an output unit. It is characterized in that a plurality of output units are provided so as to go around the main ring circuit.
By adopting this configuration, as the output unit for outputting the pulse, for example, in the main ring circuit composed of 15 inverters, the output unit can be provided at 6 places, 10 places or 30 places. It is possible to output various pulses with different pulse periods and phases.

Further, at one connection point between the inverters constituting the main ring circuit, two output terminals are connected to each of the anode sides to provide two output terminals, and the inverters of the main ring circuit are connected to each other. The connection point between the inverters of one of the two output terminals provided at one connection point, and the two adjacent outputs straddling the output terminal and the predetermined number of inverters. The connection point between the inverters of the output terminal is provided as an output unit between the inverter at the tip of one of the terminals and the cathode at the tip is provided as one end of the output unit, and the output terminal and the predetermined value are provided. A plurality of inverters straddling the number of inverters and between the inverters at the tips of adjacent output terminals and the cathode at the tip of the adjacent output terminals are provided as output units around the main ring circuit, and n output units are provided. , The cathode at the tip of the other output terminal of the two output terminals provided at one connection point between the inverters of the main ring circuit, and the output terminal and the number of inverters which are the predetermined number of inverters. The cathode at the tip of the output terminal, which is provided as an antiphase output unit between the connection points of the inverters of the adjacent output terminals and the connection points of the inverters are provided as one end of the output unit, and the output terminal. A plurality of inverters having the predetermined number of inverters straddling the inverters of the adjacent output terminals and the connection points of the inverters of the adjacent output terminals are provided as anti-phase output units around the main ring circuit. It may be characterized in that the anti-phase output unit of is provided.

According to the multi-phase oscillation circuit of the present invention, it is possible to output various pulses having different pulse periods and phases.

It is a circuit diagram of the 1st Embodiment of an oscillation circuit. It is a time chart of the pulse output by the oscillation circuit of 1st Embodiment. It is a circuit diagram of the 2nd Embodiment of an oscillation circuit. It is a time chart of the pulse output by the oscillation circuit of the 2nd Embodiment. It is a circuit diagram of the 3rd Embodiment of an oscillation circuit. It is a circuit diagram of another embodiment of an oscillation circuit. It is a periodic diagram of the pulse output by the oscillation circuit of another embodiment.

(First Embodiment)
FIG. 1 shows the oscillation circuit of the simplest embodiment.
The main ring circuit 20 is formed by connecting three inverters A, B, and C in a ring shape. The cathode of the inverter A is connected to the anode of the inverter B, the cathode of the inverter B is connected to the anode of the inverter C, and the cathode of the inverter C is connected to the anode of the inverter A.

An output circuit composed of two inverters a and a'is connected to the connection point between the inverter A and the inverter B. The anode side of this output circuit is connected to the connection point between the inverter A and the inverter B and is provided as an output terminal 21.
An output circuit composed of two inverters b and b'is connected to the connection point between the inverter B and the inverter C. The anode side of this output circuit is connected to the connection point between the inverter B and the inverter C, and is provided as an output terminal 22.
An output circuit composed of two inverters c and c'is connected to the connection point between the inverter C and the inverter A. The anode side of this output circuit is connected to the connection point between the inverter C and the inverter A, and is provided as an output terminal 23.

The first connection point between the connection point between the inverter a and the inverter a'in the output terminal 21 (the position between the cathode of the inverter a and the anode of the inverter a') and the cathode of the inverter b'at the tip of the output terminal 22. It is provided as an output unit 24.
The second connection point between the connection point between the inverter b and the inverter b'in the output terminal 22 (the position between the cathode of the inverter b and the anode of the inverter b') and the cathode of the inverter c'at the tip of the output terminal 23. It is provided as an output unit 25.
A third is between the connection point between the inverter c and the inverter c'in the output terminal 23 (the position between the cathode of the inverter c and the anode of the inverter c') and the cathode of the inverter a'at the tip of the output terminal 21. It is provided as an output unit 26.

The pulse output in the oscillation circuit of FIG. 1 is shown in FIG.
Six pulses (six pulse widths are the same) are output from the output units 24 to 26 at three locations in one cycle. Specifically, six pulses are continuously output to form one cycle, and one positive pulse and one negative pulse are output from one output unit during one cycle. Regarding the positive / negative of the pulse in this embodiment, the case where the current flows clockwise from each output unit 24 to 26 is defined as positive, and the case where the current flows counterclockwise is defined as negative in FIG.

First, a positive pulse is output from the first output unit 24 ((1) in FIGS. 1 and 2). Next, a negative pulse is output from the second output unit 25 ((2) in FIGS. 1 and 2). Next, a positive pulse is output from the third output unit 26 ((3) in FIGS. 1 and 2). Next, a negative pulse is output from the first output unit 24 ((4) in FIGS. 1 and 2). Next, a positive pulse is output from the second output unit 25 ((5) in FIGS. 1 and 2). Next, a negative pulse is output from the third output unit 26 ((6) in FIGS. 1 and 2).

As described above, in the main ring circuit 20 having three inverters (odd number), output terminals are provided every other inverter, and the number of output terminals is three. The output units are provided at three locations, but since each output unit outputs a positive pulse and a negative pulse once during one cycle, six pulses are output during one cycle. ..

When a total of 6 pulses are output from the 1st output unit 24 to the 3rd output unit 26, one cycle ends and the next cycle is reached. In the next cycle, six pulses are output in the same manner as the pulse shown in FIG. After that, the cycle in which 6 pulses are output is repeated.
Therefore, according to the oscillation circuit of the present embodiment, since the cycle in which six pulses are output is repeated, there is a possibility that data processing in the septenary system can be performed.

In addition, in FIG. 1, in order to confirm whether it is a positive pulse or a negative pulse, an LED circuit 29 in which two LEDs are connected in parallel so that their anodes and cathodes are opposite to each other is connected to each output unit 24 to 26. Although it is provided, it is not necessary to provide the LED circuit 29 when actually outputting the pulse from each output unit 24 to 26.

(Second embodiment)
Next, in FIG. 3, in a main ring circuit 20 having three inverters (odd number), the number of output terminals provided at the connection points of each inverter is set to two, and six pulses are output in one cycle. An embodiment of an oscillation circuit provided with two is shown.
The same components as those in the embodiment shown in FIG. 1 may be designated by the same reference numerals and the description thereof may be omitted.

The circuit in which the three inverters A to C described in the center of FIG. 3 are connected in a ring shape is referred to as a main ring circuit 20.
Two output terminals, an output terminal 21 and an output terminal 31, are connected in parallel between the inverter A and the inverter B of the main ring circuit 20. The output terminal 21 is composed of a circuit in which two inverters a1 and a1'are connected in series. The output terminal 31 is also composed of a circuit in which two inverters a2 and a2'are connected in series.

Two output terminals, an output terminal 22 and an output terminal 32, are connected in parallel between the inverter B and the inverter C of the main ring circuit 20. The output terminal 22 is composed of a circuit in which two inverters b1 and b1'are connected in series. The output terminal 32 is also composed of a circuit in which two inverters b2 and b2'are connected in series.

Two output terminals, an output terminal 23 and an output terminal 33, are connected in parallel between the inverter C and the inverter A of the main ring circuit 20. The output terminal 23 is composed of a circuit in which two inverters c1 and c1'are connected in series. The output terminal 33 is also composed of a circuit in which two inverters c2 and c2'are connected in series.

The first is between the connection point between the inverter a1 and the inverter a1'in the output terminal 21 (the position between the cathode of the inverter a1 and the anode of the inverter a1') and the cathode of the inverter b1'at the tip of the output terminal 22. It is provided as an output unit 24.
The second connection point between the connection point between the inverter b1 and the inverter b1'in the output terminal 22 (the position between the cathode of the inverter b1 and the anode of the inverter b1') and the cathode of the inverter c1'at the tip of the output terminal 23. It is provided as an output unit 25.
The third is between the connection point between the inverter c1 and the inverter c1'in the output terminal 23 (the position between the cathode of the inverter c1 and the anode of the inverter c1') and the cathode of the inverter a'at the tip of the output terminal 21. It is provided as an output unit 26.

The circuit configuration in the first output unit 24 to the third output unit 26 is the same as the circuit configuration shown in FIG. 1, and the pulse as shown in FIG. 2 is emitted from the first output unit 24 to the third output unit 26. It is output.

Next, the circuit configuration shown on the left side of the main ring circuit 20 in FIG. 3 will be described.
Opposite phase between the cathode of the inverter a2'at the tip of the output terminal 31 and the connection point between the inverter b2 and the inverter b2' at the output terminal 32 (the position between the cathode of the inverter b2 and the anode of the inverter b2'). It is provided as a first output unit 34.
Opposite phase between the cathode of the inverter b2'at the tip of the output terminal 32 and the connection point between the inverter c2 and the inverter c2' at the output terminal 33 (the position between the cathode of the inverter c2 and the anode of the inverter c2'). It is provided as a second output unit 35.
Opposite phase between the cathode of the inverter c2'at the tip of the output terminal 33 and the connection point between the inverter a2 and the inverter a2' at the output terminal 31 (the position between the cathode of the inverter a2 and the anode of the inverter a2'). It is provided as a third output unit 36.

Further, in FIG. 3, in order to confirm the positive / negative of the pulse, an LED circuit 29 in which two LEDs are connected in parallel so that the anode and the cathode of each LED are in opposite directions is connected to each output unit 24 to 26 and each reverse. Although it is provided in the phase output units 34 to 36, it is not necessary to provide the LED circuit 29 when actually outputting the pulse from each output unit 24 to 26 and each antiphase output unit 34 to 36.

The pulse output in the oscillation circuit of FIG. 3 is shown in FIG.
As the pulse output from each of the output units 24 to 26, the same pulse as in the case shown in FIG. 2 is output, so detailed description thereof will be omitted here.
As the pulse output from the anti-phase output units 34 to 36, the anti-phase pulse is output at the same timing as the pulse output from the output units 24 to 26.

Six pulses are continuously output from the anti-phase output units 34 to 36 to form one cycle. The pulses output from the anti-phase output units 34 to 36 have the same output timing as the pulse widths of the six pulses output from the output units 24 to 26, so the six pulses output from the output units 24 to 26 The period of the pulse and the period of the six pulses output from the antiphase output units 34 to 36 are the same.

The six pulse widths are the same. Specifically, one positive pulse and one negative pulse are output from one output unit in one cycle. The positive and negative pulses output from the opposite phase output units 34 to 36 are in opposite phase to the pulses output from the output units 24 to 26 at the same timing.
Regarding the positive / negative of the pulse in the embodiment of FIG. 3, the case where the current flows clockwise is defined as positive and the case where the current flows counterclockwise is defined as negative in FIG.

First, a positive pulse is output from the first output unit 24, and at the same time, a negative pulse is output from the antiphase first output unit 34 ((1) in FIGS. 3 and 4). Next, a negative pulse is output from the second output unit 25, and at the same time, a positive pulse is output from the antiphase second output unit 35 ((2) in FIGS. 3 and 4). Next, a positive pulse is output from the third output unit 26, and at the same time, a negative pulse is output from the antiphase third output unit 36 ((3) in FIGS. 3 and 4). Next, a negative pulse is output from the first output unit 24, and at the same time, a positive pulse is output from the antiphase first output unit 34 ((4) in FIGS. 3 and 4). Next, a positive pulse is output from the second output unit 25, and at the same time, a negative pulse is output from the antiphase second output unit 35 ((5) in FIGS. 3 and 4). Next, a negative pulse is output from the third output unit 26, and at the same time, a positive pulse is output from the antiphase third output unit 36 ((6) in FIGS. 3 and 4).

(Third embodiment)
FIG. 5 shows an embodiment in which a main ring circuit 20 in which 15 inverters are connected in a ring shape is provided with five output terminals for every three inverters.
Although not shown in FIG. 5, a total of 15 output terminals are provided for every other inverter, and 5 output terminals are provided for every 3 inverters out of the 15 output terminals. You may select and provide an output part.

Of the five output terminals, the output terminal provided between the inverter 1 and the inverter 15 is referred to as the first output terminal 41, and the output terminal provided between the inverter 3 and the inverter 4 is referred to as the second output terminal 42. The output terminal provided between the inverter 6 and the inverter 7 is referred to as a third output terminal 43, the output terminal provided between the inverter 9 and the inverter 10 is referred to as a fourth output terminal 44, and between the inverter 12 and the inverter 13. The output terminal provided in is referred to as a fifth output terminal 45.

The space between the two inverters at the output terminal 41 and the cathode of the inverter at the tip of the output terminal 42 is provided as the first output unit 51.
The space between the two inverters at the output terminal 42 and the cathode of the inverter at the tip of the output terminal 43 are provided as the second output unit 52.
The space between the two inverters at the output terminal 43 and the cathode of the inverter at the tip of the output terminal 44 is provided as the third output unit 53.
The space between the two inverters at the output terminal 44 and the cathode of the inverter at the tip of the output terminal 45 are provided as the fourth output unit 54.
The space between the two inverters at the output terminal 45 and the cathode of the inverter at the tip of the output terminal 41 is provided as the fifth output unit 55.

According to the oscillation circuit of the present embodiment, two pulses (one positive pulse and one negative pulse) are output from each of the five output units of the first output unit 51 to the fifth output unit 55 within one cycle. A total of 10 pulses make up one cycle.
After one cycle, a cycle in which 10 pulses are output is repeated.
Therefore, according to the oscillation circuit of the present embodiment, since the cycle in which 10 pulses are output is repeated, there is a possibility that data processing in the decimal system can be performed.

Further, in FIG. 5, two connection terminals are provided in parallel with each other for every three inverters of the main ring circuit 20, and the cathode at the tip of one of the one connection terminals provided in parallel is set for every three inverters. Connect by the above-mentioned connection method such as connecting between one inverter of two adjacent connection terminals, and every three inverters between the other inverters of one connection terminal provided in parallel. It may be connected to the cathode at the other end of two adjacent connection terminals.
That is, in this configuration, the output unit provided by connecting the other connection terminals to each other becomes the anti-phase output unit.

With such a configuration, two pulses (one positive pulse and one negative pulse) are output from each of the five output units provided by connecting one of the connection terminals within one cycle, for a total of ten. One cycle is composed of pulses, and at the same time, two pulses each of two pulses opposite to the pulse output from the output unit within one cycle from the five antiphase output units provided by connecting the other connection terminals to each other. (1 positive pulse, 1 negative pulse) is output, and one cycle is composed of a total of 10 pulses.

(Other embodiments)
As shown in FIG. 6, in the main ring circuit 20 in which 15 inverters are connected in a ring shape, the divisors of 15 are 1, 3, and 5, so that one output terminal is provided and three inverters are used. It is possible to configure three types of oscillation circuits provided every five inverters. An example of every three inverters is as shown in FIG.

Further, as shown in FIG. 7, when 15 output terminals are provided for every 1 inverter and the pulse width of each pulse output from 15 output units is 1, 5 for every 3 inverters. The pulse width of each pulse output from the five output units is 3, and three output terminals are provided for every five inverters to be output from the three output units. The pulse width of the pulse is 5.

Further, 15 output terminals are provided for every other inverter, and 30 pulses are output for each pulse output from 15 output units to form one cycle. Assuming that each pulse width at this time is 1, one cycle is 30.
Five output terminals are provided for every three inverters, and the pulse width of each pulse output from the five output units is 3, and 10 pulses are output to form one cycle. Since each pulse width at this time is 3, one cycle is 30.
Three output terminals are provided every five inverters, and the pulse width of each pulse output from the three output units is 5, and six pulses are output to form one cycle. Since each pulse width at this time is 5, one cycle is 30.

In this way, by providing the output terminals across several inverters, which is the number of inverters in the main ring circuit, the adjacent connection terminals are connected to each other, and when the main ring circuit goes around once, it returns to the first output terminal. , One cycle with multiple pulse outputs can be reliably defined.
Then, as described above, a plurality of circuits can be configured in which the time of one cycle is the same and different numbers of pulses are output with different pulse widths.

20 Main ring circuit 21 Output terminal 22 Output terminal 23 Output terminal 24 1st output unit 25 2nd output unit 26 3rd output unit 29 LED circuit 31 Output terminal 32 Output terminal 33 Output terminal 34 1st output unit 35 2nd output unit 36 3rd output unit 41 1st output terminal 42 2nd output terminal 43 3rd output terminal 44 4th output terminal 45 5th output terminal 51 1st output unit 52 2nd output unit 53 3rd output unit 54 4th output unit 55 5th output section

Claims (2)

A main ring circuit in which an odd number of inverters are connected in a ring shape,
It is equipped with a plurality of output circuits in which two inverters are connected in series.
The anode side of the output circuit is connected to the connection point between the inverters constituting the main ring circuit and provided as an output terminal.
Of the odd number of inverters constituting the main ring circuit, n pieces (n is a natural number of 1 or more, and the odd number is the predetermined divisor) straddling a number of inverters which are a predetermined divisor of the odd number. Between the output terminals of the quotient divided by)
The output unit is located between the connection point between the inverters of any one of the output terminals in the plurality of output terminals and the cathode at the tip of the adjacent output terminals straddling the output terminal and the predetermined divisor of the number of inverters. Provided as
The connection point between the inverters of the output terminals provided with the cathode at the tip as one end of the output unit, and the cathode at the tip of the adjacent output terminals straddling the output terminal and the predetermined number of inverters. A multi-phase oscillation circuit characterized in that a plurality of output sections are provided by providing an interval as an output section around the main ring circuit. At one connection point between the inverters constituting the main ring circuit, two output circuits are connected to each anode side to provide two output terminals.
Connection point between each inverter of the main ring circuit The connection point between the inverters of one of the two output terminals provided at one place, and the number of inverters between the output terminal and the predetermined divisor. The area between the two adjacent output terminals and the cathode at the tip of one of the output terminals is provided as an output unit.
The connection point between the inverters of the output terminals provided with the cathode at the tip as one end of the output unit, and the cathode at the tip of the adjacent output terminals straddling the output terminal and the predetermined divisor of the number of inverters. A plurality of output units are provided in the space around the main ring circuit, and n output units are provided.
The cathode at the tip of the other output terminal of the two output terminals provided at one connection point between the inverters of the main ring circuit straddles the output terminal and the number of inverters which is the predetermined divisor. The space between the inverters of the adjacent output terminals and the connection points of the inverters is provided as an anti-phase output unit.
The connection point between the inverters at the tip of the output terminal provided with the connection point between the inverters as one end of the output unit and the inverters at the adjacent output terminals straddling the output terminal and the predetermined number of inverters. 2. Oscillation circuit.

Images