JP6012072B2 - Digital demodulation circuit, digital demodulation method and digital demodulation program - Google Patents

Description

  The present invention relates to a digital demodulation circuit, a digital demodulation method, and a digital demodulation program for demodulating a modulated received signal.

  Even in a low-speed and low-capacity transmission line, communication may still be realized using a simple technique.

  For example, in the case of one-to-one communication or one-to-many (broadcast) communication, routing of a transmission signal is not necessary, and therefore, a technique related to routing is not used. In addition, a simple error detection technique such as parity check is used for error detection of the received signal on the receiving side, and advanced error detection and error such as cyclic redundancy check (CRC) are used. Corrections may not be made.

  However, even with such a simple communication method, it is necessary to suppress waveform deterioration due to the transmission path and reduce reception errors. Therefore, normally, transmission data generated by modulating a baseband signal with a modulation signal or the like is transmitted. In this case, of course, demodulation on the receiving side is necessary.

  As a technique related to such demodulation, there are techniques described in Patent Document 1 and Patent Document 2, for example. In the technique described in Patent Document 1, a phase synchronization circuit including a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) is provided, and a clock and data are reproduced from received data using the phase synchronization circuit.

  On the other hand, in the technique described in Patent Document 2, both the carrier signal and the clock are counted, and the ratio is obtained by a DAC (Digital to Analog Converter) for demodulation.

  However, in order to use these techniques, it is necessary to provide a VCO or a DAC for demodulation, which may make the configuration complicated and costly.

  Therefore, a general demodulating circuit in the case where demodulation is performed in the receiving apparatus without using these VCO and DAC will be described with reference to FIGS. FIG. 1 shows a general technology architecture. FIG. 2 shows a time chart of a general technique.

  Referring to FIG. 1, a demodulation circuit 500, which is a general demodulation circuit, includes a reception signal input terminal 51, a reception carrier detection flag generator 52, a reception carrier counter 53, a first timer 54, a clock input terminal 55, an AND circuit. 56, a second timer 57, a first rise detection circuit 58, a second rise detection circuit 59, an RS type flip-flop 60, a third rise detection circuit 61, a clock generation counter 62, a D type flip flop 63, and A reception reproduction data output terminal 65 is included.

  Further, the signal lines connecting the respective circuits shown in FIG. 1 are separately provided with symbols for identifying signals inputted / outputted through the respective signal lines. Moreover, this code | symbol is common with the code | symbol used on the time chart represented in FIG.

  A signal received by the receiving device in which the demodulation circuit 500 is incorporated is input to the reception signal input terminal 51 as a reception signal 551.

  The reception signal input terminal 51 for receiving the reception signal 551 is connected to the set terminal of the reception carrier detection flag generator 52 and the reception signal input terminal of the reception carrier counter 53.

  The output terminal of the reception carrier detection flag generator 52 is connected to the count enable signal input terminal of the reception carrier counter 53 and the reset input terminal of the first timer 54.

  The output terminal of the first timer 54 is connected to the reset input terminal of the reception carrier detection flag generator 52 and the second input terminal of the AND circuit 56, respectively.

  The output terminal of the reception carrier counter 53 is connected to the first input terminal of the AND circuit 56.

  The output terminal of the AND circuit 56 is connected to the reset input terminal of the second timer 57 and the D input terminal of the first rising detection circuit 58, respectively.

  The output terminal of the second timer 57 is connected to the D input terminal of the second rise detection circuit 59.

  The output terminal of the first rising detection circuit 58 is connected to the set input terminal of the RS type flip-flop 60. The output terminal of the second rising edge detection circuit 59 is connected to the reset input terminal of the RS type flip-flop 60.

  The output terminal of the RS type flip-flop 60 is connected to the D input terminal of the D type flip-flop 63 and the D input terminal of the third rise detection circuit 61, respectively.

  The output terminal of the third rising edge detection circuit 61 is connected to the count enable input terminal of the clock generation counter 62.

  The output terminal of the clock generation counter 62 that outputs the reception reproduction clock 564 is connected to the clock input terminal of the D type flip-flop 63. The output terminal of the D-type flip-flop 63 is connected to the reception / reproduction data output terminal 65.

  A clock 555 which is a clock of the receiving device is input to the clock input terminal 55. The clock input terminal 55 is connected to the clock input terminal of the reception carrier counter 53, the second timer 57, the three rise detection circuits 58, 59 and 61, and the clock generation counter 62, respectively.

  Next, the basic operation of the demodulation circuit 500 will be described with reference to the time chart of FIG.

  A received signal input to the demodulation circuit 500 is a signal (such as a PWM (Pulse Width Modulation) signal) that repeats a value of 0 and 1 at a predetermined cycle, and a frequency higher than a frequency corresponding to the predetermined cycle ( Preferably, a carrier signal having a frequency higher in order than the frequency corresponding to the predetermined frequency is superimposed. Alternatively, the received signal has at least approximately the above-described form by a predetermined modulation method. Therefore, when the level of the signal such as the aforementioned PWM signal is 0, the received signal is 0, and when the level of the signal such as the aforementioned PWM signal is 1, the received signal repeats 0 and 1 alternately. . The removal of the carrier signal superimposed thereon from the received signal is to restore the original signal corresponding to the signal such as the aforementioned PWM signal from the received signal.

  It is assumed that the frequency of the clock 555 is higher than the frequency of the carrier superimposed on the received signal 551. Further, the clock 555 and the carrier superimposed on the received signal 551 need not be phase-synchronized. As for the timer count value, it is assumed that the timer count value of the second timer 57 is larger than the timer count value of the first timer 54. That is, “the timer count value of the second timer 57> the timer count value of the first timer 54”.

  Further, “j” and “i” are used as codes representing the timer count value of the second timer 57, and the relationship between them is “j> i> 0”.

  When the demodulating circuit 500 receives the reception signal 551, the reception carrier detection flag generation unit 52 performs reception carrier detection, and the reception carrier detection flag 552 is changed from 0 to 1.

  The reception carrier counter 53 is in a reset state when the value of the reception carrier detection flag 552 is 0, and in this reset state, the output count value of the reception carrier counter 53 is zero. Therefore, during the period when the value of the reception carrier detection flag 552 is 0, the output count value output by the reception carrier counter 53 continues to be zero. On the other hand, when the value of the reception carrier detection flag 552 is 1, the reception carrier counter 53 counts the number of carriers superimposed on the reception signal 551 based on the clock 555 (see the reception carrier counter 553 in FIG. 2).

  The first timer 54 is reset when the reception carrier detection flag 552 is 0 (see reception carrier detection flag reset 565 in FIG. 2). On the other hand, if the reception carrier detection flag 552 is 1, the predetermined time is counted based on the clock 555 (see the first timer 554 in FIG. 2).

  The first timer 54 is in a reset state when the value of the reception carrier detection flag 552 is 0. In this reset state, the output value of the first timer 54 is zero. Therefore, during the period when the value of the reception carrier detection flag 552 is 0, the output count value output by the first timer 54 continues to be zero. On the other hand, while the value of the reception carrier detection flag 552 is 1, the first timer 54 counts a predetermined number of clocks and outputs a reception carrier detection flag reset signal having a value of 1 when the count ends. To do. The reception carrier detection flag reset signal is supplied to the reset terminal of the reception carrier detection flag generation unit 52 and the second input terminal of the AND circuit 56.

  The reception carrier detection flag generation unit 52 is set when there is a reception signal, and is reset when a reception carrier detection flag reset signal is input to the reset terminal.

  The reception carrier counter 53 sets the output signal to 1 and stops when the carrier is counted up to a predetermined number. Accordingly, when the first timer 54 outputs a reception carrier detection flag signal having a value of 1, if the reception carrier counter 53 has already counted the number of carriers to a predetermined number, the AND circuit 56 A pulse with a value of 1 is output. On the contrary, if the reception carrier counter 53 does not count the number of carriers up to a predetermined number when the first timer 54 outputs a reception carrier detection flag signal having a value of 1, the AND circuit 56 Does not output pulses.

  Therefore, by looking at the output of the AND circuit 56, it is determined whether or not the necessary number of carriers are received within a certain time corresponding to the timer count value of the first timer 54, and whether or not the carriers are continuously received. Can be determined.

  The AND circuit 56 sets the RS type flip-flop 60 through the first rising edge detection circuit 58 (see the AND output 556 and the RSFF 560 in FIG. 2). With this operation, reproduction of the received signal “0 → 1” is performed (see RSFF 560 in FIG. 2).

  Further, the AND circuit 56 becomes 1 when the number of received carriers is more than the required number within a certain time, and outputs a signal reception pulse. The output of the AND circuit 56 is a reset signal for the second timer 57 (see the AND output 556 and the second timer 557 in FIG. 2).

  Here, since the timer count value in the demodulating circuit 500 is “second timer> first timer” as described above, the second timer 57 can only count from 0 to i while receiving the carrier, and the full count. (See the second timer 557 in FIG. 2).

  When the carrier reception is completed, the reset signal of the second timer 57 disappears, so that the second timer 57 can count from 0 to j. The output of the second timer 57 resets the RS type flip-flop 60 through the second rising edge detection circuit 59 (see the second timer 557, the reset 559 and the RSFF 560 in FIG. 2). By this operation, reproduction of the received signal “1 → 0” is performed.

  Therefore, if a state where a predetermined number or more of carriers are received within a certain time corresponding to the timer count value of the first timer 54 continues, the state where the output signal of the RS type flip-flop 60 is 1 continues. On the other hand, if a state where a predetermined number of carriers are not received within a certain time corresponding to the timer count value of the first timer 54 continues for a time corresponding to the timer count value of the second timer 57, RS The output signal of the type flip-flop becomes zero.

  When the output of the RS type flip-flop 60 changes from 0 to 1, the clock generation counter 62 is activated through the third rise detection circuit 61. The activated clock generation counter 62 counts up to a count value k necessary to generate the reception reproduction clock 64, and when the count is completed, the output is changed from 0 to 1 (clock generation counter 562 in FIG. 2). And the reception reproduction clock 564).

  The D-type flip-flop 63 re-times the output of the RS-type flip-flop 60 with the clock output from the D-type flip clock generation counter 62, thereby completing the reception signal reproduction (see the RSFF 560 and the reception reproduction clock 564 in FIG. 2). ).

JP 2008-109440 A Japanese Patent Laid-Open No. 04-307810

  By using a circuit such as the demodulation circuit 500 described above, it is possible to reproduce the received signal without using a VCO or the like.

  However, a general technique algorithm such as the demodulation circuit 500 described above is difficult to understand.

  Here, it is the reason why it is considered an incomprehensible algorithm, but in general technology algorithms, execution of conditional branches to control multiple counters, continuous input of resets to counters, measurement of counts from the last reset, conditions This is because when the condition is not established, the counter must be reset, and when the condition is established, the counter must measure the count and maintain the state by the RS type flip-flop.

  Such a complex algorithm has a problem that mistakes may be mixed in the circuit design. Also in the verification, there is a problem that it is difficult to confirm all operating conditions, and there is a risk that a product will be produced without eliminating design errors.

  Accordingly, the present invention provides a digital demodulation circuit, a digital demodulation method, and a digital demodulation circuit that can implement a digital demodulation circuit of a pulse width modulated received signal on which a carrier is superimposed with a clear demodulation algorithm and a simplified architecture. The purpose is to provide a program.

  According to a first aspect of the present invention, there is provided a demodulation circuit for demodulating a reception signal that is pulse-width modulated and further superimposed on a carrier, wherein the reception signal is used as input data and has a higher frequency than the carrier. An N-bit shift registration means for shifting and storing the input data for N bits in synchronization with a clock, and a logical sum of the input data for N bits stored in the N-bit shift registration means between bits And a N-input logical sum means for obtaining a received signal from which the carrier superimposed on the received signal is removed.

  According to a second aspect of the present invention, there is provided a demodulation method performed by a demodulation circuit that demodulates a reception signal that is pulse-width modulated and further superimposed with a carrier, wherein the reception signal is input data, Shifting the input data for N bits in synchronization with a clock having a high frequency and storing it in the N-bit shift register means, and the input data for the N bits stored in the N-bit shift register means And obtaining a received signal from which the carrier superimposed on the received signal is removed by taking the logical sum of the two bits.

  According to a third aspect of the present invention, there is provided a demodulation program for causing a computer to function as a demodulation circuit that demodulates a reception signal that is pulse-width modulated and on which a carrier is superimposed. N-bit shift registration means for taking a signal as input data and shifting and storing the input data for N bits in synchronization with a clock having a frequency higher than that of the carrier; and the N-bit shift registration means stored in the N-bit shift registration means N-input logical sum means for obtaining a reception signal from which a carrier superimposed on the reception signal is removed by taking a logical sum of the input data for N bits between bits, and functioning as a demodulation circuit. A demodulation program is provided.

  According to the present invention, it is possible to realize a digital demodulation circuit for a pulse width modulated reception signal on which a carrier is superimposed with a clear demodulation algorithm and a simplified architecture.

It is a circuit diagram showing the basic composition of a general digital demodulation circuit. It is a time chart for demonstrating the basic operation | movement of a general digital demodulation circuit. It is a circuit diagram showing the basic composition of the digital demodulator circuit which is an embodiment of the present invention. It is a figure showing an example of the internal structure of the N bit shift register contained in the digital demodulation circuit which is embodiment of this invention. It is a time chart for demonstrating the basic operation | movement of the digital demodulation circuit which is embodiment of this invention.

  First, an outline of an embodiment of the present invention will be described. In the embodiment of the present invention, a pulse width modulation reception signal on which a carrier is superimposed is input to an N-bit shift register, and the carrier is removed by superimposing the output waveform of the N-bit shift register. In this embodiment, the pulse width modulation signal after carrier removal is extracted, and the reception clock is regenerated from the extracted pulse width modulation signal. Further, in this embodiment, the received signal is regenerated, that is, demodulated by retiming the pulse width modulated signal with the regenerated received clock. As a result, in this embodiment, the demodulation algorithm and the circuit configuration can be simplified as compared with a general technique.

  The above is the outline of this embodiment.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 3 is a circuit diagram showing a basic configuration of the demodulation circuit 100 according to the embodiment of the present invention. FIG. 5 is a time chart for explaining the basic operation of the demodulation circuit 100 according to the embodiment of the present invention.

  First, referring to FIG. 3, the demodulation circuit 100 includes a received signal input terminal 1, an N-bit shift register 2, a clock input terminal 3, an N input OR circuit 4, a rising edge detection circuit 5, a clock generation counter 6, a decoder 7, D-type flip-flop 8, second D-type flip-flop 9, and reception / reproduction data output terminal 11.

  Further, the signal lines connecting the respective circuits shown in FIG. 3 are separately provided with symbols, but this is for identifying signals inputted / outputted through the respective signal lines as in FIG. It is. Moreover, this code | symbol is common with the code | symbol used on the time chart represented in FIG.

  A pulse width modulated reception signal on which a carrier is superimposed, which is received by a reception device incorporating the demodulation circuit 100, is input to the reception signal input terminal 1 as a reception signal input 101. The received signal input 101 input to the received signal input terminal 1 is supplied to the D input terminal of the N-bit shift register 2 as an output of the received signal input terminal 1.

  Here, the internal configuration of the N-bit shift register 2 is shown in FIG. As shown in FIG. 4, the N-bit shift register 2 includes N D-type flip-flops 2-1 to 2-N (in the drawing, described as D-type FF) connected in series. It is out. A D input terminal 2-10 is connected to the leftmost D type flip-flop 2-1, and the received signal input 101 is input through the D input terminal 2-10. On the other hand, the output of the left D type flip-flop is connected to the D inputs of the D type flip-flops 2-2 to 2-N. Further, a clock input terminal 2-20 is connected to each of the N D type flip-flops 2-1 to 2-N, and the clock 103 is input via the clock input terminal 2-20.

  The received signal input 101 input by the leftmost D-type flip-flop 2-1 is synchronized with the clock 103 input from the clock terminal, and the right-side D-type flip-flop (D-type flip-flops 2-2 to 2-N). ). The N-bit shift register 2 has N output terminals (output terminals 2-30-1) for outputting the outputs of all D-type flip-flops (D-type flip-flops 2-1 to 2-N) in parallel. ~ 2-30-N).

  In this embodiment, the N input OR circuit 4 performs a logical sum on all N outputs (N bit shift register outputs 2 (1) to 2 (N)) of the N bit shift register 2 to remove the carrier. do. A logical sum output 104 which is an output signal of the N-input OR circuit 4 is supplied to a first input of the rising edge detection circuit 5.

  The rising edge detection circuit 5 is a differentiation circuit that detects the rising edge of the N-bit OR output 104 in synchronization with the clock input. In this embodiment, the rising detection signal 5 is extracted by detecting the rising of the output of the N-input OR circuit 4 by the rising detection circuit 5. The rising detection signal 105 that is the output of the rising detection circuit 5 is supplied to the reset signal input terminal of the clock generation counter 6.

  The clock generation counter 6 is a counter that counts in synchronization with the clock input using the rising detection signal 105 of the rising detection circuit 5 as a reset signal. A clock generation counter output 106 that is an output of the clock generation counter 6 is supplied to an input terminal of the decoder 7.

  The decoder 7 is a decoder that decodes the clock generation counter output 106 that is the output of the clock generation counter 6. The decoder output 107 which is the output of the decoder 7 is supplied to the D input terminal of the first D type flip-flop 8. Specifically, the decoder 7 outputs a pulse having a level of 1 when the count value output from the clock generation counter 6 reaches a predetermined value. The predetermined value to be compared with the count value will be described later in the description of the operation.

  The first D-type flip-flop 8 synchronizes the decoder output 107, which is the output of the decoder 7, with the clock, and uses the output of the decoder 7 after the synchronization as the reception reproduction clock 110. The reception reproduction clock 110 that is the output of the first D type flip-flop 8 is supplied to the D input terminal of the second D type flip-flop 9.

  In this embodiment, the second D-type flip-flop 9 retimes the N-bit logical sum output 104 with the reception reproduction clock 110. Here, the N-bit OR output 104 to be retimed is a signal obtained by removing the superimposed carrier from a signal such as a PWM signal whose value repeats 0 and 1 in a predetermined cycle. The signal after this retiming is the output of the second D-type flip-flop 9. The output of the second D-type flip-flop 9 is supplied as reception reproduction data 110 to the reception reproduction data output terminal 11.

  The reception reproduction data 111 output from the second D type flip-flop 9 is output to the outside from the reception reproduction data output terminal 11.

  A clock 103 that is a clock of the receiving apparatus is input to the clock input terminal 3. The clock 103 input from the clock input terminal 55 includes a clock input terminal of the N-bit shift register 2, a clock input terminal of the rising edge detection circuit 5, a clock input terminal of the clock generation counter 6, and two D-type flip-flops. 8 and 9 are supplied to the clock input terminals. The clock 103 may be generated by a receiving device in which the demodulation circuit 100 is incorporated, but may be generated by another method. For example, a third device other than the reception device and the transmission device may generate a clock and supply it to the demodulation circuit 100.

  Next, the basic operation of the demodulation circuit 100 will be described with reference to the time chart of FIG.

  In FIG. 5, the received signal input 101 is a pulse width modulated received signal, and the received signal changes from High to Low in one cycle regardless of whether the value of the transmission data is “0” or “1”. doing. More specifically, the timing of changing from Low to High does not change in the cycle, and the timing of changing to High or Low depends on whether the value of the transmission data is “0” or “1”. It fluctuates with. Whether the transmission data is “0” or “1” is identified by looking at the duty ratio. Here, the duty ratio is a ratio of the high level period to one period of the PWM signal, and is calculated by [high level period / period of PWM signal] × 100%.

  In FIG. 5, an enlarged representation of the received signal 101 is shown as the received signal input 101 (enlarged 1). As shown in the waveform of the received signal input 101 (enlarged 1), the carrier is superimposed on the section where the level of the PWM signal is High. A waveform obtained by further enlarging the superimposed carrier is represented as a received signal input 1 (enlarged 2) in the lower stage of the received signal input 101 (enlarged 1).

  The jitter will be described using the received signal input waveform of FIG. Here, received signal input waveforms for five data are shown. At the timing of the left end of each arrow, the signal is switched from LOW to a hatched portion (actually, a portion where LOW and HIGH are repeated by a modulation signal). The timing of this switching is determined by whether the data value is 0 or 1 Since it does not fluctuate regardless of whether it is, it does not have jitter. On the other hand, the portion where the signal is switched from the hatched portion to the LOW varies depending on whether the data value is 0 or 1 (specifically, if the data value is 0, the timing is faster). In other words, if the value of the data is 1, the timing is delayed), and thus there is jitter.

  Here, as a premise in this explanation, the length of the period in which the carrier value continues to be “0” as shown by the enlarged 2 in the third row from the top of FIG. 5 is supplied from the clock input terminal 3. It is assumed that there are m clocks 103 of the receiving apparatus. M is an arbitrary natural number determined by design. In this case, N, which is the number of stages of the shift register, is determined so as to satisfy the relationship “N ≧ m”. By setting the value of N so that this relationship is satisfied, the level of the output of the N-input OR circuit can be fixed to 1 during a period in which the received signal level is not 0 but 0 and 1 are repeated. It becomes like this. In other words, this relationship means that the value of N is determined such that the time difference between the data before N-bit shift and the data after N-bit shift is larger than the half period of the carrier. You can also.

  Further, in the present embodiment, the synchronization between the carrier of the transmission signal and the clock of the receiving device does not matter. That is, the carrier and the clock may be synchronized or may not be synchronized. In FIG. 5, the clock of the receiving apparatus is illustrated as a clock 103.

  In the present embodiment, the received signal input 101 (enlargement 2) is taken into the N-bit shift register 2 in synchronization with the clock 103. As shown from the input signal taken as N-bit shift register output 102 (N-bit shift register outputs 102 (1), (2)... (N) are shown in FIG. 5). N types of signals are generated. Each of the N types of signals is delayed in phase by one clock.

  An N-bit shift register output 102, which is N-bit data obtained by combining 1-bit output data of each of the N registers included in the N-bit shift register 102, is input to an N-input OR circuit 4 that is an OR circuit. The logical sum data obtained by the above is supplied to the rising edge detection circuit 5. Here, the logical sum data of the N-input OR circuit 4 is represented in FIG.

  As described above, the length of the section where the carrier level is “0” is equivalent to m clocks in terms of the number of clocks 103. Further, as described above, when m is compared with N, which is the number of stages of the N-bit shift register 2, the value of N is selected so that a relationship of N ≧ m is established. Therefore, during the period in which the PWM signal is high, the level of the logical sum data 104 is also continuously high. On the other hand, during the period when the PWM signal is low, the level of the logical sum data 104 is also continuously low. Therefore, only the carrier can be removed from the PWM signal on which the carrier is superimposed, thereby restoring the PWM signal.

  By modifying this embodiment, it is possible to cope with the case where the polarity of the entire received signal or the polarity of the PWM portion of the received signal is opposite to that described above. Specifically, for example, a logic inversion circuit (NOT circuit) is inserted into each of N connection lines between the N-bit shift register 2 and the N-input OR circuit 4. That is, each of the connection lines connecting each of the N output terminals (output terminals 2-30-1 to 2-30-N) shown in FIG. 4 and the N input terminals of the N-input OR circuit 4 A logic inversion circuit is inserted in By doing this, even if the polarity of the PWM signal is opposite to that described above, it is possible to remove only the carrier from the PWM signal on which the carrier is superimposed.

  In this case, as will be described later, when the received data is reproduced based on the reception reproduction clock, the output to the second D-type flip-flop 9 needs to be logically inverted. Therefore, a logic inverting circuit is also inserted between the N-input OR circuit 4 and the second D-type flip-flop.

  As another modification of the present embodiment, the PWM signal from which the carrier has been removed can be modified so as to be directly used for controlling some device. That is, the configuration subsequent to the rise detection circuit 5 may be omitted, and the logical sum data 104 may be directly used for applications such as control of the power supply circuit and motor drive control. In this explanation, however, the logical sum data 104 is supplied to the rising edge detection circuit 5 and used as described below.

  Next, the rise detection circuit 5 generates a rise detection signal 105 at the rise timing of the logical sum data 104. The generated rising edge detection signal 105 is output to the clock generation counter 6.

  The clock generation counter 6 is reset by the input rising edge detection signal 105 and starts counting with the clock of the receiving device after the reset.

  When the count value of the clock generation counter 6 reaches a predetermined value, the decoder 7 outputs a pulse whose level is 1. This pulse is used as a reception reproduction clock 110. As a result, it is possible to generate a reception reproduction clock having an edge after a predetermined time elapses from an edge on the side having no jitter due to pulse width modulation of the reception signal 101 from which the carrier is removed. Here, the predetermined value to be compared with the count value is a count value corresponding to a half time of the period of the PWM signal. However, although there is a balance with the modulation index or the modulation degree, it may be slightly deviated from the range in which a demodulation error does not occur.

  When the OR data 104 from which the carrier is removed by the reception reproduction clock 110 is retimed, reception reproduction data 111 is obtained.

  Note that the use of the reception / reproduction data 111 obtained in the present embodiment is not particularly limited. Therefore, the demodulation circuit 100 according to the present embodiment can be incorporated in an arbitrary receiving device realized by an arbitrary device. It is.

  With the above operation, the present embodiment can perform digital demodulation on a pulse width modulated reception signal on which a carrier is superimposed while simplifying a demodulation algorithm and a circuit configuration.

  The embodiment described above has many effects as described below.

  In the present embodiment described above, the received signal is stored in the N-bit shift register with a clock having a higher frequency than the carrier superimposed on the received signal. The shift register clock may be synchronized with the received signal. Then, the output of the N-bit shift register is used as an input of N-bit logical sum, and the received waveform is synthesized. By synthesizing in this way, the carrier can be removed, and the first effect is obtained that an output with only pulse width modulation is obtained.

  In the present embodiment described above, the rising edge of the N-bit OR output is detected, and the N-bit OR output is retimed after a predetermined time has elapsed from the rising signal. This produces a second effect that a demodulated received signal can be obtained.

  In addition, the present embodiment provides a simplified architecture with a clearer demodulation algorithm compared to a general technique. The third feature is that a clear algorithm and a simplified architecture enable the operation to be easily grasped even when a circuit other than the designer looks at the corresponding circuit, and that verification can be easily confirmed under all operating conditions, thereby reducing design errors. The effect of.

  Moreover, although the above-described embodiment is a preferred embodiment of the present invention, the scope of the present invention is not limited only to the above-described embodiment, and various modifications are made without departing from the gist of the present invention. Implementation in the form is possible.

  For example, a part or all of each logic circuit included in the demodulation circuit 100 can be realized by a programmable LSI (Large Scale Integration) such as an FPGA (Field-programmable gate array) or a DSP (Digital Signal Processor). It is. Similarly, some or all of the logic circuits included in the demodulation circuit 100 can be realized by an arithmetic processing unit such as a CPU (Central Processing Unit) performing arithmetic processing based on software.

  That is, the demodulation circuit described above can be realized by hardware, software, or a combination thereof. The digital demodulation method performed by the above demodulation circuit can also be realized by hardware, software, or a combination thereof. Here, “realized by software” means realized by a computer reading and executing a program.

  The program may be stored using various types of non-transitory computer readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD- R, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (random access memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  As an example of utilization of this embodiment, a power supply circuit (camera, mobile phone, game device, network device) and the like can be cited.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Supplementary Note 1) A demodulation circuit that demodulates a received signal that is pulse width modulated and further superimposed with a carrier,
N-bit shift registration means for using the received signal as input data and shifting and storing the input data for N bits in synchronization with a clock having a frequency higher than that of the carrier;
N-input logical sum means for obtaining a received signal from which the carrier superimposed on the received signal is removed by taking the logical sum of the input data for the N bits stored in the N-bit shift register means between bits. When,
A demodulation circuit comprising:

(Supplementary note 2) The demodulation circuit according to supplementary note 1,
A reception reproduction clock generating means for generating a reception reproduction clock having an edge after elapse of a predetermined time from an edge having no jitter due to the pulse width modulation of the reception signal from which the carrier is removed;
D-type flip retiming means for performing demodulation corresponding to the pulse width modulation by retiming the reception signal from which the carrier has been removed at the edge of the reception reproduction clock;
The demodulator circuit further comprising:

(Additional remark 3) It is a demodulation circuit of Additional remark 2, Comprising:
The reception reproduction clock generation means includes
Edge detection means for detecting an edge on the side having no jitter due to the pulse width modulation of the received signal with the carrier removed;
A counter that measures the time since the edge detection means detected the edge;
Decoding means for generating the edge of the reception reproduction clock when the time measured by the counter reaches a predetermined time;
A demodulation circuit comprising:

(Supplementary note 4) The demodulation circuit according to any one of supplementary notes 1 to 3,
The demodulation circuit according to claim 1, wherein the value of N is determined such that a time difference between data before N-bit shift and data after N-bit shift is larger than a half period of the carrier.

(Supplementary note 5) The demodulation circuit according to any one of supplementary notes 1 to 4,
The N-input logical sum means is superimposed on the received signal by taking a logical sum of the data obtained by logically inverting each of the N-bit input data stored in the N-bit shift register means. As a received signal with the carrier removed,
The D type flip retiming means performs demodulation corresponding to the pulse width modulation by retiming a signal obtained by logically inverting the reception signal from which the carrier has been removed at the edge of the reception reproduction clock.
A demodulation circuit characterized by that.

(Supplementary Note 6) A demodulation method performed by a demodulation circuit that demodulates a reception signal that is pulse-width modulated and further superimposed with a carrier,
Using the received signal as input data, shifting the input data for N bits in synchronization with a clock having a frequency higher than that of the carrier, and storing it in N-bit shift register means;
Obtaining a reception signal from which the carrier superimposed on the reception signal is removed by taking a logical OR of the input data for the N bits stored in the N-bit shift registration means between the bits;
The demodulation method characterized by having.

(Supplementary note 7) The demodulation method according to supplementary note 6, wherein
A reception reproduction clock generation step of generating a reception reproduction clock having an edge after a predetermined time has elapsed from an edge on the side having no jitter due to the pulse width modulation of the reception signal from which the carrier has been removed;
A D-type flip retiming step for performing demodulation corresponding to the pulse width modulation by retiming the reception signal from which the carrier has been removed at the edge of the reception reproduction clock; and
The demodulation method further comprising:

(Supplementary note 8) The demodulation method according to supplementary note 7,
The reception reproduction clock generation step includes:
An edge detection step for detecting an edge on the side having no jitter due to the pulse width modulation of the received signal from which the carrier has been removed; and
A counter that measures the time since the edge detection means detected the edge;
A decoding step of generating the edge of the reception reproduction clock when a time measured by the counter reaches a predetermined time;
The demodulation method characterized by having.

(Supplementary note 9) The demodulation method according to any one of supplementary notes 6 to 8,
The demodulation method according to claim 1, wherein the value of N is determined such that a time difference between data before N-bit shift and data after N-bit shift is larger than a half period of the carrier.

(Supplementary note 10) The demodulation method according to any one of supplementary notes 6 to 9,
In the N-input logical sum step, a logical sum of data obtained by logically inverting each of the N bits of the input data stored in the N-bit shift register means is superposed on the received signal by taking between the bits. As a received signal with the carrier removed,
In the D-type flip retiming step, demodulation corresponding to the pulse width modulation is performed by retiming a signal obtained by logically inverting the reception signal from which the carrier is removed at the edge of the reception reproduction clock.
The demodulation method characterized by the above-mentioned.

(Supplementary Note 11) A demodulation program for causing a computer to function as a demodulation circuit that demodulates a reception signal that is pulse-width modulated and on which a carrier is superimposed.
N-bit shift registration means for using the received signal as input data and shifting and storing the input data for N bits in synchronization with a clock having a frequency higher than that of the carrier;
N-input logical sum means for obtaining a received signal from which the carrier superimposed on the received signal is removed by taking the logical sum of the input data for the N bits stored in the N-bit shift register means between bits. When,
A demodulating program that functions as a demodulating circuit.

(Supplementary note 12) The demodulation program according to supplementary note 11,
A reception reproduction clock generating means for generating a reception reproduction clock having an edge after elapse of a predetermined time from an edge having no jitter due to the pulse width modulation of the reception signal from which the carrier is removed;
D-type flip retiming means for performing demodulation corresponding to the pulse width modulation by retiming the reception signal from which the carrier has been removed at the edge of the reception reproduction clock;
A demodulation program further comprising:

(Supplementary note 13) The demodulation program according to supplementary note 12,
The reception reproduction clock generation means includes
Edge detection means for detecting an edge on the side having no jitter due to the pulse width modulation of the received signal with the carrier removed;
A counter that measures the time since the edge detection means detected the edge;
Decoding means for generating the edge of the reception reproduction clock when the time measured by the counter reaches a predetermined time;
A demodulation program comprising:

(Supplementary note 14) The demodulation program according to any one of supplementary notes 11 to 13,
The demodulation program according to claim 1, wherein the value of N is determined so that a time difference between data before N-bit shift and data after N-bit shift is larger than a half period of the carrier.

(Supplementary note 15) The demodulation program according to any one of Supplementary notes 11 to 14,
The N-input logical sum means is superimposed on the received signal by taking a logical sum of the data obtained by logically inverting each of the N-bit input data stored in the N-bit shift register means. As a received signal with the carrier removed,
The D type flip retiming means performs demodulation corresponding to the pulse width modulation by retiming a signal obtained by logically inverting the reception signal from which the carrier has been removed at the edge of the reception reproduction clock.
A demodulation program characterized by that.

  The present invention can be used to demodulate a signal that is pulse-width modulated and modulated by a carrier or a signal that approximates it.

DESCRIPTION OF SYMBOLS 1 Reception signal input terminal 2 N bit shift register 2-1 to 2-ND D type flip-flop 2-10 D input terminal 2-20 Clock input terminal 2-30-1 to 2-30-N Output terminal 3 Clock input terminal 4 N-input OR circuit 5 Rising detection circuit 6 Clock generation counter 7 Decoder 8 First D-type flip-flop 9 Second D-type flip-flop 11 Reception reproduction data output terminal 51 Reception signal input terminal 52 Reception carrier detection flag generation unit 53 Reception carrier counter 54 First timer 55 Clock input terminal 56 AND circuit 57 Second timer 58 First rise detection circuit 59 Second rise detection circuit 60 RS type flip-flop 61 Third rise detection circuit 62 Clock generation counter 63 D-type flip-flop 65 reception Playback data output terminal

Claims (7)

A demodulation circuit that demodulates a reception signal that is pulse-width modulated and on which a carrier is superimposed,
N-bit shift registration means for using the received signal as input data and shifting and storing the input data for N bits in synchronization with a clock having a frequency higher than that of the carrier;
N-input logical sum means for obtaining a received signal from which the carrier superimposed on the received signal is removed by taking the logical sum of the input data for the N bits stored in the N-bit shift register means between bits. When,
A demodulation circuit comprising: The demodulation circuit according to claim 1,
A reception reproduction clock generating means for generating a reception reproduction clock having an edge after elapse of a predetermined time from an edge having no jitter due to the pulse width modulation of the reception signal from which the carrier is removed;
D-type flip retiming means for performing demodulation corresponding to the pulse width modulation by retiming the reception signal from which the carrier has been removed at the edge of the reception reproduction clock;
The demodulator circuit further comprising: The demodulation circuit according to claim 2, wherein
The reception reproduction clock generation means includes
Edge detection means for detecting an edge on the side having no jitter due to the pulse width modulation of the received signal with the carrier removed;
A counter that measures the time since the edge detection means detected the edge;
Decoding means for generating the edge of the reception reproduction clock when the time measured by the counter reaches a predetermined time;
A demodulation circuit comprising: The demodulation circuit according to any one of claims 1 to 3,
The demodulation circuit according to claim 1, wherein the value of N is determined such that a time difference between data before N-bit shift and data after N-bit shift is larger than a half period of the carrier. The demodulation circuit according to any one of claims 1 to 4,
The N-input logical sum means is superimposed on the received signal by taking a logical sum of the data obtained by logically inverting each of the N-bit input data stored in the N-bit shift register means. As a received signal with the carrier removed,
The D type flip retiming means performs demodulation corresponding to the pulse width modulation by retiming a signal obtained by logically inverting the reception signal from which the carrier has been removed at the edge of the reception reproduction clock.
A demodulation circuit characterized by that. A demodulation method performed by a demodulation circuit that demodulates a reception signal that is pulse width modulated and further superimposed with a carrier,
Using the received signal as input data, shifting the input data for N bits in synchronization with a clock having a frequency higher than that of the carrier, and storing it in N-bit shift register means;
Obtaining a reception signal from which the carrier superimposed on the reception signal is removed by taking a logical OR of the input data for the N bits stored in the N-bit shift registration means between the bits;
The demodulation method characterized by having. A demodulation program for causing a computer to function as a demodulation circuit that demodulates a reception signal that is pulse-width modulated and on which a carrier is superimposed, the computer comprising:
N-bit shift registration means for using the received signal as input data and shifting and storing the input data for N bits in synchronization with a clock having a frequency higher than that of the carrier;
N-input logical sum means for obtaining a received signal from which the carrier superimposed on the received signal is removed by taking the logical sum of the input data for the N bits stored in the N-bit shift register means between bits. When,
A demodulating program that functions as a demodulating circuit.

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