JP4362407B2 - Digital noise filter - Google Patents

Description

  The present invention relates to a digital noise filter that can be used in an interface that requires high-speed communication.

  FIG. 8 is a system configuration diagram of a conventional digital noise filter (see, for example, Patent Document 1). As shown in FIG. 8, the digital noise filter 100 includes a shift register 101 including n stages of flip-flops (hereinafter referred to as FFs) FF1 (1) to FF1 (n), and an output signal S1 of each FF. The output of the external output signal 104 is determined by determining whether all the values of (1) to S1 (n) coincide with the H level or by determining the values of the output signals S1 (1) to S1 (n) by majority. And a determination circuit 102 for determining the level.

  Hereinafter, the operation of the digital noise filter 100 will be described. First, the external input signal 103 is input from the input terminal “in” to the first stage FF 1 (1) of the shift register 101. Then, the output signal S1 (1) of FF1 (1) is input to FF1 (2). Such a shift is repeatedly performed from FF1 (2) to FF1 (n) in the shift register 101.

  On the other hand, output signals S1 (1) to S1 (n) of the FF1 (1) to FF1 (n) are further input to the determination circuit 102. In the determination circuit 102, the output level of the external output signal 104 is determined based on the values of the output signals S1 (1) to S1 (n), and the external output signal 104 is output from the output terminal out.

  Here, when the determination circuit 102 is a coincidence circuit for determining the coincidence of signal values, when it is determined that all the values of the output signals S1 (1) to S1 (n) are at the H level, H The level external output signal 104 is output from the output terminal out. When it is determined that the values of the output signals S1 (1) to S1 (n) are not all at the H level, the L level external output signal 104 is output from the output terminal out. As a result, the noise below the period calculated by multiplying the cycle of the operation clock 105 supplied to the FF1 (1) to FF1 (n) in the shift register 101 by the number n of FFs is removed.

  When the determination circuit 102 is a majority circuit that takes a majority decision of signal values, among the values of the output signals S1 (1) to S1 (n), the number of H levels is ½ of the number n of FF stages. If the above is satisfied (the number of H levels ≧ n / 2), the H level external output signal 104 is output from the output terminal out, and the number of H levels is less than ½ of the number n of FFs (the number of H levels < n / 2), the L level external output signal 104 is output from the output terminal out. As a result, noise of a period equal to or less than ½ of the period calculated by multiplying the period of the operation clock 105 supplied to FF1 (1) to FF1 (n) in the shift register 101 by the number n of FFs is removed. Is done.

  9 is a time chart showing the operation of the digital noise filter, FIG. 10 is a diagram showing the output value of each FF stage and the output value of the digital noise filter when the judgment circuit is a coincidence circuit, and FIG. It is a figure which shows the output value of each FF stage in the case of being a circuit, and the output value of a digital noise filter. The case where the number of FF stages of the shift register 101 is “15” will be described below.

  When an input signal as shown in FIG. 9 is input to the shift register 101 from the input terminal in, the output signals S1 (1) to S1 (15) in each cycle of the operation clock 105 of FF1 (1) to FF (15). ) Are sequentially shifted to subsequent FFs, and the output level of the external output signal 104 is determined by the determination circuit 102 every cycle of the operation clock 105.

  When the determination circuit 102 is a coincidence circuit, as shown in FIG. 10, when all the values of the output signals S1 (1) to S1 (15) coincide with the H level, the determination circuit 102 outputs an H level. The external output signal 104 is output. In the input signal shown in FIG. 9, since the values of the output signals S1 (1) to S1 (15) all coincide with the H level in the 27th cycle, the external output signal 104 becomes the H level. Thereby, the noise of the external input signal 103 is removed.

When the determination circuit 102 is a majority circuit, the number of H levels among the values of the output signals S1 (1) to S1 (15) is the FF of the shift register 101 as shown in FIG. When the number of stages is more than ½ of 15 stages (“8” or more in FIG. 9), the determination circuit 102 outputs an external output signal 104 of H level. In the input signal shown in FIG. 9, since there are eight H level signals among the values of the output signals S1 (1) to S1 (15) in the thirteenth cycle, the external output signal 104 becomes H level. Thereby, the noise of the external input signal 103 is removed.
JP-A-5-145380 (5th page, FIG. 2)

  However, in the above-described digital noise filter 100, the noise width that can be removed is fixed depending on the number of FF stages of the shift register 101. Therefore, the performance of the digital noise filter 100 depends on the number of FF stages of the shift register 101. For this reason, in order to change the noise width that can be removed, it is necessary to change the circuit, resulting in an increase in cost.

  The present invention has been made in view of such a point, and the object of the present invention is to enable setting of a noise removal width from the outside and to obtain a necessary signal component according to the purpose. There is to do.

That is, the invention of claim 1 is a shift register having a plurality of stages of flip-flops;
A register for setting the noise reduction width as a register setting value;
A selector unit that selects one of the output signals of each flip-flop in the shift register based on the register setting value;
The input signal within a period set by the register setting value based on a determination result of a match or mismatch between the value of the output signal of the selected flip-flop and the value of the input signal input to the shift register A counter unit that counts the number of H levels of
And a determination circuit for determining an output level of the external output signal based on the count value of the counter unit and the register setting value.

  Therefore, according to the present invention, one of the output signals of each FF stage in the shift register can be selected and output by the selector unit according to the register setting value that determines the noise removal width. The period of noise removal width is determined by the number of FF stages and the period of the operation clock supplied to the FF. Also, during this period, the counter unit counts up, counts down, or holds the count value based on the determination result of the match or mismatch between the output signal of the selected FF stage and the input signal input to the shift register. Is called.

  Since the count value is obtained by counting the number of H levels in the set period, by comparing the count value with the register set value, the cycle value shorter than that in the set period is obtained. Noise can be removed.

  As described above, according to the first aspect of the present invention, it is possible to set a noise removal width from the outside, and a necessary signal component can be obtained according to the purpose by changing a register setting value. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or its application.

  FIG. 1 is a system configuration diagram of a digital noise filter according to the present invention. In FIG. 1, 201 is a shift register composed of n-stage flip-flops FF2 (0) to FF2 (n-1) to which an operation clock 206 having a period T [sec] is supplied, and 205 is a register for noise removal width. A register to be set as a set value, 202 is a selector unit that selects one of output signals S2 (0) to S2 (n-1) of each FF stage of the shift register 201 based on the register set value, and 203 is A logic operation unit 204 that determines whether the value of the output signal of the FF stage selected by the selector unit 202 matches the value of the output signal S2 (0) of the first stage FF of the external input signal 103; The operation clock 206 is set based on the enable signal EN calculated by the logic operation unit 203 and the output signal S2 (0) of the first stage FF of the external input signal 103. A counter unit 207 that counts the number of H levels of S2 (1) to S2 (register setting value) in a period St (St = T × register setting value) calculated by multiplying the number of selected FF stages, The determination circuit determines the output level of the digital noise filter 200 based on the count value Cnt counted by the counter unit 204 and the register setting value.

  As shown also in FIG. 2, when the enable signal EN is 1 (the judgment of the logic operation unit 203 is coincident), the counter unit 204 counts up the count value when S2 (0) is H level, and counts down when the enable signal EN is L level. If EN is 0 (the logic operation unit 203 does not agree), the count is held to determine the H level period Cnt within the period of the noise width to be removed, which is the basis for majority decision.

  Further, the determination circuit 207 compares a half value of the input register setting value with the count value Cnt, and Cnt ≧ (register setting value) / 2 (rounds up when the register setting value is an odd number). When the condition is satisfied, the determination circuit 207 outputs an H level. As a result, it is possible to remove noise having a period of T × (register set value) / 2 (when the register set value is an odd number, the register set value / 2 is discarded).

  FIG. 3 is a configuration diagram when the digital noise filter of the present invention is mounted on a clock / data line of an I2C (Inter Integrated Circuit) interface in a system LSI for digital TV.

  The system LSI 401 includes an I2C interface 402, and a clock and data line 406 is connected to the I2C interface 402 and the NTSC encoder 403 outside the system LSI 401. The data clock of the I2C interface 402 is connected to the logic operation unit 405 of the I2C interface 402 via the digital noise filter 404.

  Next, a circuit configuration of the digital noise filter 404 is shown in FIG. The digital noise filter 404 has a shift register 301 composed of 32 stages of FFs, and based on the values set in the register 305, the output signals S3 (0) to S3 (31) of the 32 stages of FFs. A selector unit 302 that selects one of them, a logic operation unit 303 that determines whether the value of the output signal of the selector unit 302 matches the value of the input signal FF3 (0), and the output of the logic operation unit 303 Is the enable signal EN, and the counter unit 304 that counts up, counts down, or holds the count value according to the level of the input signal FF3 (0), and the count value output from the counter unit 304 is set in the register 305 And a determination circuit 307 that outputs an H level when it is greater than ½ of the measured value and an L level when it is smaller. . The value set in the register 305 determines a noise removal width.

  FIG. 5 is a timing chart of the digital noise filter 404 of the present invention. 3 and 4, the external input signal 103 is input from the NTSC encoder 403 connected to the system LSI 401 to the FF3 (0) of the digital noise filter 404 via the data line 406, and the register 305 Let us consider a case where “15 (0xF)” is set in.

  When “15” is set in the register 305 and the operation clock 306 supplied to the FF3 (0) to FF3 (15) of the shift register 301 is 50 MHz (period 20 ns), the operation clock 306 is set to the register setting value “15”. The noise removal determination is performed in the period (period 300 ns) calculated by multiplying.

  First, S3 (0), which is the output signal of the first stage of the FF of the external input signal 103, is compared with S3 (15) selected based on the register setting value in the selector unit 302, and the value match or mismatch is logically determined. This is determined by the calculation unit 303.

  As shown in FIG. 6, the counter unit 304 counts up, counts down, or holds the count value based on the enable signal EN output from the logic operation unit 303 and the signal level of S3 (0). Done.

  Further, the determination circuit 307 compares the count value counted by the counter unit 304 with a half value of the register set value set by the register 305, and the count value is 1/2 of the register set value. When the value is larger than the value of H, the H level is output.

  Specifically, when the register setting value is “15”, the H level is output from the determination circuit 307 when the count value is “8” or more, and 1 in a cycle of 300 ns (15 cycles). A signal component having a period of 140 ns (7 cycles) or less, which is / 2 or less, can be removed as noise.

  In this case, in the thirteenth cycle, the count value becomes “8”, which is larger than half of the register setting value “15”, and the determination circuit 307 outputs the H level. Thereby, it is removed as noise with a period of 140 ns or less.

  Further, when the register set value is “4”, S3 (4) is output from the selector unit 302, and each FF3 (1) as shown in FIG. 7 in the period of 4 cycles (80 ns) of the operation clock 306. ) To FF3 (4) output signal H level is counted by the counter unit 304, and when the count value becomes “3”, it exceeds “2” which is ½ of the register set value. The determination circuit 307 outputs an H level. As a result, a signal component of 40 ns or less that is two cycles of the operation clock 306 can be removed, and a signal from which noise is removed is output from the determination circuit 307.

  As described above, according to the present embodiment, the noise width that can be removed can be changed by changing the register setting value of the register. As a result, the noise characteristics can be tuned for each set using the system LSI, and malfunctions can be prevented.

  As described above, in the digital noise filter, the present invention provides a highly practical effect that the noise width that can be removed can be changed by changing the register setting value. The above availability is high.

It is a system block diagram of the digital noise filter of this invention. It is a figure which shows the operation | movement of the logic operation part and counter part of the digital noise filter of this invention. It is a block diagram at the time of mounting the digital noise filter in this embodiment in an I2C interface. It is a circuit block diagram of the digital noise filter in this embodiment. It is a time chart figure showing operation of a digital noise filter in this embodiment. It is a figure which shows the output value of each FF stage in case a register setting value is "15", and a count value. It is a figure which shows the output value of each FF stage in case a register setting value is "4", and a count value. It is a system block diagram of the conventional digital noise filter. It is a time chart figure which shows the operation | movement of the conventional digital noise filter. It is a figure which shows the output value of each FF stage in case the determination circuit of the conventional digital noise filter is a coincidence circuit, and the output value of a digital noise filter. It is a figure which shows the output value of each FF stage, and the output value of a digital noise filter in case the determination circuit of the conventional digital noise filter is a majority circuit.

Explanation of symbols

200 Digital noise filter 201 Shift register 202 Selector unit 203 Logic operation unit 204 Counter unit 205 Register 206 Operation clock 207 Determination circuit Sn (0) to Sn (n) Output signal FFn (0) to FFn (n) of each FF of the shift register Each FF in the shift register

Claims (2)

A shift register having a plurality of flip-flops;
A register for setting the noise reduction width as a register setting value;
A selector unit that selects one of the output signals of each flip-flop in the shift register based on the register setting value;
The input signal within a period set by the register setting value based on a determination result of a match or mismatch between the value of the output signal of the selected flip-flop and the value of the input signal input to the shift register A counter unit that counts the number of H levels of
A digital noise filter comprising: a determination circuit that determines an output level of an external output signal based on a count value of the counter unit and a register setting value. In claim 1,
The digital noise filter, wherein the determination circuit is configured to determine an output level of an external output signal based on the count value and a value half of the register setting value.

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