TW200522336A - Substrate structure integrated with passive component - Google Patents
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200522336 五發明說明(1) '【發明所屬之技術領域】 本發明係有關於一種可承置被動元件之半導體承載板 結構,尤指一種整合收納有多數被動元件於半導體構裝用 之承載板中之模組化結構。 【先前技術】 隨著電子產業的蓬勃發展,電子產品亦逐漸邁入多功 能、高性能的研發方向。為滿足半導體裝置高積集度( Integration)以及糕支型4匕(Miniaturization)的封裝需 求,半導體裝置上之電子元件及電子電路之密度必須高集 ' g化,因此,為提昇或穩定電子產品的電性功能,即需在 半導體裝置上整合有例如電阻元件(Resistors) 、電容 元件(Capacitors)以及電感元件(Inductors)等被動 元件(Pass i ve component) 〇 以目前而言,無論是覆晶式(F 1 i p c h i p)、球柵陣 列式(BGA)、或者是以打線式(Wire bonding)為主之半 導體裝置,通常係先於基板表面形成有圖案化導電線路, 然後於封裝前將用於消除雜訊或作電性補償之被動元件加 入該基板,並將該等被動元件電性連接至半導體晶片,藉 此使得所封裝之半導體晶片符合電性特性之要求。 · 而一般習知技術係將該些被動元件安置於基板上未被 半導體晶片所佔據之多餘佈局面積上,如美國專利第 5,6 9 6,0 3 1、5,9 0 5,6 3 9及6,3 2 0,7 5 7號等即為此種實施方 式。該等美國專利中係使用一高密度多晶片互連(Η 1 gh density multichip interconnect, HDMI)板作為夾置件200522336 Five invention descriptions (1) '[Technical field to which the invention belongs] The present invention relates to a semiconductor carrier board structure capable of supporting passive components, and more particularly to a carrier board for integrating semiconductor components into a semiconductor carrier. Modular structure. [Previous technology] With the vigorous development of the electronics industry, electronic products have gradually entered the direction of multi-function and high-performance research and development. In order to meet the packaging requirements of semiconductor devices with high integration and miniaturization, the density of electronic components and electronic circuits on semiconductor devices must be high. Therefore, in order to improve or stabilize electronic products, Electrical functions, that is, passive components such as Resistors, Capacitors, and Inductors must be integrated on the semiconductor device. At present, no matter whether it is a flip chip (F 1 ipchip), ball grid array (BGA), or wire bonding semiconductor devices, usually patterned conductive lines are formed on the substrate surface before being used in packaging. Passive components for eliminating noise or electrical compensation are added to the substrate, and the passive components are electrically connected to the semiconductor chip, so that the packaged semiconductor chip meets the requirements of electrical characteristics. · Generally known technology is to place the passive components on the substrate without being occupied by the semiconductor chip, such as U.S. Patent No. 5,6 9 6,0 3 1,5,9 0 5,6 3 9 and 6, 3 2 0, 7 5 7 and the like are such embodiments. These US patents use a high-density multichip interconnect (晶片 1 gh density multichip interconnect, HDMI) board as a clip.
]7405*S.ptci 第6頁 200522336 五、發明說明(2) (Interposer),以由該HDMI板夾設於被動元件(或主動 元件)與積體電路之間。 然而’由於此種佈設方式係利用基板區域以載接被動 元件,必須增加可選擇為一般印刷電路板之基板的佈局面 積,因而需要以較大尺寸之基板來實施,如此將會使得整 體之封裝尺寸較大。而隨著半導體封裝件高性能之要求, 被動元件之佈設數量將相對地遽增,而令該基板表面必須 同時容納多數半導體晶片以及大量被動元件,迫使封裝件 體積增大,也同時令製程更加地複雜。 而且,該些被動元件係分別接置至基板上,不僅造成 增加線路佈設(R 〇 u t a b i 1 i t y)與製程之複雜性,更使得 整體之封裝製程具有較大之複雜度,而不合乎成本效益。 再者,若被動元件及基板其中一者有損壞時,則整個裝置 將報廢而無法使用,因而導致製造成本之提高以及產品信 賴性問題。 同時,為避免諸如該等被動元件阻礙該基板與多數銲 接墊間之電性連結等問題,傳統上多將該等被動元件安置 於基板之角端位置或半導體晶片接置區域外之基板額外佈 局面積上。惟,限定被動元件之設置位置將縮小基板表面 線路佈局之靈活性,而考量銲接墊位置則將導致該等被動 元件佈設數量受到侷限。 為避免習知電路板表面之佈局性限制問題並進一步滿 足縮小電路板空間之需求,亦有人提出於多層電路板層間 安置膜狀被動元件之建議,如美國專利第5,6 8 3,9 2 8及] 7405 * S.ptci Page 6 200522336 V. Description of the Invention (2) (Interposer) The HDMI board is sandwiched between the passive component (or active component) and the integrated circuit. However, because this layout method uses the substrate area to carry passive components, the layout area of the substrate that can be selected as a general printed circuit board must be increased, so it needs to be implemented with a larger substrate, which will make the overall package Larger size. With the high performance requirements of semiconductor packages, the number of passive components will increase relatively, so that the substrate surface must accommodate most semiconductor wafers and a large number of passive components at the same time, forcing the size of the package to increase and also making the process more Land is complicated. Moreover, these passive components are separately connected to the substrate, which not only causes an increase in the complexity of the circuit layout and manufacturing process, but also makes the overall packaging process more complicated, which is not cost-effective. . Furthermore, if one of the passive components and the substrate is damaged, the entire device will be scrapped and unusable, resulting in an increase in manufacturing costs and product reliability issues. At the same time, in order to avoid problems such as the passive components hindering the electrical connection between the substrate and most of the bonding pads, traditionally, the passive components are usually placed at the corners of the substrate or outside the semiconductor wafer placement area. Area. However, limiting the placement of passive components will reduce the flexibility of circuit layout on the surface of the substrate, and considering the placement of solder pads will cause the number of such passive components to be limited. In order to avoid the problem of the layout limitation of the circuit board surface and further meet the needs of reducing the space of the circuit board, some people have also proposed the placement of film-shaped passive components between the layers of the multilayer circuit board, such as US Patent No. 5, 6 8 3, 9 2 8 and
17405全懋.ptd 第7頁 200522336 五、發明說明(3) 6,(] 5 5,1 5 1號等揭示在多層電路板製程中於形成一新疊層 前,先在一有機絕緣層表面以網印(P I" i n t i n g)及/或光 阻姓刻(Photoresist-etching)等方式形成電阻被動元 件。 惟,於多層電路板層間安置膜狀被動元件雖可避免習 知電路板表面之佈局性限制問題,但其製程繁瑣、複雜, 同時,因該被動元件係安置於於電路板層間,因此針對不 同需求之如電阻值與電容值等電性特性時,即必須重新設 計堆疊該多層電路板,造成製造成本的大幅提升,亦會產 #物料管理的困擾與材料庫存成本的增加。此種被動元件 之整合方式,將使得基板之整體結構及其所需製程具有較 大之複雜度而不符合成本效益。 因此,在現今電子產品要求多功能及高電性之趨勢下 ,當持續追求半導體裝置上之電子元件及電子電路之密度 高集積化時,現行之半導體封裝能力已面臨無法滿足此一 趨勢之窘況。如何在提供有效數量之被動元件於半導體封 裝單元及電子裝置中,以提昇電子產品之電性功能,而又 不致影響該半導體封裝單元及電子裝置之線路佈局性及製 程與庫存成本之大幅增加,實為目前亟待解決之課題。 ❿發明内容】 鑒於以上所述習知技術之缺點,本發明之主要目的在 於提供一種可承置被動元件之半導體承載板結構,利用一 簡單製程以整合收納有多數被動元件於半導體構裝用之承 載板中,俾供結合基板及封裝製程而直接形成可作電性導17405 全懋 .ptd Page 7 200522336 V. Description of the invention (3) 6, () 5 5, 1 5 1 etc. reveals that before forming a new stack in the multilayer circuit board process, a surface of an organic insulating layer is first formed. Resistive passive components are formed by screen printing (PI) and / or Photoresist-etching. However, the placement of film-shaped passive components between the layers of a multilayer circuit board can avoid the familiar layout of the circuit board surface. However, because the passive component is placed between the layers of the circuit board, it is necessary to redesign the multilayer circuit when the electrical characteristics such as resistance and capacitance are different for different requirements. Board, resulting in a significant increase in manufacturing costs, will also produce troubles in material management and increase in material inventory costs. This integration of passive components will make the overall structure of the substrate and the required process have a greater complexity. It is not cost-effective. Therefore, in the current trend of electronic products requiring multi-function and high electrical properties, it is necessary to continue to pursue the confidentiality of electronic components and electronic circuits on semiconductor devices. At the time of high integration, the current semiconductor packaging capabilities have faced a dilemma that cannot meet this trend. How to provide an effective number of passive components in semiconductor packaging units and electronic devices to enhance the electrical functions of electronic products without affecting The substantial increase in circuit layout and manufacturing process and inventory costs of the semiconductor packaging unit and electronic device is a problem to be solved at present. 目前 Summary of the Invention In view of the shortcomings of the conventional technology described above, the main purpose of the present invention is to provide a A semiconductor carrier board structure capable of supporting passive components, using a simple process to integrate and house most passive components in a carrier board for semiconductor assembly, and directly forming a conductive substrate for combining substrates and packaging processes.
17405 全®:.ptd 第8頁 200522336 五、發明說明(4) 接之被動元件,以提供承載半導體之電性設計需求。 本發明之另一目的在於提供一種可節省製造成本之可 承置被動元件之半導體承載板結構。 本發明之再一目的在於提供一種可增加半導體封裝基 板線路佈局靈活性之可承置被動元件之半導體承載板結構 〇 為達成上揭及其他目的,本發明之可承置被動元件之 半導體承載板結構係包括:一支承板,具有一上表面及一 相對之下表面;以及複數個被動元件,係設置於該支承板 之任一表面,並且形成有電極以供導通。另可於該支承板 之下表面接設有一散熱片,以提供較佳之散熱效率,俾將 半導體承載板結構模組化,以提供承載半導體之電性設計 要求。 該被動元件可選擇以已製備完成之被動元件直接黏著 於該支承板之任一表面或該表面之凹部(Cavity)中,亦 或選擇以燒結被動元件材料及直接製成被動元件之任一方 式,於該支承板之任一表面或該表面之凹部中形成被動元 件。而形成於該被動元件上之電極則可選擇位於該被動元 件表面之同一側或不同側,端視該被動元件之類型及該類 型之被動元件設置於該支承板上之方式而定。 以陶瓷型被動元件而言,該陶瓷型被動元件係可藉由 表面黏著之方式上一層黏著層而黏著至該支承板上,或是 以燒結之方式黏著至該支承板上。當該支承板為金屬材質 時,該陶瓷型被動元件可設於該支承板之任一表面或該表17405 All®: .ptd Page 8 200522336 V. Description of the Invention (4) Passive components connected to provide the electrical design requirements for carrying semiconductors. Another object of the present invention is to provide a semiconductor carrier board structure that can save manufacturing costs and can accommodate passive components. Yet another object of the present invention is to provide a semiconductor carrier board structure capable of supporting passive components that can increase the flexibility of the circuit layout of a semiconductor package substrate. To achieve the disclosure and other purposes, the semiconductor carrier board of the present invention can accommodate passive components. The structure system includes: a support plate having an upper surface and a relatively lower surface; and a plurality of passive elements, which are arranged on any surface of the support plate and formed with electrodes for conduction. A heat sink can be connected to the lower surface of the support board to provide better heat dissipation efficiency. The semiconductor carrier board structure is modularized to provide electrical design requirements for the carrier semiconductor. The passive component can be directly adhered to any surface of the support plate or a cavity in the surface (Cavity) of the prepared passive component, or any method of sintering the passive component material and directly forming the passive component. A passive element is formed in any surface of the support plate or in a concave portion of the surface. The electrodes formed on the passive element may be located on the same side or different sides of the surface of the passive element, depending on the type of the passive element and the manner in which the type of passive element is disposed on the support plate. In the case of ceramic passive components, the ceramic passive components can be adhered to the support plate by an adhesive layer on the surface, or sintered to the support plate. When the support plate is made of metal, the ceramic-type passive component may be provided on any surface of the support plate or the surface of the support plate.
7405全懋.ptd 第9頁 200522336 五ι發明說明(5) 面冬凹部中,形成於該被動元件上之電極則可選探 被動兀件表面之同一側或不同側;當該支承板 位於該 板時,該陶莞型被動元件可設於該支承板之任—~免支承 表面之凹部中,但由於陶瓷支承板不能導電,故^ =或該 被動元件之電極僅可選擇位於該被動元件表面之=陶曼型 以晶片型被動元件而言,該晶片型被動元件仑,。 表面黏著之方式上一層黏著層而黏著至該支承板藉由 支承板為金屬或陶瓷之任一材質時,該晶片型 。當該 設於該支承板之任一表面或該表面之凹部中。 凡件可 •以直接形成被動元件材料至前述支承板上之被動开杜 而言’該種被動元件係可設於該支承才反之任一表φ : 面之凹部中。當欲將被動元件材料直接形成至該支承 & 面上時,可塗佈一層被動元件材料,亦或藉由濺鍍(、 Sputtering)、電鑛(Electroplating)或化學氣相沉積 (Chenncal vapor deposition)等方式沈積被動元件材、 料於該支承板上,並藉由圖案化製程以於該支承板上形成 所需之被動元件;當然亦可將被動元件材料直接形成^該 支承板之凹部中。其中’當該支承板為金属材質時,此種 被動元件上之電極則可選擇形成於該被動元件表面之同_ 鲁或不同側;當該支承板為陶曼材質時,則僅4選擇位於 該被動元件表面之同一側。 另可於該接置有被動元件之支承板上形成一絕緣 並於該絕緣層中形成有圖案化線路,肖使該圖荦化 以電性導接至接置於該支承板上之被動元件之電極',以提7405 全懋 .ptd Page 9 200522336 Description of the invention (5) In the surface winter recess, the electrodes formed on the passive element can optionally detect the same side or different sides of the surface of the passive element; when the support plate is located in the In the case of a plate, the ceramic passive component can be placed in the recess of the support plate. The ceramic support plate cannot conduct electricity, so the electrode of the passive component can only be located in the passive component. Surface = Taoman type In terms of a chip-type passive element, the chip-type passive element is the same. When the surface is adhered, an adhesive layer is adhered to the support plate. When the support plate is made of any one of metal or ceramic, the wafer type is used. When it is provided in any surface of the support plate or in a concave portion of the surface. All the parts can be passive passive openings that directly form the passive component material to the aforementioned support plate. ‘The passive component can be set in the recess of any surface φ: face of the support. When the passive element material is to be formed directly on the support & surface, a layer of passive element material can be coated, or by sputtering, electroplating, or chemical vapor deposition (Chenncal vapor deposition) ) And other methods to deposit passive component materials on the support plate, and use a patterning process to form the required passive components on the support plate; of course, the passive component materials can also be directly formed in the recess of the support plate. . Wherein, when the support plate is made of metal, the electrodes on the passive component can be formed on the same side or different sides of the surface of the passive component; when the support plate is made of Taurman, only 4 options are located The same side of the passive element surface. In addition, an insulation can be formed on the support plate on which the passive components are connected, and a patterned circuit is formed in the insulation layer, so that the figure can be electrically connected to the passive components connected to the support plate. Electrode 'to mention
]7405*®.ptd] 7405 * ®.ptd
200522336 五、發明說明(6) 供承載半導體之電性設計要求。此外,亦可於該絕緣層中 形成有至少一開口 ,以供接置有例如半導體晶片等電子元 件。 該支承板復可選擇於其中形成有一承載電子元件之開 口 ,並可於未設有被動元件之表面連設一散熱元件,使該 半導體承載板得以藉由該支承板上的被動元件調整其所供 承載半導體之電性設計,並藉由該散熱片提供半導體裝置 更佳之散熱效率,俾有效提升半導體裝置之電性與散熱性 功能。 由於本案之可承置被動元件之半導體承載板結構僅需 進行一簡單製程,即可將被動元件設置於可承置被動元件 之半導體承載板中。如此一來,可將被動元件直接形成於 半導體承載板,以提供承載半導體之電性設計需求,而且 可結合習知相關之支承板及封裝製程,將有形成被動元件 之支承板與電子元件、散熱元件等結合,不僅可應用現有 增層(Build-up)或疊層(Lamination)等技術以堆疊一 層或多層電路結構,更可應用於球柵陣列式、覆晶式及打 線式之半導體封裝結構中。 因此,本案之可承置被動元件之半導體承載板結構, 製程簡易且可同時省去製造基板及封裝製程為配合形成被 動元件所需之製程,以解決習知技術之缺失,更因製程簡 化而可節省製造成本,俾使半導體封裝基板之線路佈局靈 活性提昇。 以下係藉由特定的具體實施例說明本發明之實施方式200522336 V. Description of the invention (6) Electrical design requirements for supporting semiconductors. In addition, at least one opening may be formed in the insulating layer for receiving electronic components such as a semiconductor wafer. The support board can optionally have an opening for carrying electronic components formed therein, and a heat dissipation element can be connected to the surface without the passive element, so that the semiconductor carrier board can adjust its position by the passive element on the support board. Provides electrical design for carrying semiconductors, and provides better heat dissipation efficiency of semiconductor devices through this heat sink, effectively improving the electrical and heat dissipation functions of semiconductor devices. Since the semiconductor carrier board structure capable of supporting passive elements in this case only needs a simple process, the passive element can be set in the semiconductor carrier board capable of supporting passive elements. In this way, passive components can be directly formed on the semiconductor carrier board to provide the electrical design requirements for carrying the semiconductor, and combined with the related supporting board and packaging processes, there will be supporting boards and electronic components that form passive elements, The combination of heat dissipation components can not only use existing build-up or lamination technologies to stack one or more layers of circuit structures, but also be applied to ball grid array, flip-chip, and wire-type semiconductor packages. Structure. Therefore, the semiconductor carrier board structure that can accommodate passive components in this case has a simple manufacturing process and can simultaneously eliminate the need for manufacturing substrates and packaging processes to cooperate with the formation of passive components to solve the lack of conventional technologies and further simplify the manufacturing process. It can save the manufacturing cost and increase the flexibility of the circuit layout of the semiconductor package substrate. The following is a description of specific embodiments of the present invention through specific embodiments.
Π405 全®.ptd 第11頁 200522336 五、發明說明(7) ’ 4 4此技#之人士可由本說明書所揭示之内容輕易地瞭 解本發明之其他優點與功效。本發明亦可藉由其他不同的 具體實施例加以施行或應用,本說明書中的各項細節亦可 基於不同觀點與應用’在不悖離本發明之精神下進行各種 修飾與變更。 【實施方式】 以下之貫施例係進一步詳細說明本發明之觀點,但並 .非以任何觀點限制本發明之範疇。又本發明之圖式僅為簡 單說明,並非依實際尺寸描繪,亦即未反應出相關構成之 1 _際尺寸,先予敘明。 請參閱第1 A至第1 G圖,係為本發明之可承置被動元件 之半導體承載板結構1第一實施例之剖面示意圖。如第1 A 圖所示’係先提供一支承板1 1,其具有一上表面丨i a及一 相對之下表面1 1 b。如第1 B圖所示,該承載板結構1主要包 括有該支承板1 1以及複數個設置於該支承板1 1之上表面 1 1 a之被動元件1 3,當然本發明之被動元件1 3並不以設置 於支承板1 1之上表面1 1 a為限,其亦可依實際需求將被動 元件1 3接置於該支承板1 1之下表面1 1 b。 如第1 B圖所示,係選擇以已製備完成之被動元件1 3直 、籲黏著於該支承板1 1上。該被動元件1 3可選擇為表面黏著 式(Surface mounted technology, SMT)被動元件或晶 片型被動元件。其中該支承板之材質可為金屬或陶瓷。 於本實施例中,該被動元件丨3可選擇為諸如電容、電 阻或電感之被動元件1 3,並以例如表面黏著技術之方式固Π405 Quan®.ptd Page 11 200522336 V. Description of the Invention (7) ′ 4 4 This technology # can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications' without departing from the spirit of the present invention. [Embodiments] The following examples are provided to further explain the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way. In addition, the drawings of the present invention are only for simple description, and are not drawn according to actual dimensions, that is, the dimensions of the relevant components are not reflected, and they will be described first. Please refer to FIGS. 1A to 1G, which are schematic cross-sectional views of the first embodiment of the semiconductor carrier board structure 1 capable of supporting passive components according to the present invention. As shown in Fig. 1A ', a support plate 1 1 is first provided, which has an upper surface 丨 i a and a relatively lower surface 1 1 b. As shown in FIG. 1B, the supporting plate structure 1 mainly includes the supporting plate 11 and a plurality of passive elements 1 3 arranged on the upper surface 1 1 a of the supporting plate 1 1. Of course, the passive element 1 of the present invention 3 is not limited to being disposed on the upper surface 1 1 a of the support plate 1 1, and it can also place the passive component 13 on the lower surface 1 1 b of the support plate 1 1 according to actual needs. As shown in FIG. 1B, the passive component 1 3 that has been prepared is selected to be straight and adhered to the support plate 11. The passive component 1 3 can be a surface-mounted technology (SMT) passive component or a wafer-type passive component. The material of the support plate may be metal or ceramic. In this embodiment, the passive element 3 can be selected as a passive element 1 3 such as a capacitor, a resistor, or an inductor, and is fixed by, for example, a surface bonding technology.
17405全懋.ptd 第12頁 200522336 · _____—__—---- —-- ------------- 五、發明說明(8) 設至該支承板11之上表面113上。如圖所示,該被動元件 1 3與該支承板1 1之間係以一層黏著層1 5彼此黏接,於該被 動元件1 3未與該支承板1 1黏接之表面上則形成有電極1 3 a 0 其中,雖本實施例中係以形成於該被動元件1 3上表面 (即未與該支承板1 1黏接之表面)之電極1 3 a為例作說明 者,該電極1 3 a則係形成於遠被動元件1 3之同側表面上, 但應注意的是,當該支承板1 1為金屬支承板時,此種被動 元件1 3上之電極1 3 a可選擇形成於該被動元件1 3表面之同 一側或不同侧;當該支承板1 1之材質為陶瓷時,則僅可選 擇位於該被動元件1 3表面之同一側。因此,該電極1 3 a亦 可選擇形成於該被動元件1 3之不同側表面上,而非侷限於 本實施例中所述者。 此外,如第1 C圖所示,係於該支承板Π上選擇接置有 陶瓷型被動元件1 3,其中該支承板之材質可為金屬或陶瓷 ,該被動元件1 3可選擇以諸如低溫共燒陶瓷(Low temperature cofired ceramic, LTCC)技術、南溫燒結 方式或其他適當技術而燒結(Fuse)形成於該支承板1 1之 上表面 1 1 a上。 再者,於本實施例中,亦可以直接形成被動元件材料 至該支承板1 1上,其中該支承板之材質可為金屬或陶瓷, 該被動元件1 3係選擇設於該支承板U之上表面1 1 a上。當 欲將被動元件材料直接形成至該支承板1 1之上表面1 1 3上 時,可由塗佈一層被動元件材料於該支承板U之上表面Π a17405 全懋 .ptd Page 12 200522336 · _____ — __ —-—-------------- 5. Description of the invention (8) Set to the upper surface of the support plate 11 113 on. As shown in the figure, the passive element 13 and the support plate 11 are adhered to each other with an adhesive layer 15. On the surface of the passive element 13 that is not adhered to the support plate 11, there is formed Electrode 1 3 a 0 Although the electrode 1 3 a formed on the upper surface of the passive element 13 (that is, the surface not bonded to the support plate 11) is taken as an example in this embodiment, the electrode 1 3 a is formed on the same side surface of the far passive element 13, but it should be noted that when the support plate 11 is a metal support plate, the electrode 1 3 a on this passive element 13 can be selected Formed on the same side or different sides of the surface of the passive element 13; when the material of the support plate 11 is ceramic, only the same side of the surface of the passive element 13 can be selected. Therefore, the electrodes 1 a may also be formed on different side surfaces of the passive element 13 instead of being limited to those described in this embodiment. In addition, as shown in FIG. 1C, a ceramic-type passive component 13 is selectively connected to the support plate Π. The material of the support plate may be metal or ceramic, and the passive component 13 may be selected such as low temperature. A co-fired ceramic (Low temperature cofired ceramic, LTCC) technology, a South temperature sintering method, or other appropriate technology is used to form a sintering (Fuse) on the upper surface 1 1 a of the support plate 1 1. Furthermore, in this embodiment, the passive element material can also be directly formed on the support plate 11, wherein the material of the support plate can be metal or ceramic, and the passive element 13 is selected to be provided on the support plate U. Upper surface 1 1 a. When the passive element material is to be formed directly on the upper surface 1 1 3 of the support plate 1, a layer of passive element material may be coated on the upper surface of the support plate U a
17405全懋.ptd 第13頁 200522336 五、發明說明(9) 後,由諸如曝光、姓刻或雷射修整(user trimming) 等圖本化製程而形成所需之被動元件13於該支承板u之上 表面广。而且’當該支承板11為金屬支承板時,此種被 動元件u上之電極13a則可選擇形成於該被動元件13表面 之同側或不同側’當該支承板))為陶瓷日寺,則僅可選擇 位於該被動元件1 3表面之同一側。 該被動元件1 3係可潠擇以雷阳从L, 材料之被動元件材料所;:者€容材料或電感 ,, ^ ^ ^ ^ 右该破動元件13為電阻元 1,則使用選自係如銀粉(SlWer p〇wder )或碳顆粒 .Carbon partlcle)散布於樹脂中’氧化釕(Ru〇2)與 玻璃粉末散布在一黏結劑(Binder)塗佈再固化而形成’ 或如錄絡(Ni-Cr)、錄磷(Nl_P)、鎳錫(Ni_Sn)、鉻 鋁(Cr —A1)、及氮化鈦(TaN)合金等電阻材料,而將該 電阻材料沈積形成於該支承板1丨之上表面i丨&上。 右鑪被動兀件1 3為電容元件,則可使用選自介電常數 大之高介電電容材料。此種高介電電容材料係由諸如高分 子材料、陶瓷材料、陶瓷粉末填充之高分子及類似材料, 可例如為鈦酸鋇(Barium-titanate )、鈦酸锆鉛 ^Lead-Zlrconate-tltanate)、無定形氫化碳(Am〇rph〇us • drogenated carbon)、或其粉末散佈於黏結劑(Binder )或鈦酸鏍鋇(Barium strontium titanate )以塗佈形 成厚膜電容材料或以化學氣相沉積(CVD)形成薄膜電容 材料’於該支承板1 1之上表面1 1 3上。 方该被動元件1 3為電感元件,首先形成一軟磁性膜於 第14頁 200522336 五、發明說明(10) 一導電结層之表面上—螺 # + , · , . $ ^疋型線圈,該軟磁性膜可以濺鍍 、方疋堂(spin coating)式心σ 气鉍卿r μ 7 f . 一 p刷等方式形成。係如猛-鋅鐵 乳磁體(Mn-Zn ferrite)、μ r . λ ^ 錄-盆-辞鐵氧磁體(Ni-Μη-Ζη ferrite)或四氧化三鐵Γ 、magnetite)等,可以被濺鍍沈積 (sputter - deposited) ·:、: - λ χ ’而添加以鐵氧磁體-樹脂貧材 (f e r r i t e - r e s i n pasta θϊ 、一 > P te)則可以印刷方式沈積。其中該 鐵氧磁體_樹脂貧材可為好 马在孟—鋅鐵氧磁體(Mn-Zn ferrite) 粉末散佈在樹脂中者。可w、私 .. ·、 J 以濺鍍、旋塗(spin coating)或17405 全懋 .ptd Page 13 200522336 V. After the description of the invention (9), the required passive components 13 are formed on the support plate 13 by a process such as exposure, last name engraving, or laser trimming (13). The surface is wide. And 'when the support plate 11 is a metal support plate, the electrode 13a on the passive element u can be formed on the same side or different side of the surface of the passive element 13' when the support plate)) is a ceramic nichi, Only the same side of the surface of the passive component 13 can be selected. The passive component 1 3 can be selected from the passive component materials of Leiyang, L: material or inductance, ^ ^ ^ ^ Right The broken component 13 is a resistance element 1, then use the selected element Such as silver powder (SlWer powder) or carbon particles. Carbon partlcle) is dispersed in the resin 'ruthenium oxide (Ru〇2) and glass powder is dispersed in a binder (Binder) coating and then solidified' or as recorded (Ni-Cr), phosphorous (Nl_P), nickel-tin (Ni_Sn), chromium-aluminum (Cr-A1), and titanium nitride (TaN) alloy and other resistance materials, and the resistance material is deposited and formed on the support plate 1丨 Upper surface i 丨 & The right furnace passive element 13 is a capacitor element, and a high dielectric capacitor material selected from a large dielectric constant can be used. Such high-dielectric capacitor materials are made of polymers such as polymer materials, ceramic materials, ceramic powders, and the like, and can be, for example, barium-titanate, lead zirconium titanate (Lead-Zlrconate-tltanate) , Amorphous hydrogenated carbon (Am〇rph〇us • drogenated carbon), or its powder is dispersed in a binder (Binder) or barium strontium titanate (Barium strontium titanate) to coat to form a thick film capacitor material or chemical vapor deposition (CVD) A thin film capacitor material is formed on the upper surface 1 1 3 of the support plate 1 1. The passive element 13 is an inductive element. First, a soft magnetic film is formed on page 14 200522336 V. Description of the invention (10) On the surface of a conductive junction layer—spiral # +, ·,. $ ^ 疋 type coil, the The soft magnetic film can be formed by sputtering, spin coating, core σ, air bismuth, r μ 7 f. 1 p brush, and the like. Such as Mn-Zn ferrite magnets, μ r. Λ ^ Record-pot-ci ferrite magnets (Ni-Μη-Zη ferrite), ferric oxide Γ, magnetite, etc., can be splashed Sputter-deposited (sputter-deposited) · :,--λ χ 'and the addition of ferrite-resin pasta (ferrite-resin pasta θϊ, a > P te) can be deposited by printing. The ferrite magnet_resin lean material can be a good one. Mn-Zn ferrite powder is dispersed in the resin. W, private .., J by sputtering, spin coating, or
印刷等方式形成。係如銳—雜讲$ , 7 r * , X 蜮鲜鐵乳磁體(Μη-Zn ferrite)、 鎳-錳-鋅鐵氧磁體(Nl—Mn —Zn ferrite)或四氧化三鐵 (magnetite)專’可以被錢鍍沈積(spUtter — deposited )’而添加以鐵氧磁體—樹脂膏材(paste )則可以印刷方式沈積。其中該鐵氧磁體-樹脂膏材可為 猛-鋅鐵氧磁體(Mn-Zn f err i te)粉末散佈在樹脂中者。 再利用一有機:絕緣層作為黏著層將上述螺旋型線圈形成於 該支承板11表面。 以上’於該支承板丨丨表面直接作出該被動元件丨3之技 術手段係為習知者,於此不再予贅述。 上述陶兗燒結型與直接形成被動元件之電極位置,與 該支承板之材質有關,當該支承板1丨之材質為陶瓷時,僅 可選擇位於該被動元件丨3表面之同一側,如第1〔圖所示, 當該支承板1 1為金屬支承板時,此種被動元件1 3上之電極 1 3 a可選擇形成於該被動元件1 3表面之同一側(如第丨〔圖 所不)或不同側(如第丨D圖所示)。Formed by printing. Departments such as Rui—Miscellaneous $, 7 r *, X 蜮 fresh iron milk magnet (Μη-Zn ferrite), nickel-manganese-zinc ferrite magnet (Nl-Mn-Zn ferrite) or ferric oxide (magnetite) 'SpUtter — deposited' can be deposited, and ferrite magnets — resin paste (paste) can be deposited by printing. The ferrite magnet-resin paste may be a powder of manganese-zinc ferrite (Mn-Zn ferrite) powder dispersed in the resin. The above-mentioned spiral coil is formed on the surface of the support plate 11 by using an organic: insulating layer as an adhesive layer. The technical means for directly making the passive element 3 on the surface of the support plate 丨 is known, and will not be repeated here. The above ceramic sintered type is related to the position of the electrode directly forming the passive element, which is related to the material of the support plate. When the material of the support plate 1 丨 is ceramic, it can only be selected on the same side of the surface of the passive element 丨1 [shown, when the support plate 11 is a metal support plate, the electrode 1 3 a on such a passive element 13 may optionally be formed on the same side of the surface of the passive element 13 (as shown in FIG. No) or different sides (as shown in Figure 丨 D).
17405全想· ptd 第15頁 200522336 五、發明說明(11) ^如1 E至1 G圖所示,本發明之被動元件1 3並不以設置於 支承板1 1之表面為限,其亦可依實際需求將被動元件1 3接 置於該支承板1 1之表面凹部1 1 0。 本發明之可承置被動元件之半導體承載板結構係包括 一金屬或陶瓷支承板1 1以及複數個形成於該支承板中之被 動元件1 3。其中於該支承板1 1之上表面1 1 a係形成有複數 個凹部1 1 0,而該被動元件1 3可為電容元件、電阻元件或 電感元件,並且可選擇形成於該凹部1 1 0中。形成於該凹 部1 1 0中之被動元件1 3係可藉由表面黏著技術(如第1 E圖 示),燒結技術或直接形成方式(如第1 F圖所示)。當 欲將被動元件材料直接埋設至該支承板1 1表面之凹部1 1 0 中時,係可利用例如電鍍、化學氣相沉積或塗佈等方式將 被動元件材料埋於該支承板1 1表面之凹部1 1 0中,以於該 凹部1 1 0中形成所需之被動元件。 當然,形成於該被動元件1 3上之電極1 3 a亦可選擇形 成於該被動元件1 3之同一側或不同側上,端視該支承板1 1 之類型而定,當該支承板1 1為金屬支承板時,此種被動元 件1 3上之電極1 3 a則可選擇形成於該被動元件1 3表面之同17405 All thoughts · ptd Page 15 200522336 V. Description of the invention (11) ^ As shown in Figures 1 E to 1 G, the passive element 13 of the present invention is not limited to the surface provided on the support plate 11 and it also The passive component 13 can be connected to the surface recess 1 1 0 of the support plate 1 1 according to actual needs. The semiconductor carrier board structure capable of supporting passive components of the present invention includes a metal or ceramic support plate 11 and a plurality of driven components 13 formed in the support plate. A plurality of recesses 1 1 0 are formed on the upper surface 1 1 a of the support plate 1 1, and the passive element 13 may be a capacitor element, a resistance element or an inductance element, and may be formed in the recess 1 1 0. in. The passive components 1 3 formed in the recesses 1 10 can be formed by surface adhesion technology (as shown in Fig. 1E), sintering technology or direct formation (as shown in Fig. 1F). When the passive component material is to be directly buried in the recessed portion 1 10 on the surface of the support plate 11, the passive component material can be buried in the surface of the support plate 11 by, for example, plating, chemical vapor deposition or coating. In the recessed part 1 10, a desired passive element is formed in the recessed part 10. Of course, the electrodes 1 3 a formed on the passive element 13 may also be formed on the same side or different sides of the passive element 13. The end depends on the type of the support plate 1 1. When 1 is a metal support plate, the electrode 1 3 a on the passive element 1 3 can be formed on the surface of the passive element 13.
17405全®· ptd 第16頁 200522336 五、發明說明(12) 承板11中,而可直接形成作為電性導接之被動元件13。隨 後,更可應用現有增層或疊層等技術以堆疊一層或多層電 路結構,並將此可承置被動元件之半導體承載板結構1可 應用於球柵陣列式、覆晶式及打線式之半導體封裝結構中 〇 此外,亦可在該支承板未接置有被動元件之表面’黏 著一散熱片(未圖示),以提升後續半導體構裝之散熱效 率。 請參閱第2A至第2F圖以及第2A,至第2F,圖,係為本發 明之可承置被動元件之半導體承載板結構第二實施例之剖 面示意圖。 如第2 A至第2 C圖所示,本發明第二實施例之可承置被 動元件之半導體承載板結構與第一實施例所揭示者大致相 同,其不同處係在該支承板1 1表面接置有被動元件1 3後’ 再於該承置有被動元件1 3之支承板1 1上形成一絕緣層2 0, 並可利用圖案化製程以在該絕緣層中形成有圖案化線路結 構2 1 ’並使該線路結構2 1得以電性導通至該被動元件丨3之 電極1 3 a。其中,該絕緣層2 〇之材質可為有機材質、纖維 強化(F 1 b e r - r e i n f 〇 r c e d )有機材質或顆料強化(P a r t i c 1 ε-πιηί orced) 有機 材質等 所構成 ,例 如環 氧樹脂 ( Epoxy resin)聚乙醯胺(p〇iyimide)、順雙丁稀二酸醯亞胺/ 二氮拼(Bismaleimide triazine-based)樹脂、氰酯 (Cyanate ester)等。該線路結構2丨之製作,可先於該 絕緣層2 0上形成一金屬導電層,例如為一銅層,復利用°蝕17405 All® · ptd Page 16 200522336 V. Description of the invention (12) In the support plate 11, the passive element 13 can be directly formed as an electrical connection. Subsequently, it is possible to apply existing technologies such as layering or stacking to stack one or more layers of circuit structures, and the semiconductor carrier board structure 1 that can support passive components can be applied to ball grid array, flip chip and wire bonding In the semiconductor package structure, in addition, a heat sink (not shown) may be affixed to the surface of the support plate where the passive components are not connected, so as to improve the heat dissipation efficiency of subsequent semiconductor structures. Please refer to Figs. 2A to 2F and Figs. 2A to 2F, which are schematic cross-sectional views of the second embodiment of the semiconductor carrier board structure capable of bearing passive components of the present invention. As shown in FIGS. 2A to 2C, the structure of the semiconductor carrier plate capable of receiving passive components in the second embodiment of the present invention is substantially the same as that disclosed in the first embodiment, and the difference lies in the support plate 1 1 After the passive components 13 are connected on the surface, an insulating layer 20 is formed on the support plate 11 on which the passive components 13 are placed, and a patterning process can be used to form a patterned circuit in the insulating layer. The structure 2 1 ′ allows the circuit structure 21 to be electrically connected to the electrode 1 3 a of the passive element 丨 3. Wherein, the material of the insulating layer 2 can be made of organic material, fiber reinforced (F 1 ber-reinf rced) organic material, or particle reinforced (P artic 1 ε-πιηί orced) organic material, such as epoxy resin. (Epoxy resin) poiyimide, bis-succinimide / bisismeimide triazine-based resin, cyanate ester, etc. The circuit structure 2 丨 can be manufactured by forming a metal conductive layer, such as a copper layer, on the insulating layer 20, and then reuse the etch
]7405全懋· ptd 第17頁] 7405 全懋 · ptd Page 17
7 1. .C 200522336 五、發明說明(13) 刻彳支術形成一線路圖案化之線路層,該線路層亦可利用電 鍍方法於圖案化之電鍍阻層中形成細緻電路,此外,該線 路結構非以一層為限。該支承板1 1可為金屬或陶瓷材料, 且被動元件1 3則可以黏著、燒結或直接作成等方式形成於 其表面。 如第2 A ’至第2 C ’圖所示之可承置被動元件之半導體承 載板結構,係與第2 A至第2 C圖所揭示者大致相同,其不同 處僅在該絕緣層2 0中形成有至少一開口 2 2,並使該支承板 1 1得以封閉住該絕緣層開口 2 2之一側,俾得提供後續於該 #緣層開口 22中安置有例如半導體晶片等電子元件。其中 該支承板1 1可為金屬或陶瓷材料,且被動元件1 3則可以黏 著、燒結或直接作成等方式形成於其凹部1 1 0中。 如第2 D至第2 F圖所示之可承置被動元件之半導體承載 板結構,同樣地與第一實施例所揭示者大致相同,其不同 處係在該支承板1 1之上表面1 1 a形成有複數個凹部1 1 0,以 將被動元件1 3選擇形成於該凹部1 1 0中後,再於該承置有 被動元件之支承板1 1表面上形成一絕緣層2 0,並可利用圖 案化製程以在該絕緣層中形成有圖案化線路結構2 1,並使 該線路結構2 1得以電性導通至該被動元件1 3之電極1 3 a。 • 如第2 D ’至第2 F ’圖所示之可承置被動元件之半導體承 載板結構,係與2 D至第2 F圖所揭示者大致相同,其不同處 僅在該絕緣層2 0中形成有至少一開口 2 2,並使該支承板1 1 得以封閉住該絕緣層開口 2 2之一側,俾得提供後續於該絕 緣層開口 2 2中安置有例如半導體晶片等電子元件。其中該7 1. .C 200522336 V. Description of the invention (13) The engraving technique forms a circuit patterned circuit layer. The circuit layer can also be used to form a detailed circuit in the patterned plating resist layer by electroplating. In addition, the circuit The structure is not limited to one floor. The support plate 11 may be a metal or ceramic material, and the passive element 13 may be formed on the surface by means of adhesion, sintering, or direct fabrication. The structure of the semiconductor carrier plate capable of receiving passive components as shown in Figs. 2A 'to 2C' is substantially the same as that disclosed in Figs. 2A to 2C, and the difference is only in the insulating layer 2 At least one opening 22 is formed in 0, and the support plate 11 can close one side of the opening 22 of the insulating layer, so as to provide subsequent installation of electronic components such as semiconductor wafers in the #edge layer opening 22 . The support plate 11 may be a metal or ceramic material, and the passive component 13 may be formed in the recess 1 10 by means of adhesion, sintering or direct fabrication. As shown in FIGS. 2D to 2F, the structure of the semiconductor carrier plate capable of receiving passive components is similar to that disclosed in the first embodiment, and the difference lies in the upper surface 1 of the support plate 1 1. 1 a is formed with a plurality of recesses 1 1 0 to selectively form passive components 13 in the recesses 1 10, and then an insulating layer 2 0 is formed on the surface of the support plate 11 1 on which the passive components are placed. A patterning process can be used to form a patterned circuit structure 21 in the insulating layer, and the circuit structure 21 can be electrically conducted to the electrode 1 3 a of the passive element 13. • The structure of the semiconductor carrier board that can accommodate passive components as shown in Figures 2D 'to 2F' is roughly the same as that disclosed in Figures 2D to 2F, and the difference is only in the insulating layer 2 At least one opening 22 is formed in 0, and the support plate 1 1 can close one side of the opening 22 of the insulating layer, so as to provide subsequent installation of electronic components such as semiconductor wafers in the opening 22 of the insulating layer. . Where the
17405全懋.ptd 第18頁 200522336 五、發明說明(14) 支承板1 1可為金屬或陶瓷材料,且被動元件1 3則可以黏著 、燒結或直接作成等方式形成於其凹部1 1 Q中。 此外’亦可在該支承板未接置有絕緣層之表面,黏著 一散熱片C未圖示),以提升後續半導體構裝之散熱效率 0 請參閱第3 A至第3 F圖,係為本發明之可承置被動元件 之半導體承載板結構第三實施例之剖面示意圖。 如第3 A至第3 C圖所示,本發明第三實施例之可承置被 動元件之半導體承載板結構與第一實施例所揭示者大致相 同,其不同處係在該支承板1 1中形成至少一開口 1丨丨,俾 供後續得以容置有電子元件,另於該支承板1丨表面上亦得 利用黏著、燒結或直接作成等方式接置有多數被動元件i 3 ’且‘ ό亥支承板1 1為金屬材質’該被動元件1 3上之電極 1 3 a則可選擇形成於該被動元件1 3表面之同一側或不同側 〇 如第3D至第3 F圖所示之可承置被動元件之半導體承載 板結構,同樣地與第一實施例所揭示者大致相同,其不同 處係在該支承板1 1中形成至少一開口 1 1 1,俾供後續得以 容置有電子元件,另於該支承板1 1上形成多數可供接置有 被動元件1 3之凹部110。其中該支承板11可為金屬或陶曼 材料,且被動元件1 3則可以黏著、燒結或直接作成等方式 形成於該凹部11 〇中。 請參閱第4A至第4F圖,係為本發明之可承置被動元件 之半導體承載板結構第四實施例之别面不意圖。17405 全懋 .ptd Page 18 200522336 V. Description of the invention (14) The support plate 1 1 can be a metal or ceramic material, and the passive component 13 can be formed in the recess 1 1 Q by means of adhesion, sintering or direct fabrication. . In addition, 'a heat sink C (not shown) may be adhered to the surface of the support plate without an insulating layer attached to improve the heat dissipation efficiency of the subsequent semiconductor structure. 0 Please refer to Figures 3A to 3F. A schematic cross-sectional view of a third embodiment of a semiconductor carrier board structure capable of supporting passive components according to the present invention. As shown in FIGS. 3A to 3C, the structure of the semiconductor carrier plate capable of receiving passive components in the third embodiment of the present invention is substantially the same as that disclosed in the first embodiment, and the difference lies in the support plate 1 1 At least one opening 1 丨 is formed in the opening, so that electronic components can be accommodated later, and on the surface of the support plate 1 丨 most passive components i 3 'and' must also be connected by means of adhesion, sintering or direct production. The support plate 1 1 is made of metal. The electrodes 1 3 a on the passive element 13 can be formed on the same side or different sides of the surface of the passive element 13 as shown in Figures 3D to 3F. The structure of the semiconductor carrier plate capable of receiving passive components is similar to that disclosed in the first embodiment. The difference is that at least one opening 1 1 1 is formed in the support plate 1 1 for subsequent storage. The electronic component has a plurality of recessed portions 110 formed on the supporting plate 11 for receiving the passive components 13. Wherein, the support plate 11 may be made of metal or Taumann material, and the passive element 13 may be formed in the recessed portion 11 by being adhered, sintered, or directly made. Please refer to FIG. 4A to FIG. 4F, which are not intended for other aspects of the fourth embodiment of the semiconductor carrier board structure capable of supporting passive components according to the present invention.
17405全懋.ptd 第19頁 200522336 五、發明說明(15) .如第4A至第4C圖所示,本發明第四實施例之可承置被 動元件之半導體承載板結構與第三實施例所揭示者大致相 同,其不同處係在該支承板1 1中形成至少一開口 1 1 1,並 於該支承板1 1上未設置有被動元件1 3之一側以一黏著層3 1 接置有一散熱片3 0,俾使該散熱片3 0得以封閉住該支承板 開口 1 1 1之一側,以供後續將至少一例如半導體晶片等電 子元件得以直接接置於該散熱片3 0上並收納於該支承板1 1 之開口 1 1 1内。其中,該支承板1 1可為金屬或陶瓷材料, 且被動元件1 3則可以黏著、燒結或直接作成等方式形成於 •表面,此外,若該支承板1 1為金屬時,係可與該散熱片 3 0—體成型,且該散熱片3 0之結構並非以本實施例中所示 者為限,其他例如形成有鰭片以增加散熱面積之散熱片亦 可適用於本發明中。 如第4 D至第4 F圖所示之可承置被動元件之半導體承載 板結構,同樣地與第三實施例所揭示者大致相同,其不同 處係在該支承板1 1中形成至少一開口 1 1 1,並於該支承板 1 1上形成多數可供接置有被動元件1 3之凹部1 1 0,且於該 支承板1 1上未設置有被動元件1 3之一側接置有一散熱片3 0 ,俾使該散熱片3 0得以封閉住該支承板開口 1 1 1之一側, 蠢供後續將至少一例如半導體晶片等電子元件,得以直接 接置於該散熱片3 0上並收納於該支承板1 1之開口内。其中 該支承板1 1可為金屬或陶瓷材料,且被動元件1 3則可以黏 著、燒結或直接作成等方式形成於該凹部11 0中。 由於本發明之可承置被動元件之半導體承載板結構117405 全懋 .ptd Page 19 200522336 V. Description of the invention (15). As shown in FIGS. 4A to 4C, the structure of the semiconductor carrier board capable of receiving passive components according to the fourth embodiment of the present invention and that of the third embodiment The revealers are substantially the same, but the difference is that at least one opening 1 1 1 is formed in the support plate 11, and one side of the support plate 11 is not provided with a passive element 1 3 and is connected with an adhesive layer 3 1. There is a heat sink 30, so that the heat sink 30 can close one side of the opening 1 1 1 of the support plate, so that at least one electronic component such as a semiconductor wafer can be directly connected to the heat sink 30. And stored in the opening 1 1 1 of the support plate 1 1. The support plate 11 can be made of metal or ceramic material, and the passive element 13 can be formed on the surface by means of adhesion, sintering, or directly made. In addition, if the support plate 11 is metal, it can be connected with the The heat sink 30 is formed in a single body, and the structure of the heat sink 30 is not limited to that shown in this embodiment. Other heat sinks such as fins formed to increase the heat dissipation area can also be used in the present invention. As shown in FIGS. 4D to 4F, the structure of the semiconductor carrier plate capable of receiving passive components is similar to that disclosed in the third embodiment, and the difference lies in that at least one of the supporting plates 11 is formed. An opening 1 1 1 is formed on the support plate 11 to form a plurality of recessed portions 1 1 0 to which a passive element 13 may be placed, and one side of the support plate 11 is not provided with a passive element 13. There is a heat sink 30, which enables the heat sink 30 to close one side of the opening 1 1 of the support plate, so that at least one electronic component such as a semiconductor wafer can be directly connected to the heat sink 30. The upper part is accommodated in the opening of the support plate 11. The support plate 11 may be a metal or ceramic material, and the passive element 13 may be formed in the recess 110 by means of adhesion, sintering, or direct fabrication. Because of the semiconductor carrier board structure capable of bearing passive components of the present invention 1
17405全懋.ptd 第20頁 200522336 五、發明說明(16) 不僅可整合該被動元件1 3,更可連接該散熱片3 0,以同時 整合該被動元件1 3、散熱片3 0、以及電子元件(未圖示), 提供該電子元件適當之遮蔽效果(Shielding),使該電子 元4牛免受夕卜界之電磁干擾(Electromagnet interference, EM I),更可在現今電子產品要求多功能及高電性之趨勢 下,提供有效數量之被動元件1 3與諸多半導體晶片等電子 元件於半導體構裝結構中。 以上所述者,僅為本發明之具體實施例而已,然本發 明並不受該實施例之限制應屬自明之事,亦即,本發明事 實上仍可做其他改變。再者,本發明亦可任意整合前述之 各式實施態,例如可在該支承板之上表面或其凹部内接置 有被動元件,並可於其上形成一具有圖案化線路結構之絕 緣層,且使該線路結構得以電性導接至該被動元件之電極 ,當然另可在該支承板之下表面再接置有一散熱片,且該 絕緣層或支承板中係可選擇性開設有至少一開口 ,藉以形 成一收納空間。 本發明之可承置被動元件之半導體承載板結構係可避 免習知於多層電路板層間安置膜狀被動元件所導致之製程 繁瑣,以及習知技術為因應不同設計需求之電阻值與電容 值等電性特性時,而必須重新設計、堆疊該多層電路板所 造成之製造成本大幅提升、物料管理困擾、及材料庫存成 本增加等問題,提供使用者針對所需電子裝置(例如半導 體封裝基板與印刷電路板)之電性功能,事先完成所需之 電性設計後再與一層或多層線路結構結合,並可承載諸如17405 全懋 .ptd Page 20 200522336 V. Description of the invention (16) Not only the passive component 1 3 can be integrated, but also the heat sink 30 can be connected to integrate the passive component 1 3, the heat sink 30, and the electronics. Component (not shown), to provide proper shielding effect of the electronic component, so that the electronic element 4N is protected from Electromagnet interference (EM I), and it can also be multifunctional in today's electronic products. Under the trend of high electrical properties, electronic components such as passive components 13 and many semiconductor wafers are provided in a semiconductor package structure. The above are only specific embodiments of the present invention, but the present invention is not limited by the embodiments and should be self-evident, that is, the present invention can be modified in other ways. Furthermore, the present invention can also arbitrarily integrate the aforementioned various implementation modes. For example, a passive element can be connected to the upper surface of the support plate or a recess thereof, and an insulating layer having a patterned circuit structure can be formed thereon. In addition, the circuit structure can be electrically connected to the electrodes of the passive component. Of course, a heat sink can be connected to the lower surface of the support plate, and the insulation layer or the support plate can optionally be provided with at least An opening forms a storage space. The semiconductor carrier board structure capable of supporting passive components of the present invention can avoid the tedious process caused by placing film-like passive components between layers of multilayer circuit boards, and the known technology is the resistance value and capacitance value according to different design requirements. Electrical characteristics, it is necessary to redesign and stack the multilayer circuit boards, which greatly increases manufacturing costs, troubles in material management, and increases in material inventory costs. It provides users with the required electronic devices (such as semiconductor packaging substrates and printing). Circuit board) electrical functions, complete the required electrical design in advance and then combine with one or more layers of circuit structure, and can carry such as
11 17405全懋.ptd 第21頁 200522336 五、發明說明(17) 晶之電子元件於其中以縮小半導體封裝基板之尺寸。再 者,本發明之可承置被動元件之半導體承載板結構不僅可 應用金屬支承板,亦可應用於陶瓷支承板。換言之,可利 用簡單製程以整合收納有多數如電阻、電容或電感元件等 被動元件於該支承板中,俾供結合基板及封裝製程而直接 形成可作電性導接之被動元件,以完成其所供承載半導體 之電性設計。 因此,本發明之可承置被動元件之半導體承載板結構 可解決習知技術中限定被動元件之設置位置及佈設數量等 g造成之種種問題,而可視線路佈局或其他需要來提供彈 性的設置位置及佈設數量。同時,本發明之可承置被動元 件之半導體承載板結構更可應用於球栅陣列式、覆晶式及 打線式之半導體封裝結構中,而不致影響該半導體封裝單 元及電子裝置之線路佈局性。 此外,雖於上述實施例中係以該支承板承載一個電子 元件為例作說明者,但須注意的是,該支承板亦可用以承 載複數個電子元件,該被動元件之設置位置與數量亦得視 需要作改變,而非以上述實施例中所顯示之兩個設於該支 承板兩端部之被動元件者為限。先前圖式中僅以部分之電 _元件及電容元件表示,實際上該電阻元件與電容元件之 數目以及相對位置,係依實際製程所需而加以設計而非為 上述具體實施例所限定者。換言之,上述實施例僅為例示 性說明本發明之原理及其功效,而非用於限制本發明。任 何熟習此技藝之人士均可在不違背本發明之精神及範疇下11 17405 全懋 .ptd Page 21 200522336 V. Description of the invention (17) Crystal electronic components are included therein to reduce the size of the semiconductor package substrate. Furthermore, the semiconductor carrier plate structure capable of receiving passive components of the present invention can be applied not only to a metal support plate but also to a ceramic support plate. In other words, a simple process can be used to integrate and house most passive components such as resistors, capacitors, or inductive components in the support board, which can be directly combined with the substrate and packaging process to form passive components that can be electrically conductive to complete their Electrical design of the supplied semiconductor. Therefore, the semiconductor carrier board structure capable of receiving passive components of the present invention can solve various problems caused by limiting the installation positions and the number of passive components in the conventional technology, and can provide flexible installation positions according to the circuit layout or other needs. And the number of deployments. At the same time, the semiconductor carrier board structure capable of supporting passive components of the present invention can be applied to ball grid array, flip-chip, and wire-type semiconductor packaging structures without affecting the layout of the semiconductor packaging unit and the electronic device. . In addition, although in the above embodiment, the support plate is used as an example for description, it should be noted that the support plate can also be used to carry a plurality of electronic components, and the position and number of passive components are also set. It may be changed as needed, not limited to the two passive components provided at the two ends of the support plate as shown in the above embodiment. In the previous drawings, only part of the electrical components and capacitor components are shown. In fact, the number and relative positions of the resistive and capacitive components are designed according to the actual process requirements and are not limited by the specific embodiments described above. In other words, the above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can do this without departing from the spirit and scope of the present invention.
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] 7405 全懋.ptd 第22頁 200522336] 7405 懋 .ptd p. 22 200522336
17‘105全®. ptd 第23頁 200522336 圖式簡單說明 [圖式簡單說明】 第1 A至1 G圖為根據本發明第一實施例之可承置被動元 件之半導體承載板結構之示意圖; 第2 A至2 F及第2 A ’至2 F ’圖為根據本發明第二實施例之 可承置被動元件之半導體承載板結構之不意圖, 第3 A至3 F圖為根據本發明第三實施例之可承置被動元 件之半導體承載板結構之示意圖;以及 第4 A至4 F圖為根據本發明第四實施例之可承置被動元 件之半導體承載板結構之示意圖。 1 半導體承載板結構 11 支承板 1 la 上表面 lib 下表面 110 凹部 111 開口 13 被動元件 13a 電極 15 黏著層 20 絕緣層 21 線路結構 22 開口 30 散熱片 31 黏著層17'105 全 ®. Ptd Page 23 200522336 Brief description of drawings [Simplified description of drawings] Figures 1 A to 1 G are schematic diagrams of a structure of a semiconductor carrier board capable of receiving passive components according to the first embodiment of the present invention; Figures 2A to 2F and 2A 'to 2F' are views of the structure of a semiconductor carrier board capable of supporting passive components according to the second embodiment of the present invention, and Figures 3A to 3F are according to the present invention The third embodiment is a schematic diagram of a structure of a semiconductor carrier board capable of supporting passive components; and FIGS. 4A to 4F are schematic diagrams of the structure of a semiconductor carrier board capable of supporting passive components according to a fourth embodiment of the present invention. 1 Semiconductor carrier board structure 11 Support plate 1 la upper surface lib lower surface 110 recess 111 opening 13 passive element 13a electrode 15 adhesive layer 20 insulating layer 21 wiring structure 22 opening 30 heat sink 31 adhesive layer
]7405全懋.ptd 第24頁] 7405 全懋 .ptd Page 24
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