TW200425727A - Solid-state imaging apparatus - Google Patents

Solid-state imaging apparatus Download PDF

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Publication number
TW200425727A
TW200425727A TW092132431A TW92132431A TW200425727A TW 200425727 A TW200425727 A TW 200425727A TW 092132431 A TW092132431 A TW 092132431A TW 92132431 A TW92132431 A TW 92132431A TW 200425727 A TW200425727 A TW 200425727A
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Taiwan
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pixel
signal
pixels
solid
state imaging
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TW092132431A
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Chinese (zh)
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TWI237503B (en
Inventor
Takashi Abe
Nobuo Nakamura
Yomoyuki Umeda
Keiji Mabuchi
Hiroaki Fujita
Funatsu Eiichi
Sato Hiroki
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Sony Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/10—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
    • H04N23/12—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths with one sensor only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
    • H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
    • H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • H04N25/11—Arrangement of colour filter arrays [CFA]; Filter mosaics
    • H04N25/13—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
    • H04N25/134—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements based on three different wavelength filter elements

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Color Television Image Signal Generators (AREA)

Abstract

The present invention is a solid-state imaging apparatus wherein the size of pixels has been reduced by simplifying the pixel structure, and wherein in a case of employing a plural-system-output structure, the variations between pixels can be suppressed. A unit cell (30) includes two pixels (31,32), which are constituted by: two upper and lower photoelectric conversion elements (33,34), transfer transistors (35,36), respectively, a single reset transistor (37) and a single amplifying transistor (38). An overall signal line (39) is connected to the drains of the reset and amplifying transistors (37,38). This overall signal line (39) is controlled together with the transfer signal wires (42,43) and a reset signal wire (41) to read signals, thereby realizing the simplification of pixel wires, the reduction of the pixel size and the like.

Description

200425727 玖、發明說明： 【發明所屬之技術領域】 本發明係關於在每個二次元排列的複數個單位像素設有 光電轉換元件及複數個像素電晶體之CMOS影像感測器等 之固體攝影裝置。 【先前技術】 圖8係顯示以往所採用之包含CM〇S影像感測器的像素構 成之一例之電路圖。 在圖示例中，各像素之構成係包括一個光電轉換元件1， 及複數個電晶體2、3、4、6。 光電轉換元件1係受光而累積信號電荷者，使用光電二 體等。 兒一極 又，電晶體2係用於信號電荷放大之電晶體（以下表示為 放大電晶體2)，·電晶體3係用於將光電轉換元件}所累積 “虎電何’傳达到放大電晶體2的閘極部之傳送電晶體(以 下表示為傳送電晶體3)。 =卜，電晶體4剌於重置放大電晶體2的閘極電位之重 置電晶體（以下表示為重置電晶體4)。 再者，信號線5係電源電位供給線 供仏绂5、·舌班+ Γ衣不為電源電位 °、’重置電晶體4和放大電晶體2的汲 位供給線5連接。 L、电廣電 又，電晶體6係用於選擇輸出像素的選擇 示為選擇雷曰雜/：、/ 下表 出線(以下矣 係用於輸出像素信號的像素輪 出線(以下表示為像素輸出線7)。 輸[Technical Field] The present invention relates to a solid-state imaging device in which a plurality of unit pixels arranged in each of the second elements are provided with a photoelectric conversion element, a CMOS image sensor of a plurality of pixel transistors, and the like . [Prior Art] Fig. 8 is a circuit diagram showing an example of a pixel configuration including a CM〇S image sensor which has been conventionally used. In the illustrated example, each pixel is composed of a photoelectric conversion element 1 and a plurality of transistors 2, 3, 4, and 6. The photoelectric conversion element 1 is a person who receives light and accumulates signal charges, and uses a photodiode or the like. One pole, the transistor 2 is used for signal charge amplification of the transistor (hereinafter referred to as the amplifying transistor 2), and the transistor 3 is used to convey the "Tiger Electric" accumulated by the photoelectric conversion element to the amplification The transfer transistor of the gate portion of the crystal 2 (hereinafter referred to as the transfer transistor 3). The transistor 4 is placed on the reset transistor for resetting the gate potential of the amplifying transistor 2 (hereinafter referred to as resetting the battery). Crystal 4). Further, the signal line 5 is connected to the power supply potential supply line 5, the tongue shift + the clothing is not the power supply potential °, and the reset transistor 4 and the amplification transistor 2 are connected to the clamp supply line 5 L, electric radio and television, transistor 6 is used to select the output pixel selection is selected as the choice of thunder / /, / the following table outlet (the following is used to output the pixel signal of the pixel wheel outlet (hereinafter expressed as Pixel output line 7).

O:\87\87775.DOC 200425727 素外之黾晶體8係用於向像f γ ψ娃& 的電晶體(以下夺-Α 一 '像素輸出線供給恆定電流 電流供給至選定像+ #係將恆定 共汲極組態作動而 ^曰體2’使放大電晶體2作為 ，、乍動，而於像素輸出線7產生與 閑極電位具有特定怪定電位差的電位，W的 信二::9:'用:傳控制傳送電晶雜3的_位之傳送 制重"晶趙4的 ^位之重置^唬配線（以下表示 ^號Si線1G)。信號線1 i係、用於控制選擇電晶體6的問極 電位之選擇信號線(以下表示為選擇信號線 係將特定電位供給至閉極之怪定電位供給線(以下：2 Μ電位供給線12)，使值定電流供給電晶體8以進行供給 恆定電流之飽和區域動作。 又，端子13係將傳送脈衝供給至各列之傳送信號配線9 ㈣衝端子’且連接於列選擇用娜元件14之—側的輸入 端。又’在列選擇用AND元件14之另一側的輸入端係連接 有來自垂直選擇手段15的輸出，❿列選擇用and元件^之 輸出端係連接於傳送信號配線9。 知子16係用於將重置脈衝供給至各列之重置信號配線工〇 的脈衝知子，其連接於列選擇用AND元件丨7之一側的輸入 端在列選擇用AND元件1 7之另一側輸入端係連接有來自 垂直選擇手段15的輸出，而列選擇用AND元件17之輸出端 係連接於重置信號配線丨〇。 端子18係用於將選擇脈衝供給至各列之選擇信號線丨丨的O:\87\87775.DOC 200425727 The external crystal 8 is used to supply a constant current to a selected image + # system to a transistor like f γ & & & ( The constant common drain configuration is activated, and the body 2' is used to make the amplifying transistor 2 as a sway, and the pixel output line 7 generates a potential having a specific strange potential difference from the idle potential, W 2::9 : 'Use: Transmission control transmission 电 的 之 transmission transmission weight " Crystal Zhao 4 ^ position reset ^ 唬 wiring (hereinafter indicated ^ No. Si line 1G). Signal line 1 i system, for The selection signal line for controlling the potential of the transistor 6 is selected (hereinafter, the selection signal line supplies a specific potential to the strange potential supply line of the closed electrode (hereinafter: 2 Μ potential supply line 12), so that the constant current is supplied. The transistor 8 operates in a saturation region where a constant current is supplied. Further, the terminal 13 supplies a transfer pulse to the transfer signal wiring 9 (four) of each row, and is connected to the input terminal on the side of the column selection element 14 . In addition, the input terminal on the other side of the column selection AND element 14 is connected from the vertical selection. The output of the means 15 is connected to the transmission signal wiring 9 at the output end of the array selection and component ^. The koji 16 is a pulse chirp for supplying a reset pulse to the reset signal wiring process of each column, which is connected to The input terminal on one side of the column selection AND element 丨7 is connected to the output from the vertical selection means 15 at the other input terminal of the column selection AND element 17, and the output terminal of the column selection AND element 17 is connected. The reset signal wiring port is used. The terminal 18 is for supplying a selection pulse to the selection signal line of each column.

O:\87\87775.DOC 200425727 脈衝如子其連接於列選擇用and元件i 9之一側的輸入 端在列k擇用AND兀件19之另一側的輸入端係連接有來 自垂直選擇手段15的輸出，而列選擇用AND元件19之輸出 端係連接於選擇信號線丨i。 藉由如此之構成，僅針對藉由垂直選擇手段15而選定的 各列之各#號配線供給各控制脈衝。 4之各像素之言買出動作，力μ上 _ 力上如圖9所示之驅動信號，按如 下進行之。 再者’圖9中的選擇信號表示賦予圖8之選擇信號線^的 信號；重置信號表示賦予重置信號線10的信號；傳送信號 表示賦予傳送信號線9的信號。 瓦先，使進行讀出之像素列的選擇電晶體6和重置電晶體 4處於導通狀態，重置放大電曰 人八电日日體2的閘極部。使重置電晶 體4處於非導通後，將傻夸 1冢言之重置位準的相對電壓讀出至後 段之C D S (相關倍頻取樣）電路2 〇。 其次，使傳送電晶體3轉為導通狀態，將光電轉換元件夏 所累積的電荷傳送至放大電晶體2的閘極部。傳送完成後， 使傳送電晶體3處於非導通狀態後，將累積電荷量的相對作 號位準電壓讀出至後段之CDS電路2〇。 在CDS電路2G中’取先前讀出的重置位準與信號位準之 差’消除因每—像素之讀出電晶體的臨限值（Vth)差異所造 成之固定性圖案雜訊。 CDS電路2G所累積的信號—旦被行選擇手段^選定，即 經由水平信號線22讀出至AGC等後段電路予以處理。O:\87\87775.DOC 200425727 The pulse is connected to the input of one side of the column selection and component i 9 at the input end of the other side of the column selection AND member 19 with vertical selection The output of the means 15 and the output of the column selection AND element 19 are connected to the selection signal line 丨i. With such a configuration, each control pulse is supplied only to each #-number wiring of each column selected by the vertical selection means 15. The word of each pixel of 4 buys the action, and the force is applied to the drive signal as shown in Fig. 9, as follows. Further, the selection signal in Fig. 9 indicates a signal given to the selection signal line ^ of Fig. 8; the reset signal indicates a signal given to the reset signal line 10; and the transmission signal indicates a signal applied to the transmission signal line 9. In the first step, the selection transistor 6 and the reset transistor 4 of the pixel row to be read are placed in an on state, and the gate portion of the amplifier 8 is reset. After the reset transistor 4 is rendered non-conducting, the relative voltage of the reset level is read out to the C D S (correlated frequency doubling sampling) circuit 2 of the latter stage. Next, the transfer transistor 3 is turned into an on state, and the charge accumulated in the summer of the photoelectric conversion element is transferred to the gate portion of the amplifying transistor 2. After the transfer is completed, after the transfer transistor 3 is in the non-conduction state, the relative level of the accumulated charge amount is read out to the CDS circuit 2 of the subsequent stage. In the CDS circuit 2G, 'the difference between the previously read reset level and the signal level' is removed to eliminate the fixed pattern noise caused by the difference (Vth) of the read transistor of each pixel. The signal accumulated by the CDS circuit 2G is selected by the row selection means ^, i.e., read out to the AGC or the like by the horizontal signal line 22 for processing.

O:\87\87775 DOC 200425727 如上所述，在CM0S影像感測器中，一像素中除了光電轉 矣凡件外’尚有必要設置用作讀出光電轉換元件所累積之 電荷的各種電晶體和控制信號配線。 ’、、 因此，相車交於具有單純的像素構造之CCD影像感測器， 像素縮小化較為困難。 對此，以往的方法是藉由改變像素電路之驅動法，例如 圖11所不，有人提出省去選擇電晶體而使像素構成單純化 的提案（參照特開2002_07773丨號公報）。 、 或者，如圖12所示，有人提出在從複數個光電轉換元件 之頃出中共用一個放大電晶體者（參照 wcm/07630號公報）。 …開 即，圖12所示之像素係介以傳送電晶體3使鄰接之像素的 ^個光電轉換元件丨之輸出連接於一個放大電晶體2的閘極 部者，亚藉由傳送電晶體3以及重置電晶體4的依序控制而 從放大電晶體2輸出兩個像素信號。 再者，放大電晶體2的閘極連接有電容23 ,藉由急沖電容 用配線24提供急沖脈衝，而形成可控制閘極部之電位的構 造。 根據上述之圖1 2所示的先前技術，可藉由共用放大電晶 體而實現一像素中的元件數之減少以及像素尺寸之縮小， 不過，在圖8或圖Π所示之單位胞（單位胞内含一個像素者） 中’其像素陣列中的所有像素乃同一形狀，而相對的，排 列成圖12所示之單位胞（共用放大電晶體的像素組）而構成 的像素陣列則係以兩種像素所構成。O:\87\87775 DOC 200425727 As described above, in the CMOS image sensor, in addition to the photoelectric conversion of a pixel, it is necessary to set various transistors for reading the charge accumulated by the photoelectric conversion element. And control signal wiring. Therefore, the car is handed over to a CCD image sensor having a simple pixel structure, and pixel reduction is difficult. On the other hand, the conventional method is to change the driving method of the pixel circuit, for example, as shown in Fig. 11. It has been proposed to omit the selection of the transistor and to simplify the pixel formation (refer to Japanese Laid-Open Patent Publication No. 2002_07773). Alternatively, as shown in Fig. 12, it has been proposed to share one of the magnifying transistors from the plurality of photoelectric conversion elements (see wcm/07630). ...that is, the pixel shown in FIG. 12 is connected to the gate of one of the amplifying transistors 2 via the transmitting transistor 3, and the output of the photoelectric conversion element 邻接 of the adjacent pixel is transferred by the transistor 3 And the sequential control of the reset transistor 4 outputs two pixel signals from the amplifying transistor 2. Further, a capacitor 23 is connected to the gate of the amplifying transistor 2, and a rush pulse is supplied by the snubber capacitor wiring 24 to form a structure capable of controlling the potential of the gate portion. According to the prior art shown in FIG. 12 above, the number of components in one pixel can be reduced and the pixel size can be reduced by sharing the amplifying transistor. However, the unit cell (unit shown in FIG. 8 or FIG. In a cell containing one pixel, all of the pixels in the pixel array have the same shape, and the pixel arrays formed by the unit cells (the pixel group sharing the amplified transistor) shown in FIG. 12 are It consists of two types of pixels.

O:\87\87775.DOC 200425727 所以，由於兩種像素間的元 .^ ^ j幻兀件形狀不冋，故兩者之間會 屋生感度、飽和度等特性上之差異。 /列如、，以RGB拜耳（Ba㈣模式進行彩色編碼之時，即使 2樣以G進行色彩編碼的像素，也會由於列的因素 像素特性產生差異，因而若杲 的P”… 幅畫面來看時會有橫線 的問題產生。 此問題並非僅為第丨2圖所示 平位肊的問碭，與電晶體 數或構、無關，係由於像素間之電晶體共有化所造成。 /12中：由於僅在下側之像素内形成電容23,故而會產 生例如電谷23所造成之入射光的. . 、 友*妁遮光，或者因電容23之形 成讓受光面積變小而降低入射 里使侍下側像素之感度 較上側像素為低。 兩種像素中’碩出光電轉換後的電荷之傳送電晶體 的配置不同，讀出電荷之方向也不同。由於決定電荷讀出 方向之傳送電晶體的配置不同， 夏个U使侍兩像素間產生感度差 〃。究其原因，可看作例如因傳送電晶體之電位對受光部 之電位所造成之影響出現在不同位置，所以來自同一方向 之入射光的光電轉換效率或電荷累積量會有所差異。 再者’根據先前之讀出方或办 貝®万式例如以一個輸出系統（水平 信號線、縱、ADC等）處理自各像素讀出至咖電路之信 號輸出並將其轉換為數位信妒， 呢然後，再用内部電路以及 外部電路處理並讀出該數位信號。 然而’近年來為謀求-種能以更高速度進行取樣的固體 攝影元件，而如圖13圖所元，女2知 圓所不有人想到將自各像素讀出至O:\87\87775.DOC 200425727 Therefore, since the shape of the element between the two pixels is not good, there is a difference in characteristics such as sensitivity and saturation between the two. / column as, when color coding is performed in RGB Bayer mode, even if two pixels are color-coded by G, the pixel characteristics of the column will be different, so if the P" is viewed from the picture There is a problem with the horizontal line. This problem is not only the problem of the flat 肊 shown in Fig. 2, but it is caused by the number of transistors or the structure, which is caused by the commonality of the transistors between the pixels. Medium: Since the capacitor 23 is formed only in the pixel on the lower side, for example, the incident light caused by the electric valley 23 is generated, or the light is blocked by the formation of the capacitor 23, and the incident area is made smaller by the formation of the capacitor 23. The sensitivity of the lower side pixel is lower than that of the upper side pixel. In the two types of pixels, the arrangement of the charge transfer transistor after the photoelectric conversion is different, and the direction of the read charge is also different. The transfer transistor that determines the charge readout direction is determined. The configuration is different, and the summer U causes a difference in sensitivity between the two pixels. The reason can be seen as, for example, because the potential of the transmitting transistor affects the potential of the light receiving portion at different positions, so The photoelectric conversion efficiency or charge accumulation amount of the incident light in the same direction may be different. Further, 'according to the previous readout method or the Dolby® type, for example, an output system (horizontal signal line, vertical, ADC, etc.) is processed from each The pixel reads out the signal output of the coffee circuit and converts it into a digital signal, and then processes and reads the digital signal by using an internal circuit and an external circuit. However, in recent years, it has been able to perform at a higher speed. Sampled solid-state photographic elements, and as shown in Figure 13, the female 2 knows the circle, no one thought of reading from each pixel to

0 \87\87775.DOC -10- 200425727 CDS電路的信號輸出分為兩個輸出系統來進行處理。 即，圖1 3係顯示CM〇s影像感測器的整體構成例，其構成 包括.含有上述之像素陣列的感測器部】丨】、垂直驅動電路 1 士 12、快門驅動電路113、CDS電路114、水平驅動電路出、 時序脈波產生器116、AGC電路117A、117B，及ADC電路 1 8B等，並藉由雙系統之水平信號線119A、11、 AGf電路117A、U7B及ADC電路u8A、u8B輸出信號。 1由士此將輸出系統分成兩部A，使加諸於一條水平信 號線上之負荷減半’相對於以往之單輸出系統者而言，； 以雙倍速度進行讀出。 广，：使兩個輸出系統内之各元件的特性完全一樣，在 f私上I屬不可能°即’輸出系統中既然包含有AGC、ADC 寺矢員比電路，其增益、雜訊特性等便會有所不同，所以即 使輸入完全相同的信號，處理後的信號也會產生㈣ 異。 :別是在此會有問題的固體攝影元件中，來自像素之信 =屮係處理位準為數(，〜〇 .數(，之微小類比信號， 口而輸出糸統間的特性差異將成為非常重大之問題。 例如’圖1 4係表示以兩個於山 兩個輸出乐統針對以拜耳模式實施 衫色遽光的攝影元件之讀出 圖。 貝出l唬進仃處理後的狀態之說明 根據如圖所示之拜耳排列，其係將 置之RG列和Gb像素盥b傻去^ 诼京· 乂互配 “回 /常^像素父互配置之GB列鄰接配置。 圖14所不的RG列（第n列）矣 木之項出，係經由輸出系統Α0 \87\87775.DOC -10- 200425727 The signal output of the CDS circuit is divided into two output systems for processing. That is, FIG. 13 shows an overall configuration example of a CM〇s image sensor, which includes a sensor portion including the above-described pixel array, a vertical drive circuit 12, a shutter drive circuit 113, and a CDS. Circuit 114, horizontal drive circuit output, timing pulse generator 116, AGC circuit 117A, 117B, and ADC circuit 18B, etc., and by horizontal signal lines 119A, 11, AGf circuits 117A, U7B and ADC circuit u8A , u8B output signal. 1 The division of the output system into two parts A reduces the load applied to a horizontal signal line by half compared to the previous single output system; reading at double speed. Wide: Make the characteristics of each component in the two output systems exactly the same. It is impossible to use I in the private sector. That is, the output system contains AGC, ADC, and other components, and its gain, noise characteristics, etc. It will be different, so even if you input the exact same signal, the processed signal will produce (four) different. : In the solid-state imaging component that has problems here, the signal from the pixel = the processing level of the system is a number (, ~ 〇. number (, the tiny analog signal, the difference between the output characteristics of the output and the system will become very A major problem. For example, 'Fig. 1 4 shows a reading diagram of a photographic element that performs a shirt color in a Bayer mode with two output systems in the mountains. Explanation of the state after the processing According to the Bayer arrangement as shown in the figure, it will be placed in the RG column and the Gb pixel 盥b stupid ^ 诼 · 乂 乂 “ 回 回 回 回 常 常 常 常 常 常 常 常 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素The RG column (nth column) is the item of the coffin, which is via the output system.

O:\87\87775.DOC 200425727 而讀出R像素 出0 來自Gr像素的信號則是經由輪出 系統B讀 之下一 GB列（第n+1列）之 B像素的信號，係分別經O:\87\87775.DOC 200425727 and the R pixel is read out. The signal from the Gr pixel is read by the wheel system B. The signal of the B pixel of the lower GB column (the n+1th column) is respectively

讀出為：來自 由輸出系統A 此外，自圖14所示 Gb像素的信號和來自 和輸出系統B讀出。 了之來自R像素和Gb像素的信號係經由輸出系統a讀 ，而來自B像素和Gr像素之信號係經由輸出系統b讀出。 而^種來自R、G、B各個像素之信號，因為會在後段依 各色施加调整色彩平衡之信號處理，故即使加上各個輸出 系統造成的微小差異，也不會有太大的問題。 但疋，右當作同一 G像素予以處理之Gr、仍由於是以不 同的輸出系統進行處理因而具有微小之差異時，會在列方 向上產生週期性的信號差，所以以一幅晝面來看時可能會 看到橫線。 曰 因此，本發明之目的係提供一種固體攝影裝置，其可藉 由像素構成之簡化以謀求像素之縮小，還可抑制複數個系 統之輸出構成情形下的像素間之差異。 【發明内容】 本發明為達前述之目的，其特徵在於：具有將以特定數 量之像素為一組而構成之複數個單位胞配置成二次元陣列 狀的攝影區域部，及用於選擇前述各像素之信號配線；前 述之單位胞具有：對應各像素相的複數個光電轉換元件； 為前述各像素所共有，且將自各光電轉換元件讀出之信號 1放大並輸出的放大手段；及選擇性讀出來自各光電轉換 O:\87\87775.DOC -12- 200425727 凡件的H，並供給前述放大手段的傳送手段；動前述 放大手段之信號配線包括配線成全像素共用之全面信號 線，精由驅動前述全面信號線而讀出來自各像素的信號。 本發明的再一特徵在於：在前述攝影區域部的各像素行 ^象素或未滿一像素朝行方向錯開配置有前述單位 胞。 本發明的又一特徵在於：具有將以特定數量的像素為— ’”且而構成之稷數個單位胞配置成二次元陣列狀的攝影區域 部’以及用於選擇前述各像素之信號配線；前述單位胞具 有：對應各像素之複數個光電轉換元件；為前述各像素所 共有’且將自各光電轉換元件讀出之信號量放大並輸出的 放大手段；以及選擇性讀出來自各光電轉換元件的传號並 供給前述放大手段的傳送手段；前述單位胞的各光電轉換 元件為斜向鄰接配置。 、 本务明之固體攝影裝置藉由像素間電晶體之共有化和入 面信號線的使用’可減少每—像素之電晶體數及信號料 數，進而能夠使像素尺寸縮小化。 此外’即使對於像素間電晶體共有化之關注點— 同形狀的像素間之特性差或兩個輸出系統間之增益差而 言’亦可藉由單位胞之配置或斜向兩像素間之：： 法，抑制來自像素間、特別是來自以G實施濾光 號的特性差。 15 【實施方式】 以下，就本發明之固體攝影裝置的實施形態例進行說明。Read out as: From output system A In addition, the signal from the Gb pixel shown in Figure 14 is read from the output and output system B. The signals from the R pixels and the Gb pixels are read via the output system a, and the signals from the B pixels and the Gr pixels are read out via the output system b. The signals from the respective pixels of R, G, and B are used because the signal processing for adjusting the color balance is applied in the subsequent stages. Therefore, even if a small difference caused by each output system is added, there is no problem. However, if the right G is treated as the same G pixel, and the processing is performed by different output systems, and there is a slight difference, a periodic signal difference will occur in the column direction, so You may see a horizontal line when you look at it. Accordingly, it is an object of the present invention to provide a solid-state imaging device which can reduce the number of pixels by simplifying the pixel configuration and suppress the difference between pixels in the case of the output configuration of a plurality of systems. SUMMARY OF THE INVENTION The present invention has attained the above object, and has an imaging region portion in which a plurality of unit cells configured by a specific number of pixels are arranged in a quadratic array shape, and is used for selecting each of the foregoing a signal line of a pixel; the unit cell has a plurality of photoelectric conversion elements corresponding to each pixel phase; an amplification means common to the pixels and amplifying and outputting the signal 1 read from each photoelectric conversion element; and selectivity Reading out the transfer means from the respective photoelectric conversion O:\87\87775.DOC -12- 200425727 and supplying the above-mentioned amplification means; the signal wiring of the amplifying means includes a comprehensive signal line which is wired to be shared by all pixels, The signals from the respective pixels are read by driving the aforementioned full signal lines. Still another feature of the present invention is that the unit cells are arranged in a row in the pixel direction or in a pixel in the image capturing area. Still another feature of the present invention is that a photographing region portion ′ in which a plurality of unit cells are configured with a specific number of pixels as “′′ and arranged in a quadratic array shape, and signal wirings for selecting the respective pixels are provided; The unit cell has a plurality of photoelectric conversion elements corresponding to the respective pixels, an amplification means for amplifying and outputting a signal amount read from each of the photoelectric conversion elements, and selectively reading out the photoelectric conversion elements from the respective photoelectric conversion elements. The transmission means is supplied to the amplifying means; the photoelectric conversion elements of the unit cell are arranged adjacent to each other in an oblique direction. The solid-state imaging device of the present invention is shared by the inter-pixel transistors and the use of the in-plane signal line. The number of transistors per pixel and the number of signals can be reduced, which in turn can reduce the pixel size. In addition, 'even the focus on the inter-pixel transistor sharing—the difference between the pixels of the same shape or between two output systems In terms of gain difference, 'can also be used by the unit cell or obliquely between two pixels:: method, suppressing between pixels, Is a characteristic number from the filter to the difference in G embodiment. [Embodiment 15] Hereinafter, the embodiment will be described showing an embodiment of the solid-state imaging device according to the present invention.

O:\87\87775 DOC -13 - 200425727 _本實鈀之形悲例的攝影裝置’其構成如CM〇s影像感測器 寺，於各像素設置光電轉換元件和複數個電晶體，藉由複 數個像素之二次元排列而構成像素陣列，並配置有用於驅 動各像素的複數個錢配線，其巾像相共有電晶體，並 進一步採用全面信號線構成單位胞（即共有電晶體之像素 組），藉此可減少相當於一個像素的元件數和控制配線數， 而求得像素縮小化者。 又，藉由改變此種像素間電晶體共有型之單位胞的排列 方式’在以同色遽光之像素上採用相同形狀的像素，從而 使以同色濾光的像素之特性互相一致。 進言之，藉由斜向鄰接之像素進行像素間電晶體共有 化:從而即使在將輸出系統一分為二之時，也能以同一輪 出系統從以同色渡光之像素進行讀出。 以下，佐以圖式對本發明之具體實施例加以說明。 (第一實施例） 圖1為表示本發明第一實施例之上下兩個像素間共有電 晶體時的像素構造之電路圖。 在本例中，單位胞30為用實線框起之部分，該單位胞3〇 包括兩個像素31(用間隔小的點線框起之部分）、32(用間隔 大的虛線框起部分）。 在此單位胞30中的兩個像素包含：上下兩個 件…，各一個傳送電晶體35、36, 一個重置電= 和一個放大電晶體3 8。 信號線39為全面信號線（下稱··全面信號線外），其連接於O:\87\87775 DOC -13 - 200425727 _The photographic device of the shape of the palladium is composed of a CM〇s image sensor temple, and photoelectric conversion elements and a plurality of transistors are arranged in each pixel. A plurality of pixels are arranged in a second element to form a pixel array, and a plurality of money wirings for driving each pixel are arranged, the towel image phase shares a transistor, and further a full signal line is used to form a unit cell (ie, a pixel group of a common transistor) Therefore, the number of components corresponding to one pixel and the number of control wirings can be reduced, and the pixel reduction can be obtained. Further, by changing the arrangement pattern of the unit cells of the inter-pixel transistor sharing type, pixels of the same shape are used for pixels of the same color, and the characteristics of the pixels filtered by the same color are matched with each other. In other words, inter-pixel transistor sharing is performed by obliquely adjacent pixels: even when the output system is divided into two, reading can be performed from pixels that are in the same color by the same polling system. Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. (First Embodiment) Fig. 1 is a circuit diagram showing a pixel configuration when a transistor is shared between two lower pixels in the first embodiment of the present invention. In this example, the unit cell 30 is a portion which is framed by a solid line, and the unit cell 3 includes two pixels 31 (parts with a small dot frame) and 32 (with a large dotted line framed portion) ). The two pixels in this unit cell 30 include: upper and lower two parts, one for each of the transfer transistors 35, 36, one for resetting the electric = and one for the magnifying transistor 38. The signal line 39 is a full signal line (hereinafter referred to as a full signal line), which is connected to

O:\87\87775.DOC -14- 200425727 各重置電晶體37和放大電晶體％之汲極。 <吕號線40為像素輸出線（下摇 像素輸出線40);信號線4 ! 係用於控制重置電晶體37 ^ W牷包位的重置信號配線（下 稱·重置信號配線4 1)。 信號線42係心控制傳送電晶體35之閘極電位的傳送作 號配線（下稱：傳送信號配線42);信號線们係用於控制傳送 電晶體36的傳送信號配線（下稱：傳送定信號配線43)。 圖2為表示設有圖！所示之像素構造的固體攝影裝置之二 次元像素的整體構成之電路圖。 固體攝影裝置之受光面女开後 〇 尤甶（一-人疋像素區塊）之構成係以此 二像素為單位胞並將其作二次元排列。 但定電流供給電晶體8係用於對像素輸出線供給恆定電 流的電晶體，其供給恆定電流至選定的像素之放大電晶體 38而使其作為共㈣組態作動，於像素輸出㈣產生相$ 於放大電晶體38之閘極電位具有特定電壓差之電位。 端子44係對各㈣送㈣線42、43供給料脈衝的脈衝 端子’其與列選擇用AND元件45、46之—側的輸入端連接， :列選擇用娜元件45、46之另一側輸入端係與來自垂直 選擇手段15的輸出連接。又，列選擇用AND元件、仏之 輸出端係與傳送信號配線42、43連接。 端子47係用以將重置脈衝供給至各列重置信號配線41的 脈衝端子，與列選擇用AND元件48之一側的輪入端連接， 而列選擇用娜元件48之輸出端係與重置信號配線㈣ 接。又，列選擇用AND元件48之另一側輸入端連接有⑽電 O:\87\87775.DOC -15- 路49的輸出。 OR電路49的於人八 之垂直選擇作。/刀別連接有上T兩個像素所在的兩列 即，1 :線15Α、15Β’並輸出重合兩列信號之波形。 入各信―擇手段15所選定的列輸 件33、34 電日日37之閘極會在來自光電轉換元 的像素5貝出日守，賦加以來自脈衝端子47之信 就0此外，除了 l、j_、 ^ 之信號配線外，又驅動全面信號線39， 稭此進行讀出動作。 圖3A〜3D為表示在本例 读 个】又像素構造中，從像素進行信號 貝 作日守之各驅動信號的情形之時序圖。 。圖3A〜30所示之信號係分別賦加i進行讀出之列的信 入王面遥擇仏號、重置信號及傳送信號係分別賦加至圖2 之全面信號線39、重置信號配線41以及傳送信號配線心、 4 3的信號。 首先’以圖3為例就讀出動作敘述之。 ▲在初始狀態下，重置信號、傳送信號都設定為l〇w(非有 效）王面選擇信號設定為High(有效）。 其次，重置信號只要轉為Hlgh,則各像素之放大電晶體 W的閑極部電位就重置到全面選擇信號之出§1^在此，使 重置信號轉為Low之後，會使重置位準的相對電位讀出至 像素輪出線，並於CDS電路累積其電壓值。 然後，使傳送信號轉為Hlgh，將各光電轉換元件内累積 的電荷傳送至放大電晶體3 8的閘極部，並在傳送結束後， 使傳送信號轉為Low ,將各光電轉換元件所累積之電荷數 O:\87\87775.DOC -16- 200425727 的相對電位經由像素輸出線向CDS電路讀出，並於CDS電路 取得重置位準和信號位準之差。 取後一連串讀出動作結束後，使全面選擇信號轉變為 使重置彳5唬轉變為HiSh，並將放大電晶體38的輸入 部重置。 卜如果使用空乏型電晶體作為重置電晶體，則只要 使全面選擇信號為Low，就可以進行放大電晶體輸入部的 重置，故可用圖3B所示之波形進行驅動。 再者，圖3C至圖3D係將圖3八至33變更而得者，其係只 在讀出動作時將全面選擇信號設定為Hlgh者。 藉由X上之構成’可使像素構造較之以往更為簡化。 即’在圖11所示之先前例的構成中，每—像素的電晶體 為二個，相對的’在此像素構成中則為兩個，信號配線 數也從2條減少紅5條(即全面信號線兼用作遮光膜；即全 面信號線如一般所熟知的固體攝影裝置之遮光膜般，每一 像素含有對應於受光面的開口）。 二Si術中’由於電容乃偏離特定像素而形成，所以 p谷之像素和未形成電容之像素間的感度和飽和信 ，但根據本實施例之構成，因其係使用入面 信號線以控制放大電晶體輸入部之重置位準而讀出至：音 外，故無形成電容之必要，使此問題得以解決。 ” 又’較之於圖12所示的先前例之構成，其既 以外的電容’每—像素之信號線也 … “ 可望實現像素之縮小化。 成^.5條，更O:\87\87775.DOC -14- 200425727 Each reset transistor 37 and the anode of the amplified transistor %. <Lv line 40 is a pixel output line (downward pixel output line 40); signal line 4! is used to control the reset signal wiring of the reset transistor 37 ^ W牷 packet (hereinafter referred to as reset signal wiring) 4 1). The signal line 42 is used to control the transmission wiring of the gate potential of the transmission transistor 35 (hereinafter referred to as the transmission signal wiring 42); the signal lines are used to control the transmission signal wiring of the transmission transistor 36 (hereinafter: transmission setting) Signal wiring 43). Figure 2 shows the map! A circuit diagram of the overall configuration of the second-order pixel of the solid-state imaging device of the pixel structure shown. After the light-receiving surface of the solid-state imaging device is opened, 甶 甶 甶 (one-person 疋 pixel block) is composed of two pixels as a unit cell and arranged as a second element. However, the constant current supply transistor 8 is used to supply a constant current transistor to the pixel output line, which supplies a constant current to the amplifying transistor 38 of the selected pixel to operate as a common (four) configuration, and produces a phase at the pixel output (4). The potential at the gate potential of the amplifying transistor 38 has a specific voltage difference. The terminal 44 is connected to the input terminal on the side of the column selection AND elements 45 and 46 for supplying the pulse terminals of the respective (four) feed (four) lines 42 and 43 to the side of the row selection AND elements 45 and 46. The input is connected to the output from the vertical selection means 15. Further, the column selection AND elements and the output terminals of the NMOS are connected to the transmission signal wirings 42, 43. The terminal 47 is for supplying a reset pulse to the pulse terminal of each column reset signal wiring 41, and is connected to the wheel terminal of one side of the column selection AND element 48, and the output terminal of the column selection sensor element 48 is connected. Reset signal wiring (4). Further, the output of (10) electric O:\87\87775.DOC -15-way 49 is connected to the other input terminal of the column selection AND element 48. The OR circuit 49 is selected vertically for the eight people. The / knife is connected to the two columns in which the upper two pixels are located, that is, the lines 15 Α and 15 Β ' and output the waveforms of the signals of the two columns. The gates 33, 34 selected by each letter-selection means 15 will be gated at the pixel 5 from the photoelectric conversion element, and the letter from the pulse terminal 47 will be added. l, j_, ^ signal wiring, and drive the full signal line 39, the straw to read out. Figs. 3A to 3D are timing charts showing the state in which the respective signals of the signals are clocked from the pixels in the pixel structure of this example. . The signals shown in FIGS. 3A to 30 are respectively added to the readout column, and the input signal, the reset signal, and the transmission signal are respectively added to the full signal line 39 and the reset signal of FIG. The wiring 41 and the signal of the signal wiring core and the 4 3 are transmitted. First, the reading operation will be described by taking FIG. 3 as an example. ▲In the initial state, the reset signal and transmission signal are all set to l〇w (non-effective). The king selection signal is set to High. Secondly, as long as the reset signal is changed to Hlgh, the potential of the idle pole of the amplifying transistor W of each pixel is reset to the output of the full selection signal. Here, after the reset signal is turned into Low, the weight is increased. The set relative potential is read out to the pixel wheel output line and its voltage value is accumulated in the CDS circuit. Then, the transfer signal is converted to Hlgh, the charge accumulated in each photoelectric conversion element is transferred to the gate portion of the amplifying transistor 38, and after the transfer is completed, the transfer signal is turned to Low, and the photoelectric conversion elements are accumulated. The relative potential of the charge number O: \87\87775.DOC -16- 200425727 is read out to the CDS circuit via the pixel output line, and the difference between the reset level and the signal level is obtained in the CDS circuit. After the completion of the subsequent series of readout operations, the full selection signal is turned to change the reset 彳5唬 to HiSh, and the input portion of the amplifying transistor 38 is reset. If a depleted transistor is used as the reset transistor, the reset of the amplifying transistor input portion can be performed as long as the full selection signal is Low, so that it can be driven by the waveform shown in Fig. 3B. Further, Fig. 3C to Fig. 3D are modified from Figs. 3 to 33, and the full selection signal is set to Hlgh only during the read operation. The structure of X can make the pixel structure more simplified than ever. That is, in the configuration of the previous example shown in FIG. 11, the number of transistors per pixel is two, the relative 'in this pixel configuration is two, and the number of signal lines is reduced from two to five (ie, The full signal line also serves as a light-shielding film; that is, the full-scale signal line, like the well-known light-shielding film of a solid-state imaging device, each pixel having an opening corresponding to the light-receiving surface). In the case of the second Si, since the capacitance is formed by deviating from a specific pixel, the sensitivity and the saturation signal between the pixel of the p-valley and the pixel of the non-capacitance are formed, but according to the configuration of the embodiment, the in-plane signal line is used to control the amplification. The reset level of the transistor input portion is read out to the outside of the sound, so there is no need to form a capacitor, so that the problem can be solved. Further, compared with the configuration of the prior art shown in Fig. 12, the capacitance of each of the capacitors 'each pixel is also "reduced". Into ^. 5, more

O:\87\87775.DOC -17- 200425727 (弟二實施例） 如上述圖12所示之先前例子或第-實施例(圖υ的構成 例’令兩個光電轉換元件共有放大、重置電晶體等的手法， 可以減少每1象素之電晶體數和信號配線數，有益於像素 尺寸的細小化。然而，正如先前技術課題中之說明，要使 上下各光毛轉換兀件、傳送閘極具有完全相同的形狀和特 1± ’貝屬困難。因此，將單位胞排列成二次元陣列狀，而 施以拜耳模式的彩色濾光時，因兩個G濾光片斜向放置，所 以RG列的G和GB列的G之間的像素特性會有所不同。 一在此’本實施例中，將圖1所示之單位胞如圖4所示，於 每行上下各錯開一像素進行配置。此外，圖4中除了單位 胞之配置改受’且每列的各控制配線之連接端皆不同以 外，其餘均與H2所示之構成為共通，所以，針對共通的構 成要素標註同一符號並省略逐一說明。 藉由此種配置，每-像素之信號線則從1.5條增至2條。 然而’取而代之以在R列的0和Β列的G使用相同形狀之像O:\87\87775.DOC -17- 200425727 (Second Embodiment) The previous example or the first embodiment shown in Fig. 12 (the configuration example of Fig. 2) causes the two photoelectric conversion elements to be amplified and reset in common. A method such as a transistor can reduce the number of transistors per 1 pixel and the number of signal lines, which is advantageous for miniaturization of the pixel size. However, as explained in the prior art, the upper and lower bristles are converted and transferred. The gates have exactly the same shape and are difficult to use. Therefore, the unit cells are arranged in a quadratic array, and when the Bayer mode color filter is applied, the two G filters are obliquely placed. Therefore, the pixel characteristics between the G of the RG column and the G of the GB column may be different. In this embodiment, the unit cell shown in FIG. 1 is shifted as shown in FIG. In addition, in Fig. 4, except that the configuration of the unit cells is changed by 'and the connection ends of the control lines of each column are different, the rest is the same as the configuration shown by H2, so the common constituent elements are labeled. The same symbol is omitted and explained one by one. Configuration, each - of the pixel from the signal line 2, however increased to 1.5 'to replace the R and G Β row 0 column using the same shape of the image.

素，故而可防止如繁一本A 戈弟，、轭例的情況下可預料的列之間之g 像素特性差。 更具體而g，例如像素所含之傳送電晶體，於R列的G和 B列的G之相對像素中，是與來自光電轉換部之電荷讀出成 同一方向配置，所ιν #+ 所以傳迗電晶體之雜質區域的電位對於光 電轉換部的電位所帶來的影響會顯現在光電轉換部大致相 同的位置’故而避免産生光電轉換部之感度與飽和信號量 的差異。Therefore, it is possible to prevent the difference in g pixel characteristics between the predictable columns in the case of the yoke case. More specifically, for example, the transfer transistor included in the pixel is disposed in the same direction as the charge from the photoelectric conversion portion in the G and the opposite pixel of the G column of the R column, and the ιν #+ The influence of the potential of the impurity region of the germanium crystal on the potential of the photoelectric conversion portion appears at substantially the same position of the photoelectric conversion portion, so that the difference between the sensitivity of the photoelectric conversion portion and the saturation signal amount is avoided.

O:\87\87775.DOC -18- 200425727 此外，圖4例中，所示之情形雖然為兩個像素共有一個電 晶體’且於每一列將單位胞上下錯開一像素，但即使改變 像素數或單位胞的偏移量，也可同樣適用。 (弟二實施例） 圖5為表示本發明之第三實施例的像素構造電路圖，其係 顯示斜向鄰接之兩個光電轉換元件間共有重置電晶體、放 大電晶體、重置信號線和全面信號線之例。再者，圖^之構 成具有與圖丨所示者共通的構成要素，只是配置有些改變， 所以，針對共通的構成要素均標註同一符號並省略逐一說 明。 當於排列有此種單位胞的受光部中採用拜耳模式的彩色 濾光片時，其信號就會以圖6B所示的順序輸出。 / 在此，由於通常之像素構成中係、以如i6A之情形進行輪 出，因此，為配合通常的信號系統處理、 在奇數或偶數列進行將圖6B之信號各錯開—像素:處=要 广如先前例之說明’通常來自各像素的信號係二為 早位而讀出到咖電路，其後，藉以行選擇手 = 列信號會通過水平作骑娩，私％机 丨^疋的 取至外部。κι線，於後段的咖等加以處理並讀 士圖1 3所述’將以往為_個系統之此 娜個，並列方式向外部讀出來自各像素：分 藉此可以更南速進行像素取樣。 μ别出， {疋-將輪出系統分成複數個，除了電路 以外，輸出系統間的# a介各#、 吟了電路面積増大 、，、亦a成為問題。特別是以拜耳模O:\87\87775.DOC -18- 200425727 In addition, in the example of Fig. 4, the case shown is that two pixels share one transistor 'and one unit is shifted up and down by one pixel in each column, but even if the number of pixels is changed Or the offset of the unit cell can also be applied. (Second Embodiment) Fig. 5 is a circuit diagram showing a pixel structure of a third embodiment of the present invention, which shows that a reset transistor, a magnifying transistor, a reset signal line, and the like are displayed between two photoelectric conversion elements which are obliquely adjacent to each other. An example of a comprehensive signal line. In addition, the configuration of the figure has the same components as those shown in the figure, but the configuration is somewhat changed. Therefore, the same components are denoted by the same reference numerals, and the description thereof will be omitted. When a color filter of the Bayer pattern is used in the light receiving portion in which such unit cells are arranged, the signals are output in the order shown in Fig. 6B. / Here, since the normal pixel structure is in the middle and is rotated as in the case of i6A, the signals of FIG. 6B are shifted in order to cope with the usual signal system processing in odd or even columns - pixel: As explained in the previous example, 'the signal system from each pixel is usually read early to the coffee circuit, and then the row selects the hand = the column signal will be passed through the level for childbirth. To the outside. Κι line, in the latter paragraph of the coffee and so on and read the words shown in Figure 13. 3 'will be a system of the past, the side-by-side way to read out from each pixel: the point can be more south-speed pixel sampling . μ don't come out, {疋- divides the round-out system into multiples. In addition to the circuit, the #a介# between the output systems, the circuit area is large, and a is also a problem. Bayer mode

O:\87\87775.DOC -19- 200425727 式進行色彩編碼時，RG列的g#〇gb?iJG則有可能由於處理 系統不同而產生增益差且出現橫線。具體如圖14中所說明。 對此，本發明之第三實施例中，如圖5所示，考慮以斜向 兩像素共有重置、放大電晶體、重置信號配線及全面信號 =形’則如圖7所示，咖之間係自相同的像素輸出 線輸出’因此可以相同之輸“統處理來自G像素之輸出， 以相同的處理系統讀出各列之〇’且能夠用較以往單一輸出 系統方式快上一倍的速度進行取樣。 又：此第三實施例為兩個像素共有電晶體時之一例，但 也可適用於共有像素數或各像素錯開未滿_像素予以配置 之情形’當然，此手法也可適用於圖8或圖12所示之像素構 造或其他像素構造。 ^外’本發明之固體攝影裝置亦可含有上述構成以外的 構成’例如圖1 0中盘光學系 ^ ^ τ 一尤干糸統或“號處理晶片組合的照相 機权組式之固體攝影裝置亦可。 再者’像素之二次元排列的列和行、垂直方向和水平方 向亚無貫質性區別’例如，如果將像素排列於大致直行之 上’則依據看向固體攝影裝置的方向，像素列也就 疋像素行，反之亦同。 藉由以上本發明之各實施例，可得如下之效果·· (第一實施例） 綠I炎像素間之電晶體共有化，並進一步使用全面驅動配 ，Ά 5虎線’错此可大幅減少每一像素的電晶體數和信 線數，進而可實現像素尺寸之縮小。When color coding is performed by O:\87\87775.DOC -19- 200425727, the g#〇gb?iJG of the RG column may have a gain difference and a horizontal line due to the difference in the processing system. Specifically, as illustrated in FIG. In this regard, in the third embodiment of the present invention, as shown in FIG. 5, it is considered that the two pixels in the oblique direction share the reset, the amplifying transistor, the reset signal wiring, and the full signal = shape 'as shown in FIG. The output is from the same pixel output line 'so the same output can be processed from the output of the G pixel, read out the columns in the same processing system' and can be doubled faster than the previous single output system The speed is sampled. Further, this third embodiment is an example in which two pixels share a transistor, but it can also be applied to a case where the number of shared pixels or each pixel is shifted by less than _ pixels. Of course, this method can also be used. It is suitable for the pixel structure or other pixel structure shown in Fig. 8 or Fig. 12. The solid-state imaging device of the present invention may also contain a configuration other than the above-described configuration, for example, the optical system of the disk in Fig. 10 It is also possible to use a solid-state imaging device of the camera right type of the combination of the wafer processing unit. Furthermore, the column and row of the pixel's quadratic arrangement, the vertical direction and the horizontal direction have no sub-quality difference 'for example, if the pixels are arranged on a substantially straight line', the pixel column is also in accordance with the direction of the solid-state imaging device. Just 疋 pixel rows, and vice versa. According to the embodiments of the present invention described above, the following effects can be obtained: (First Embodiment) The transistors between the green and inflammatory pixels are shared, and the full-drive device is further used, and the 虎 5 tiger line is wrong. By reducing the number of transistors and the number of lines per pixel, the pixel size can be reduced.

O:\87\87775 DOC -20- 200425727 (第二實施例） ^者’對於像素間進行電晶體共有化的問題， 於因使用不同形狀之#I ”疋關 差，可_由改作^ ” 肖色遽光之像素間的特性 伟田胞之配置方法使同色遽光的像素-律 使用形狀相同之像素而得以解決。 μ律 朝雖就將（相對於以拜耳模式^濾光之攝影面 向排列之二像素共有晶體管之類型）單位胞於每行 上下錯開一像素而設之構 配置方法d，、一 但依據單位胞 °又心以同色濾光之像素使用同形狀者之手法 ，也可適用於其他彩色遽光、像 i主之又π σσ m I偁k。又，根據構 之：：，早位胞的配置方法未必以一像素為準，亦可視 清況考里錯開未滿一像素的作法。 (第二實施例） 面為二’而自以拜耳模式予以遽光之攝影 2的各像素讀出時，在—般之像素構成中，由於 u八„ (狀G像素和GB列之G像素）之輸出系統 :刀：’因而會受到輸出系統間之差異所造成的影響，而 ^出現橫線’而採用上下兩個像素實施像素間電晶體 之情形雖然也有同樣的情形，但在本實施例中，藉 由以斜向的兩個像素實施像素間電晶體共有化’能夠以同 一輸出系統讀出來自Gr、Gb像素之輪出。因此，即使在輪 出系關產生製程上的差異，也不會受其影響，而能夠以 比^用早輪出线讀出時快上_倍的速度進行取樣。 斤述I據本發明之固體攝影裝置，藉由像素間電O:\87\87775 DOC -20- 200425727 (Second embodiment) ^The problem of performing transistor commonalization between pixels is due to the use of different shapes of #I", which can be changed to ^" The characteristics of the pixels of the sacred light are placed in a way that the pixels of the same color are resolved using pixels of the same shape. The μ law is a configuration method d that is set to be shifted by one pixel from the top of each row (relative to the type of the two-pixel shared transistor in which the image is arranged in the Bayer mode), and is based on the unit cell. ° The heart uses the same shape of the pixels of the same color filter, but also applies to other color 遽, like i main π σσ m I偁k. Moreover, according to the configuration::, the configuration method of the early cells is not necessarily based on one pixel, and it is also possible to stagger the less than one pixel. (Second Embodiment) When the pixels of the photograph 2 which are calendered in the Bayer mode are read out, the pixels are read by the Bayer pattern, and in the general pixel configuration, the U-eight pixels (the G-pixels and the G-pixels in the GB column) The output system: knife: 'Therefore, it will be affected by the difference between the output systems, and ^ appears horizontal line' and the upper and lower pixels are used to implement the inter-pixel transistor. However, the same situation exists, but in this implementation In the example, by performing inter-pixel transistor sharing by two pixels in an oblique direction, it is possible to read out the rounds from the Gr and Gb pixels in the same output system. Therefore, even if the round-trip system causes a difference in the process, It is also unaffected by it, and can be sampled at a speed that is _ times faster than when it is read out by the early round. 千述 I According to the solid-state imaging device of the present invention, by inter-pixel power

O:\87\87775.DOC -21- 200425727 曰曰 曰曰 體之共有化及全面信號線之❹，可減少每—像素之電 體數及信號配線數，實現像素尺寸之縮小化。 又，即使對於像素間電晶體共有化之問m就是不 *同形㈣像素間之特性差或雙輸出系統間之增益差，亦可 藉由單位胞之配置或斜而庶& 直次斜向兩像素間之共有等辦法，而得以 抑制像素間、特別是來自G實施清杏 慮先之像素的信號之特性 差〇 【圖式簡單說明】 圖1為表示本發明第-實施例之像素構造的電路圖。 圖2為表不適用於圖1 構成的電路圖。 ”料構4的固體攝影裝置之 /3A〜3D為表示在圖1所示之像素構造中，自像素讀師 號呀各驅動信號之情形的時序圖。 ’、° 圖4為表示本發明第—音 電路圖。 《一貫施例之固體攝影裝置之構成的 =表示本發明第三實施例之像素構造的電路圖。 6B為表不在圖5所示之像素構μ 早一糸統的輸出部之作動例的說明圖。 出至 圖7為表示在圖5所干 咬的幹出π * 像素構造下將信號讀出至兩料 、.先的輪出部之作動例的說明圖。 1U^ 圖8為表示以往具有筮_ 成之電路圖。~ 素構造之固體攝影裝置的構 圖9為表示圖§所示之 ® l〇A * . 冢素構&中之驅動例的時序圖。 為表心組化之固體攝影裝置圖。O:\87\87775.DOC -21- 200425727 曰曰 共有 共有 共有 共有 及 及 及 及 及 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有 共有Moreover, even if the inter-pixel transistor sharing is m, the difference between the characteristics of the non-homogeneous (four) pixels or the gain difference between the two output systems can be achieved by the configuration or skew of the unit cells. Between the two pixels, etc., it is possible to suppress the characteristic difference of the signals between the pixels, in particular, the pixels from the G-priest. [Fig. 1 is a diagram showing the pixel structure of the first embodiment of the present invention. Circuit diagram. Figure 2 is a circuit diagram of the table not applicable to Figure 1. 3A to 3D of the solid-state imaging device of the material structure 4 are timing charts showing the state of the driving signals from the pixel reading unit in the pixel structure shown in Fig. 1. ', ° FIG. 4 is a view showing the present invention. - Sound circuit diagram. The configuration of the solid-state imaging device of the conventional embodiment is shown in the circuit diagram of the pixel structure of the third embodiment of the present invention. 6B is an example of the operation of the output portion of the pixel structure shown in FIG. Fig. 7 is an explanatory view showing an example of the operation of reading the signal to the two materials and the first rounding portion in the dry π* pixel structure of the dry bite of Fig. 5. 1U^ Fig. 8 is It is a circuit diagram of a solid-state imaging device having a structure of 筮 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Solid photography device diagram.

O:\87\87775.DOC -22- 200425727 =11為表^以往之第二像素構造的電路圖。 Θ12為表示以往之第三像素構造的電路圖。 圖13為表示以往具有雙系 的電路圖。 “ ··先輪出的固體攝影裝置之構成 圖14為表示圖13所示之固體攝影裝置中 的說明圖。 之信號讀出動作 【圖式代表符號說明】 12, 3, 4, 6 10 11 12 13 14，17，19, 45, 46, 48 15 光電轉換元件 電晶體 · 電源電位供給線 像素輸出線 像素外之電晶體 傳送信號配線 重置信號配線 選擇信號線 恆電位供給線 向各列之傳送信號配線9供給傳送 脈衝用的脈衝端子 列選擇用AND元件 垂直選擇手段 15A? 15B 16 18 垂直選擇信號線 向各列之重置信號配線10供给傳 送脈衝用的脈衝端子 向各列之選擇信號線11供給傳送O:\87\87775.DOC -22- 200425727 =11 is a circuit diagram of the second pixel structure of the prior art. Θ12 is a circuit diagram showing a conventional third pixel structure. Fig. 13 is a circuit diagram showing a conventional double system. Fig. 14 is a view showing the solid-state imaging device shown in Fig. 13. The signal reading operation [illustration representative symbol] 12, 3, 4, 6 10 11 12 13 14,17,19, 45, 46, 48 15 Photoelectric conversion element transistor · Power supply potential supply line Pixel output line Pixel output signal wiring wiring reset signal wiring selection signal line constant potential supply line to each column The transmission signal line 9 is supplied with a pulse terminal for selecting a pulse terminal. The AND element vertical selection means 15A to 15B 16 18 The vertical selection signal line supplies a pulse terminal for each pulse to the reset signal line 10 of each column. Line 11 supply transfer

O:\87\87775.DOC -23- 200425727 脈衝用的脈衝端子 20， 114 21 22 23 24 30 31，32 33, 34 35, 36 37 38 39 40 41 42, 43 44 47 49 111 112 CDS(相關倍頻取樣）電路 選擇手段 水平信號線 電容 配線 單位胞 像素 光電轉換元件 傳送電晶體 重置電晶體 放大電晶體 全面信號線 像素輸出線 重置信號配線/重置信號系統配線 傳送信號線 傳送恆定信號配線 向各列重置信號配線41供給重置 脈衝用的脈衝端子 OR電路 感測器部 垂直驅動電路 113 快門驅動電路 115 水平驅動電路 O:\87\87775.DOC -24- 200425727 116 時序脈波產生器 117A， 117B AGC電路 118A， 118B ADC電路 119A， 119B 水平信號線 O:\87\87775.DOC -25 -O:\87\87775.DOC -23- 200425727 Pulse terminals for pulses 20, 114 21 22 23 24 30 31,32 33, 34 35, 36 37 38 39 40 41 42, 43 44 47 49 111 112 CDS (related Frequency doubling sampling) Circuit selection means horizontal signal line capacitance wiring unit cell pixel photoelectric conversion element transmission transistor reset transistor amplification transistor full signal line pixel output line reset signal wiring / reset signal system wiring transmission signal line transmission constant signal The wiring is supplied to the reset signal wiring 41 of each column. The pulse terminal for supplying the reset pulse is OR circuit sensor portion vertical drive circuit 113. The shutter drive circuit 115 is horizontally driven circuit O: \87\87775.DOC -24- 200425727 116 Time-series pulse wave Generator 117A, 117B AGC circuit 118A, 118B ADC circuit 119A, 119B horizontal signal line O:\87\87775.DOC -25 -

Claims (1)

200425727 拾、申請專利範圍： L 一種固體攝影裝置，其特徵在於具有： /特疋數里之像素為_組而構成的複數個單位胞成二 -車列狀配置而構成之攝影區域部，以及用於選擇前 述各像素的信號配線； 前料位胞具有：對應於各像素之複數個光電轉換元 由前述各像素所共有，將讀出自各光電轉換元件的 信號量放大並輸出之放大手段，以及選擇性讀出來自各 光電轉換元件之信號並提供給前述放大手段之傳送手 段； 驅動削述放大手段之信號配線係包括就全像素共通配 線之全面信號線，藉由驅動前述全面信號線而讀出來自 各像素之信號。 2·如申請專利範圍第1項之固體攝影裝置，其中具有重設前 述放大手段之輸入部之重置手段。 3，如申請專利範圍第2項之固體攝影裝置，其中驅動前述重 置手段之信號配線係包括前述全面信號線，並藉由驅動 前述全面信號線以重置各放大手段之輸入部。 4. 如申請專利範圍第1項之固體攝影裝置，其中於前述攝影 區域部之各像素的每一行上，朝行方向各錯開一像素或 未滿一像素而配置有前述單位胞。 5. 如申請專利範圍第2項之固體攝影裝置，其中驅動前述重 置手段和放大手段之前述全面信號線的全面選擇信號係 於前述像素之讀出動作期間以外從有效轉變為非有效。 O:\87\87775.DOC 200425727 6. 其中前述重置手 内使前述全面信 如申请專利範圍第2項之固體攝影裝置， 段包括電晶體，於前述像素之讀出期間 號線之全面選擇信號轉變為有效，輪入至前述重置手段 之閘極的重置信號轉變為非有效，提供給前述傳送手段 的驅動信號轉變為有效，而讀出光電轉換元件所累積的 電荷信號。 7· —種固體攝影裝置，其特徵在於 具有.以特定數量之像素為—組而構成的複數個單位 胞成二次元陣列狀配置而構成之攝影區域部，以及用於 選擇前述各像素的信號配線； 前述單位胞具有：對應於各像素之複數個光電轉換元 件；由前述各像素所共有，將讀“各光f轉換元件的 信號量放大並輸出之放大手段；以及選擇性讀出來自各 光電轉換元件之信號並提供給前述放大手段之傳送手 段； 别述單位胞之各光電轉換元件係成斜向鄰接配置。 8. 如申請專利範圍第7項之固體攝影裝置，其中前述斜向鄰 接之各光電轉換元件係朝水平方向或垂直方向錯開未滿 一像素予以配置。 9. 如申請專利範圍第7項之固體攝影裝置，其中驅動前述放 大手段之信號配線係包括就所有像素共通配線之全面信 號線，藉由驅動前述全面信號線以讀出來自各像素之^ 號。 · '口 10·如申請專利範圍第9項之固體攝影裝置，其中具有重設前 O:\87\87775.DOC 200425727 述放大手段之輸入部的重置手段。 "•如申請專利範圍第10項之固體攝影裝置，其中驅動前述 重置手段之信號配線係包括前述全面信號線，藉由驅動 月丨j述全面信號線以重設各放大手段之輸入部。 12. 如申請專利範圍7項之固體攝影裝置，其中係將來自前述 攝影區域部的各像素之輸出信號分成兩個輸出系統讀 出。 ' 13. 如申請專利範圍第12項之固體攝影裝置，其中在前述攝 影區域部設有RGB拜耳模式之彩色濾光片，其介以同— 輸出系統從經過G濾光之各像素進行讀出。 14·如申請專利範圍第10項之固體攝影裝置，其中驅動前述 重置手段和放大手段之前述全面信號線的全面選擇信號 係於前述像素之讀出動作期間以外從有效轉變為非有 效。 15·如申請專利範圍第10項之固體攝影裝置，其中前述重置 手段包括電晶體，於前述像素之讀出期間内使前述全面 信號線之全面選擇信號轉變為有效，輸入至前述重置手 段之閘極的重置信號轉變為非有效，供給前述傳送手段 之驅動信號轉變為有效，而讀出光電轉換元件所累積之 電荷信號。 16· —種固體攝影裝置，其具有以特定數量之像素為一組而 構成的複數個丰位胞成一次元陣列狀配置而構成之攝景；; 區域； 前述單位胞具有：將從前述像素内含之光電轉換部讀 O:\87\87775.DOC 200425727 出的電荷進行放大之放大電晶體；重設前述放大電晶體 之輸入部的重置電晶體；以及連接於前述放大電晶體並 可改變放大電晶體之重置位準的信號線； 包含於前述單位胞中之至少兩個像素係共有前述放大 電晶體； 前述信號線係就所有像素共通地形成。 17·如:請專利範圍第16項之㈣攝影裝置，其中具有配置 於則述攝影區域之每一像素行的輪出信號線； 在前述像素上配置有拜耳排列之彩色濾光片的各色濾 光片； 〜 配置有鄰接的紅色遽光片和藍色攄光片之雙像素係共 有一條前述輸出信號線； 配置有鄰接的兩個綠色遽光片之雙像素係共有—條前 述輸出信號線。 1δ.如中請專利範圍第17項之固體攝影裝置，其中具有對應 於複數個前述輸出信號線而形成之至少兩二 號線， 科〗出仏 :來自對應於則述彩色遽光片之綠色濾光片的所有像 素之信號讀出到同一前述水平輪出信號線。 19.Π:=範圍第16項之固體攝影裝置，其中在前述像 部讀…，色遽光片；前述像素具有從前述光電轉換 了的傳送電晶體；對應於前述彩色渡光片之终 色濾先片的所有像素係藉由前述傳送電晶 讀出電荷。 刊U ~方向 O:\87\87775.DOC 200425727 20.如申請專利範圍第16項之固體攝影裝置，其中前述信號 線係具有對應於前述光電轉換部之開口而具有遮光層之 功能。 O:\87\87775.DOC200425727 Pickup, Patent Application Range: L A solid-state imaging device, characterized in that: a plurality of unit cells formed in a plurality of units are in a two-car array configuration, and a photographing area portion is formed. a signal line for selecting each of the pixels; the pre-growth cell has: a plurality of photoelectric conversion elements corresponding to each pixel shared by the respective pixels, and an amplification means for amplifying and outputting a signal amount read from each photoelectric conversion element, And a transmission means for selectively reading signals from the photoelectric conversion elements and supplying the amplification means; and the signal wiring for driving the thinning amplification means comprises a comprehensive signal line for the all-pixel common wiring, by driving the comprehensive signal line The signals from each pixel are read. 2. The solid-state imaging device of claim 1, wherein the resetting means for resetting the input portion of the amplifying means is provided. 3. The solid-state imaging device of claim 2, wherein the signal wiring for driving the reset means comprises the aforementioned full signal line, and the input portion of each of the amplification means is reset by driving the aforementioned full signal line. 4. The solid-state imaging device according to claim 1, wherein the unit cell is disposed in each row of each pixel of the photographing region portion by one pixel or less than one pixel in the row direction. 5. The solid-state imaging device according to claim 2, wherein the comprehensive selection signal of the integrated signal line for driving the reset means and the amplifying means is converted from valid to inactive other than the readout period of the pixel. O:\87\87775.DOC 200425727 6. In the foregoing resetting hand, the above-mentioned comprehensive letter, such as the solid-state imaging device of the second application patent scope, includes a transistor, and is fully selected in the reading period of the aforementioned pixel. The signal transitions to be effective, the reset signal that is turned to the gate of the aforementioned reset means is turned into inactive, the drive signal supplied to the aforementioned transfer means is turned into active, and the charge signal accumulated by the photoelectric conversion element is read out. A solid-state imaging device comprising: a photographing region portion configured by arranging a plurality of unit cells in a plurality of arrays with a specific number of pixels as a group, and a signal for selecting each of the pixels The unit cell has: a plurality of photoelectric conversion elements corresponding to the respective pixels; and an amplification means for amplifying and outputting the signal amount of each of the optical f conversion elements by the respective pixels; and selectively reading out each The signal of the photoelectric conversion element is supplied to the transmission means of the amplifying means; the photoelectric conversion elements of the unit cell are arranged in an obliquely adjacent configuration. 8. The solid-state imaging device of claim 7, wherein the obliquely adjacent Each of the photoelectric conversion elements is disposed in a horizontal direction or a vertical direction by being shifted by less than one pixel. 9. The solid-state imaging device according to claim 7, wherein the signal wiring system for driving the amplification means includes common wiring for all pixels. A full signal line that reads the number from each pixel by driving the aforementioned full signal line. '口10·, as in the solid-state imaging device of claim 9 of the patent application, wherein there is a resetting means for resetting the input portion of the magnifying means before O:\87\87775.DOC 200425727. "•If the patent application scope is 10th The solid-state imaging device of the present invention, wherein the signal wiring system for driving the resetting means comprises the above-mentioned comprehensive signal line, and the input signal portion of each of the amplifying means is reset by driving the full-scale signal line. 12. As claimed in claim 7 The solid-state imaging device in which the output signal of each pixel from the photographic area portion is divided into two output systems. [13] The solid-state imaging device of claim 12, wherein the photographic area portion is provided The color filter of the RGB Bayer mode is read from the G-filtered pixels through the same-output system. 14· The solid-state imaging device of claim 10, wherein the aforementioned resetting means and amplification are driven The comprehensive selection signal of the foregoing comprehensive signal line of the means is converted from valid to inactive except during the readout operation of the aforementioned pixel. The solid-state imaging device of claim 10, wherein the resetting means comprises a transistor for converting a comprehensive selection signal of the full-scale signal line into an active signal during a readout period of the pixel, and a reset signal input to a gate of the resetting means When the conversion is inactive, the drive signal supplied to the transfer means is converted to be effective, and the charge signal accumulated by the photoelectric conversion element is read. 16· A solid-state imaging device having a plurality of pixels formed by a specific number of pixels The unit cell has a single-element array configuration; the area; the unit cell has: the charge from the photoelectric conversion unit included in the pixel is read to read O:\87\87775.DOC 200425727 Amplifying the transistor; resetting the reset transistor of the input portion of the amplifying transistor; and connecting a signal line connected to the amplifying transistor and changing a reset level of the amplifying transistor; at least two included in the unit cell Each of the pixel systems has the aforementioned amplifying transistor; the signal line is formed in common for all the pixels. [17] For example, in the fourth aspect of the invention, in the fourth aspect, the photographing device has a rounding signal line disposed in each pixel row of the photographing region; and each color filter of the Bayer array color filter is disposed on the pixel. a two-pixel system in which a pair of adjacent red and green pupils are disposed; one of the output signal lines; and a two-pixel system in which two adjacent green phosphors are disposed to share the aforementioned output signal line . 1 δ. The solid-state imaging device of claim 17, wherein at least two of the two lines formed corresponding to the plurality of the output signal lines are selected from the green color corresponding to the color light-emitting sheet. The signals of all the pixels of the filter are read out to the same horizontal rounding signal line. 19. The solid-state imaging device of item 16, wherein the image portion is read, the color light-slicing sheet; the pixel has a transfer transistor that is photoelectrically converted; and corresponds to a color of the color light-emitting sheet All of the pixels of the filter are read out by the aforementioned transfer transistor. The solid-state imaging device of claim 16, wherein the signal line has a function of having a light shielding layer corresponding to an opening of the photoelectric conversion portion. O:\87\87775.DOC
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