200423395 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係有關一種半導體裝置及一種製造半導體裝置 之方法，而更明確地係有關一種減少相關於一具有一或更 多像素之像素區的周邊電路區之面積的技術。本發明亦有 關一種增進像素區之孔徑比的技術，藉由透過一多層佈線 以提供周邊電路區（“邊界框”）一較小的寬度。 【先前技術】 圖6係一平面圖，其槪略地顯示一種習知液晶顯示裝 置中之晶片。 液晶顯示裝置中之此晶片具有一像素區1 0 1，其具有 平面上之正方形。像素區101包含一或更多像素。像素區 1 〇 1之周邊配置有周邊電路1 0 2 a至1 0 2 c。晶片被配置於 一基底上（或者此晶片及類似晶片被配置於相同基底 上）。周邊電路102a至102c各具有平面上之薄矩形形 狀，且各矩形之短邊長度爲2至3 mm。每一周邊電路需 要2至3 mm之寬度的原因係因爲周邊電路中所形成之電 源供應線、時脈線、及其他佈線的寬度係於數十至數百V m之等級，因而佔據大面積。 周邊電路102a至102c具有TFTs (薄膜電晶體）。 那些TFTs具有形成自一耐火金屬（諸如聚矽或w )之閘 極電極。閘極電極係用以供應一閘極電壓至特定的TFT 活性層，而多數TFTs之閘極電極係彼此電連接。閘極電 (2) 200423395 極被電連接至交叉的佈線。佈線係將多數TFTs彼此電 接，且被置於閘極電極上方之層。佈線亦將TFTs連接 像素電極。佈線具有一疊層結構，包含（例如）一 A1 及一障蔽金屬膜。障蔽金屬膜係Ti、TiN、Ta、TaN、 等之單一層或多層結構。 佈線層上方之層中形成以一黑色遮罩，其爲A1 寺。黑色遮罩具有光遮敝功目^及電位阻檔能力。一像素 極被形成自黑色遮罩上方之層中的I TO。 [參考 1 : JP 09-43 63 0 A] 如上所述，周邊電路區（構成像素區周圍之一 “邊 框”的周邊電路）具有2至3 mm之寬度。周邊電路區 望具有一較窄的寬度，因爲周邊電路區（邊界框）之寬 減少導致像素區之孔徑比的增進。爲了執行，周邊電路 之寬度減少提供像素區較大的面積（當晶片尺寸係相等 因而各像素之面積增加時），因而增加的各像素中之孔 的面積並增進亮度。另一方面，當像素區具有相同面 時，周邊電路區之寬度減少使其得以減少晶片尺寸且晶 變得更適於大量生產。 於上述習知液晶顯示裝置中，佈線層係單一層且提 佈線層中之整合程度是困難的，由於光微影術系統等之 制。當佈線被形成於相同層中時，佈線佔據了大面積且 動器電路及其他周邊電路之面積與整個晶片面積的比例 而是很大的，其導致周邊電路區之寬度減少的障礙。 連 至 膜 W 膜 電 界 希 度 區 且 徑 積 片 升 限 驅 因 -6- (3) (3)200423395 當周邊電路區具有大寬度時，將多數像素彼此電連接 之佈線亦傾向於具有延伸的長度，因爲佈線係橫越像素 區。如此可能導致佈線之高於理想的電阻値及供應至 TFTs之電流的短缺。 此外，佈線底下之層中所形成的閘極電極常被製成較 厚以降低閘極電極之電阻。較厚的閘極電極增加了佈線層 之基極中的位準差異以利減少佈線形成時之圖案化邊際。 如此可能導致已圖案化之佈線中的位準中斷。 【發明內容】 本發明係有鑑於上述情況而產生，且本發明之一目的 因而係提供一種用以減少相對於一像素區之周邊電路區的 面積之技術。特別地，本發明之一目的係藉由透過一多層 佈線以提供周邊電路區（“邊界框”）一較小的寬度而增進 像素區之孔徑比。 爲了解決上述問題，依據本發明，提供一種半導體裝 置，包含： 一像素區； 一周邊電路區，其係置於一圍繞像素區之區域的至少 一部分；及 一佈線’其係形成自周邊電路區中之一低電阻材料。 依據上述半導體裝置，周邊電路區中之佈線被形成自 一低電阻材料’藉此賦予佈線一較小的寬度。因此，相對 於像素區面積之周邊電路區面積可被減少。 (4) (4)200423395 依據本發明，提供一種半導體裝置，包含·· 〜像素區； ~周邊電路區，其係置於一圍繞像素區之區域的至少 —部分；及 ~佈線，其係形成於周邊電路區中， 其中佈線係一具有兩或更多層之多層佈線。 ί衣據上述半導體裝置，周邊電路區中所形成之佈線係 ~多層佈線且因而周邊電路區（邊界框）被賦予一較小寬 度°以此方式，像素區可具有增進的孔徑比。 依據本發明，提供一種半導體裝置，包含： 一像素區； 一周邊電路區，其係置於一圍繞像素區之區域的至少 一部分； T F Τ ’ s之閘極電極，其係形成於周邊電路區中；及 一佈線，其係形成於閘極電極上方或下方之一層中且 連接至閘極電極， 其中不同TFTs中之閘極電極係彼此隔離。 此外，於依據本發明之半導體裝置中，佈線最好是一 具有兩或更多層之多層佈線。 依據本發明，提供一種半導體裝置，包含： 一像素區； 一周邊電路區，其係置於一圍繞像素區之區域的至少 〜部分； TFT’s之閘極電極，其係形成於周邊電路區中；及 (5) (5)200423395 短距離佈線’其係形成於閘極電極上方或下方之一 層中且連接至閘極電極， 其中不同TFTs中之閘極電極係彼此隔離。 此外’於依據本發明之半導體裝置中，短距離佈線可 爲一像素中之佈線引線或者一用以導引一功能區塊之佈 線c 此外’於依據本發明之半導體裝置中，短距離佈線最 好是或更長且短於2cm。 此外’於依據本發明之半導體裝置中，短距離佈線可 爲一具有兩或更多層之多層佈線。 此外’依據本發明之半導體裝置可進一步包含一長距 離佈線，其係形成於短距離佈線上方之一層中。 依據本發明，提供一種半導體裝置，包含： 一像素區； 一周邊電路區，其係置於一圍繞像素區之區域的至少 一部分； T F T ’ s之閘極電極，其係形成於周邊電路區中；及 一長距離佈線，其係形成於閘極電極上方或下方之一 層中， 其中不同TFTs中之閘極電極係彼此隔離。 此外，於依據本發明之半導體裝置中，長距離佈線可 爲較像素節距更長百倍或更多倍。 此外，於依據本發明之半導體裝置中，長距離佈線最 好是2 cm或更長且短於10 cm。 „ 9 - (6) (6)200423395 此外，於依據本發明之半導體裝置中，長距離佈線可 爲一具有兩或更多層之多層佈線。 此外，於依據本發明之半導體裝置中，最好是其多層 佈線之至少一層被形成自一低電阻材料。 此外，於依據本發明之半導體裝置中，低電阻材料可 爲選自包括銅、銅合金、金、金合金、銀、及銀合金的族 群之一或更多材料。 此外，於依據本發明之半導體裝置中，一電晶體可被 形成於周邊電路區中，而一具有兩或更多層之多層佈線可 被形成於電晶體之上。 依據本發明，提供一種製造半導體裝置之方法，包 含： 形成一驅動器電路TFT於一基底上之一驅動器電路 區中及一像素TFT於基底上之一像素區中；及 形成一第一佈線於驅動器電路TFT上、一第二佈線 於第一佈線上、及一第三佈線於第二佈線上，並形成一第 一電容元件於像素TFT之一汲極區上及一第二電容元件 於第一電容元件上。 依據以上製造半導體裝置之方法’第一至第二佈線被 形成於驅動器電路TFT之上且第一及第二電容元件被形 成於像素TFT之汲極區上。因此，像素區可具有增進的 孔徑比。 依據本發明，提供一種半導體裝置，包含： 一驅動器電路TFT，其係形成於一基底上之一驅動器 •10- (7) (7)200423395 電路中； 一像素TFT ’其係形成於基底上之一像素區中； 一第一佈線’其係形成於驅動器電路TFT之上； 第一佈線’其係形成於第一佈線之上； 一第二佈線’其係形成於第二佈線之上； 一第一電容元件，其係形成於像素TFT之一汲極區 上；及 一第二電容元件，其係形成於第一電容元件上。 依據本發明，提供一種製造半導體裝置之方法，包 含： 形成一驅動器電路TFT於一基底上之一驅動器電路 區中及一像素TFT於基底上之一像素區中； 形成一第一層間絕緣膜於驅動器電路TFT及像素 TFT 上； 形成一第一接觸孔於其位於像素區中之第一層間絕緣 膜的一部分中，該第一接觸孔被置於像素TFT之一汲極 區上； 從一第一導電膜形成一第一佈線於其位於驅動器電路 區中之第一層間絕緣膜的一部分上，並從第一導電膜形成 一汲極電極於第一接觸孔中； 形成一第二層間絕緣膜於第一佈線、汲極電極、及第 一層間絕緣膜上； 形成一第二接觸孔於其位於像素區中之第二層間絕緣 膜的一部分中，該第二接觸孔被置於第一接觸孔及汲極電 -11 - 200423395200423395 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more specifically relates to a method for reducing a pixel area having one or more pixels Technology of the area of the peripheral circuit area. The present invention also relates to a technique for improving the aperture ratio of the pixel region by providing a smaller width of the peripheral circuit region ("boundary box") through a multilayer wiring. [Prior Art] FIG. 6 is a plan view, which schematically shows a wafer in a conventional liquid crystal display device. The wafer in the liquid crystal display device has a pixel region 101, which has a square shape on a plane. The pixel area 101 includes one or more pixels. Peripheral circuits 10 2 a to 10 2 c are arranged around the pixel area 101. The wafer is disposed on a substrate (or the wafer and similar wafers are disposed on the same substrate). The peripheral circuits 102a to 102c each have a thin rectangular shape on a plane, and the short side length of each rectangle is 2 to 3 mm. The reason why each peripheral circuit requires a width of 2 to 3 mm is because the width of the power supply lines, clock lines, and other wirings formed in the peripheral circuits is in the order of tens to hundreds of V m, thus occupying a large area . The peripheral circuits 102a to 102c have TFTs (thin film transistors). Those TFTs have a gate electrode formed from a refractory metal such as polysilicon or w. The gate electrode is used to supply a gate voltage to a specific TFT active layer, and the gate electrodes of most TFTs are electrically connected to each other. Gate (2) 200423395 The electrode is electrically connected to the cross wiring. The wiring is a layer that electrically connects most of the TFTs to each other and is placed above the gate electrode. The wiring also connects the TFTs to the pixel electrodes. The wiring has a stacked structure including, for example, an A1 and a barrier metal film. The barrier metal film is a single-layer or multi-layer structure of Ti, TiN, Ta, TaN, and the like. A black mask is formed in the layer above the wiring layer, which is the A1 temple. The black mask has the ability of light shielding and potential blocking. One pixel is formed from I TO in the layer above the black mask. [Reference 1: JP 09-43 63 0 A] As described above, the peripheral circuit area (peripheral circuits constituting a “side frame” around the pixel area) has a width of 2 to 3 mm. The peripheral circuit area is expected to have a narrower width because the decrease in the width of the peripheral circuit area (boundary box) results in an increase in the aperture ratio of the pixel area. For implementation, the reduction in the width of the peripheral circuit provides a larger area of the pixel area (when the chip size is equal and the area of each pixel increases), thereby increasing the area of the holes in each pixel and increasing the brightness. On the other hand, when the pixel regions have the same face, the reduction in the width of the peripheral circuit region allows it to reduce the wafer size and crystals to become more suitable for mass production. In the conventional liquid crystal display device described above, the wiring layer is a single layer and it is difficult to increase the degree of integration in the wiring layer due to the photolithography system and the like. When the wiring is formed in the same layer, the wiring occupies a large area and the ratio of the area of the actuator circuit and other peripheral circuits to the entire wafer area is large, which leads to an obstacle that the width of the peripheral circuit area decreases. Connected to the film ’s electrical world ’s Hidden area and the rising limit drive factor of the film is -6- (3) (3) 200423395 When the peripheral circuit area has a large width, the wiring that electrically connects most pixels to each other also tends to have extended Length because the wiring runs across the pixel area. This may result in higher wiring resistance than desired, and a shortage of current supplied to the TFTs. In addition, the gate electrode formed in the layer under the wiring is often made thicker to reduce the resistance of the gate electrode. The thicker gate electrode increases the level difference in the base of the wiring layer to help reduce the patterning margin when wiring is formed. This may cause level interruption in the patterned wiring. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique for reducing the area of a peripheral circuit area relative to a pixel area. In particular, one object of the present invention is to improve the aperture ratio of the pixel region by providing a smaller width of the peripheral circuit region ("boundary box") through a multilayer wiring. In order to solve the above problems, according to the present invention, a semiconductor device is provided, including: a pixel region; a peripheral circuit region that is disposed on at least a portion of a region surrounding the pixel region; and a wiring that is formed from the peripheral circuit region One of the low resistance materials. According to the above semiconductor device, the wiring in the peripheral circuit region is formed from a low-resistance material ', thereby giving the wiring a smaller width. Therefore, the area of the peripheral circuit area with respect to the area of the pixel area can be reduced. (4) (4) 200423395 According to the present invention, there is provided a semiconductor device including a pixel region; a peripheral circuit region which is disposed at least in a portion of a region surrounding the pixel region; and a wiring which is formed In the peripheral circuit area, the wiring is a multilayer wiring having two or more layers. According to the semiconductor device described above, the wiring system formed in the peripheral circuit area is a multilayer wiring and thus the peripheral circuit area (boundary box) is given a smaller width. In this way, the pixel area can have an improved aperture ratio. According to the present invention, there is provided a semiconductor device including: a pixel region; a peripheral circuit region, which is disposed on at least a portion of a region surrounding the pixel region; a gate electrode of TF T's, which is formed on the peripheral circuit region And a wiring formed in a layer above or below the gate electrode and connected to the gate electrode, wherein the gate electrodes in different TFTs are isolated from each other. Further, in the semiconductor device according to the present invention, the wiring is preferably a multilayer wiring having two or more layers. According to the present invention, there is provided a semiconductor device including: a pixel region; a peripheral circuit region, which is disposed at least to a portion of a region surrounding the pixel region; a gate electrode of TFT's, which is formed in the peripheral circuit region; And (5) (5) 200423395 short-distance wiring is formed in a layer above or below the gate electrode and connected to the gate electrode, where the gate electrodes in different TFTs are isolated from each other. In addition, in the semiconductor device according to the present invention, the short-distance wiring can be a wiring lead in a pixel or a wiring to guide a functional block. C 'Furthermore, in the semiconductor device according to the present invention, the short-distance wiring is the most It is better or longer and shorter than 2cm. Further, in the semiconductor device according to the present invention, the short-distance wiring may be a multilayer wiring having two or more layers. In addition, the semiconductor device according to the present invention may further include a long-distance wiring formed in a layer above the short-distance wiring. According to the present invention, there is provided a semiconductor device including: a pixel region; a peripheral circuit region, which is disposed on at least a portion of a region surrounding the pixel region; a gate electrode of TFT's, which is formed in the peripheral circuit region And a long-distance wiring formed in a layer above or below the gate electrode, wherein the gate electrodes in different TFTs are isolated from each other. In addition, in the semiconductor device according to the present invention, the long-distance wiring may be a hundred times or more longer than the pixel pitch. Further, in the semiconductor device according to the present invention, the long-distance wiring is preferably 2 cm or longer and shorter than 10 cm. „9-(6) (6) 200423395 In addition, in the semiconductor device according to the present invention, the long-distance wiring may be a multilayer wiring having two or more layers. In addition, in the semiconductor device according to the present invention, it is preferable It is that at least one layer of the multilayer wiring is formed from a low-resistance material. In addition, in the semiconductor device according to the present invention, the low-resistance material may be selected from the group consisting of copper, copper alloy, gold, gold alloy, silver, and silver alloy. One or more materials of the group. In addition, in the semiconductor device according to the present invention, a transistor may be formed in a peripheral circuit region, and a multilayer wiring having two or more layers may be formed on the transistor. According to the present invention, a method for manufacturing a semiconductor device is provided, including: forming a driver circuit TFT in a driver circuit region on a substrate and a pixel TFT in a pixel region on the substrate; and forming a first wiring on A driver circuit TFT, a second wiring on the first wiring, and a third wiring on the second wiring, and a first capacitor element is formed on a drain region of the pixel TFT A second capacitor element is on the first capacitor element. According to the above method for manufacturing a semiconductor device, the first to second wirings are formed on the driver circuit TFT and the first and second capacitor elements are formed on the drain of the pixel TFT. Therefore, a pixel region may have an improved aperture ratio. According to the present invention, a semiconductor device is provided, including: a driver circuit TFT, which is a driver formed on a substrate • 10- (7) (7) 200423395 In the circuit; a pixel TFT is formed in a pixel region on a substrate; a first wiring is formed over a driver circuit TFT; a first wiring is formed over a first wiring; a first Two wirings are formed on the second wiring; a first capacitive element is formed on one of the drain regions of the pixel TFT; and a second capacitive element is formed on the first capacitive element. The present invention provides a method for manufacturing a semiconductor device, including: forming a driver circuit TFT in a driver circuit region on a substrate and a pixel TFT in a pixel region on the substrate; Forming a first interlayer insulating film on the driver circuit TFT and the pixel TFT; forming a first contact hole in a part of the first interlayer insulating film located in the pixel region, the first contact hole being placed in the pixel TFT On a drain region; forming a first wiring from a first conductive film on a portion of a first interlayer insulating film located in a driver circuit region; and forming a drain electrode from the first conductive film on a first contact Forming a second interlayer insulating film on the first wiring, the drain electrode, and the first interlayer insulating film; forming a second contact hole in a part of the second interlayer insulating film located in the pixel region, The second contact hole is placed between the first contact hole and the drain electrode-11-200423395
極上； 形成一第三層間絕緣膜於第二層間絕緣膜上且於第二 接觸孔中； 從一第二導電膜形成一第二佈線於其位於驅動器電路 區中之第三層間絕緣膜的一部分上，並從第二導電膜形成 一第一電容電極於第二接觸孔中； 藉由蝕刻第一電容電極以部分地暴露第三層間絕緣膜 於第二接觸孔之底部上； 形成一第四層間絕緣膜於第二佈線、第一電容電極、 及第三層間絕緣膜上； 形成一第三接觸孔於其位於像素區中之第四層間絕緣 膜的一部分中，該第三接觸孔被置於第二接觸孔及第一電 容電極上； 形成一第五層間絕緣膜於第四層間絕緣膜上且於第三 接觸孔中， 藉由蝕刻其位於第三接觸孔之底部上的第三及第五層 間絕緣膜的部分以部分地暴露其置於第三接觸孔之底部下 方的汲極電極；及 從一第三導電膜形成一第三佈線於其位於驅動器電路 區中之第五層間絕緣膜的一部分上，以及從第三導電膜形 成一第二電容電極於第三接觸孔中且將第二電容電極電連 接至汲極電極； 其中一第一電容元件及一第二電容元件被形成於第一 至第三接觸孔中，該第一電容元件包括汲極電極、當作介 -12- (9) (9)200423395 電質之桌二層間絕緣膜、及第一電容電極；該第二電容兀 件包括第一電容電極、當作介電質之第五層間絕緣膜 '及 弟—電谷電極。 此外’於依據本發明之製造半導體裝置的方法中，將 第二電容電極電連接至汲極電極可被接續以形成一第六層 間絕緣膜於第三佈線、第二電容電極、及第五層間絕緣膜 上·’並於其位於像素區中之第五層間絕緣膜的一部分上形 成一電連接至第二電容電極的像素電極。 依據本發明，提供一種半導體裝置，包含： 一驅動器電路TFT，其係形成於一基底上之一驅動器 電路區中、及一像素TFT，其係形成於基底上之一像素區 中； 一第一層間絕緣膜’其係形成於驅動器電路TFT及 像素TFT上； 一第一接觸孔，其係形成於一位於像素區中之第一層 間絕緣膜的部分中，該第一接觸孔被置於像素TFT之一 汲極區上；. 一第一佈線’其係從一第一導電膜被形成於一位於驅 動器電路區中之第一層間絕緣膜的部分上； 一汲極電極’其係從第一導電膜被形成於第一接觸孔 中； 一第一層間絕緣膜，其係形成於第一佈線、汲極電 極、及第一層間絕緣膜上； 一第一接觸孔’其係形成於一位於像素區中之第二層 -13- (10) (10)200423395 間絕緣膜的部分中’該第二接觸孔被置於第一接觸孔及汲 極電極上； 一第三層間絕緣膜，其係形成於第二層間絕緣膜上且 於第二接觸孔中； 一第二佈線，其係從一第二導電膜被形成於一位於驅 動器電路區中之第三層間絕緣膜的部分上； 一第一電容電極，其係從第二導電膜被形成於第二接 觸孔中； 一孔，用以部分地暴露第三層間絕緣膜於第二接觸孔 之底部上，該孔係形成於第一電容電極中； 一第四層間絕緣膜，其係形成於第二佈線、第一電容 電極、及第三層間絕緣膜上； 一第三接觸孔，其係形成於一位於像素區中之第四層 間絕緣膜的部分中，該第三接觸孔被置於第二接觸孔及第 一電容電極上； 一第五層間絕緣膜，其係形成於第四層間絕緣膜上且 於第三接觸孔中； 一孔，用以部分地暴露其置於第三接觸孔之底部下方 的汲極電極，該孔係形成於第三接觸孔之底部上的第三及 第五層間絕緣膜的部分中；及 一第三佈線，其係從一第三導電膜被形成於一位於驅 動器電路區中之第五層間絕緣膜的部分上； 一第二電容電極，其係從電連接至汲極電極之第三導 電膜被形成於第三接觸孔中， -14· (11) (11)200423395 其中一第一電容元件及一第二電容元件被形成於第一 至第二接觸孔中，該第一電容元件包括汲極電極、當作介 電質之第三層間絕緣膜、及第一電容電極；該第二電容元 件包括第一電容電極、當作介電質之第五層間絕緣膜、及 第二電容電極。 此外，依據本發明之半導體裝置可進一步包含：一第 六層間絕緣膜，其係形成於第三佈線、第二電容電極、及 第五層間絕緣膜上；及一像素電極，其係形成於一位於像 素區中且被電連接至第二電容電極之第五層間絕緣膜的部 分上。 【實施方式】 本發明之實施例模式及實施例係參考後附圖形而被描 述於下。Forming a third interlayer insulating film on the second interlayer insulating film and in the second contact hole; forming a second wiring from a second conductive film on a portion of the third interlayer insulating film located in the driver circuit area Forming a first capacitor electrode in the second contact hole from the second conductive film; etching the first capacitor electrode to partially expose the third interlayer insulating film on the bottom of the second contact hole; forming a fourth An interlayer insulating film is formed on the second wiring, the first capacitor electrode, and the third interlayer insulating film; a third contact hole is formed in a part of the fourth interlayer insulating film located in the pixel region, and the third contact hole is disposed On the second contact hole and the first capacitor electrode; forming a fifth interlayer insulating film on the fourth interlayer insulating film and in the third contact hole, by etching the third and third electrodes located on the bottom of the third contact hole; A portion of the fifth interlayer insulating film to partially expose its drain electrode placed below the bottom of the third contact hole; and forming a third wiring from a third conductive film on its fifth layer in the driver circuit area A second capacitor electrode is formed on a part of the interlayer insulating film, and a second capacitor electrode is formed in the third contact hole from the third conductive film, and the second capacitor electrode is electrically connected to the drain electrode; one of the first capacitor element and one second capacitor element Is formed in the first to third contact holes, the first capacitor element includes a drain electrode, a dielectric interlayer insulating film of the table -12- (9) (9) 200423395, and a first capacitor electrode; The second capacitor element includes a first capacitor electrode, a fifth interlayer insulating film 'serving as a dielectric, and a valley-electrode. In addition, in the method of manufacturing a semiconductor device according to the present invention, electrically connecting the second capacitor electrode to the drain electrode may be connected to form a sixth interlayer insulating film between the third wiring, the second capacitor electrode, and the fifth layer. On the insulating film, a pixel electrode electrically connected to the second capacitor electrode is formed on a part of the fifth interlayer insulating film located in the pixel region. According to the present invention, there is provided a semiconductor device including: a driver circuit TFT formed in a driver circuit region on a substrate, and a pixel TFT formed in a pixel region on the substrate; a first The interlayer insulating film is formed on the driver circuit TFT and the pixel TFT; a first contact hole is formed in a portion of the first interlayer insulating film in the pixel region, and the first contact hole is disposed On a drain region of a pixel TFT; a first wiring is formed from a first conductive film on a portion of a first interlayer insulating film in a driver circuit region; a drain electrode is A first conductive film is formed in the first contact hole; a first interlayer insulating film is formed on the first wiring, the drain electrode, and the first interlayer insulating film; a first contact hole ' It is formed in a part of a second layer of 13- (10) (10) 200423395 insulating film located in a pixel area. 'The second contact hole is placed on the first contact hole and the drain electrode. Three interlayer insulating film formed on the second interlayer insulating film And in the second contact hole; a second wiring formed from a second conductive film on a portion of a third interlayer insulating film located in a driver circuit area; a first capacitor electrode formed from A second conductive film is formed in the second contact hole; a hole for partially exposing the third interlayer insulating film on the bottom of the second contact hole, the hole is formed in the first capacitor electrode; a fourth interlayer An insulating film is formed on the second wiring, the first capacitor electrode, and the third interlayer insulating film; a third contact hole is formed in a portion of the fourth interlayer insulating film located in the pixel region, the The third contact hole is placed on the second contact hole and the first capacitor electrode; a fifth interlayer insulating film is formed on the fourth interlayer insulating film and is in the third contact hole; a hole for partially The drain electrode, which is placed below the bottom of the third contact hole, is formed in the portions of the third and fifth interlayer insulating films on the bottom of the third contact hole; and a third wiring is formed from A third conductive film is formed on a On the part of the fifth interlayer insulating film in the actuator circuit area; a second capacitor electrode formed in the third contact hole from the third conductive film electrically connected to the drain electrode, -14 · (11) (11) 200423395 A first capacitor element and a second capacitor element are formed in the first to second contact holes. The first capacitor element includes a drain electrode, a third interlayer insulating film serving as a dielectric, And a first capacitor electrode; the second capacitor element includes a first capacitor electrode, a fifth interlayer insulating film serving as a dielectric, and a second capacitor electrode. In addition, the semiconductor device according to the present invention may further include: a sixth interlayer insulating film formed on the third wiring, the second capacitor electrode, and the fifth interlayer insulating film; and a pixel electrode formed on a A portion located in the pixel region and electrically connected to the fifth interlayer insulating film of the second capacitor electrode. [Embodiment] The mode and embodiment of the present invention will be described below with reference to the drawings.
實施例模式I 圖1係一平面圖，其槪略地顯示依據本發明之實施例 模式1之液晶顯示裝置中的晶片。 液晶顯示裝置中之此晶片具有一像素區丨，其具有平 面圖上之實質上方形的形狀。像素區1包括一或更多像 素。於像素區1之周邊（上、左、及右）設有周邊電路 2a至2c。此等晶片被配置於一基底上。周邊電路2a至2c 各具有平面圖上之一實質上薄的矩形形狀，且各矩形之較 短邊長度爲1至1.5 mm。周邊電路2a至2c因而具有較 -15- (12) 200423395 習知液晶顯示裝置更小的寬度。 爲了賦予周邊電路較小的寬度並減少相對於像素區 積之周邊電路區（邊界框）面積以利增進孔徑比，則可 用下述方法。 第一方法係減少一佈線之線寬度，藉由形成佈線自 具有較習知佈線材料更低電阻的佈線材料（例如，A1 含有A1之合金的單一層或多層）。以一形成自低電阻 料之佈線’則可抑制佈線電阻之增加，當佈線之線寬度 減少時。低電阻材料之範例包含：銅、銅合金、金、金 金、銀、及銀合金。 第二方法係一種多層佈線，以用提供一佈線兩或更 層。於此情況下，可使用一種A1爲基礎的佈線材料。 爲基礎的佈線材料之範例包含A1及A1合金。在一具有 或更多層之多層佈線中，至少一層可被形成自一低電阻 線材料。一具有兩或更多層之多層佈線可被置於一電晶 之上。 周邊電路中之佈線的面積可藉由上述第一或第二方 而被減少。如此使其得以增加像素尺寸而不改變液晶面 之晶片尺寸且因而增進亮度。另一方面，當像素區之面 保持相同時，晶片尺寸可被減少而形成於一基底上之晶 數目增加，且晶片變得適於大量生產。 於習知技術中，其形成於周邊電路中之電源供應線 時脈線、及其他佈線係二維地配置於單一層中，以致其 線變得較長且佈線之突出區域因而變得較大。反之，此 面 利 或 材 被 合 多 A1 兩 佈 體 法 板 積 片 佈 實 -16- (13) (13)200423395 施例模式係使用具有兩或更多層之多層佈線，以致其佈線 可被置於一驅動器電路上且佈線之突出區域可被因而減 少。此外，此實施例模式利用一低電阻材料於佈線中以使 佈線之寬度更窄。 習知技術係使用一具有大的線寬度之單一佈線於各電 源供應線、時脈線、等等，且此亦使得佈線之突出區域變 大。因此，於此實施例模式中，電源供應線、時脈線、或 其他佈線被形成自一具有小的線寬度之佈線組合，且窄的 佈線被三維地配置於一多層佈線。佈線之突出區域因而被 減少。此外’藉由使用低電阻材料於佈線，則佈線之寬度 可變得更窄。 習知技術具有一種佈線結構，其中大量佈線被彼此平 行地配置，且此佈線結構使得佈線之突出區域變大。因 此’於此實施例模式中’每層之佈線數目可藉由多層佈線 而被減少且因而佈線之突出區域可被減少。此外，藉由使 用低電阻材料於佈線，則佈線之寬度可變得更窄。 如圖1中所示，周邊電路2a至2c之寬度係藉由上述 方法而被減至習知技術之寬度的一半。例如，假如習知技 術中之周邊電路寬度爲2 mm，則此實施例模式中之寬度 可被減至1 mm。於是，得以達成每像素之約2 μπι的增 加，且假如習知技術中之像素節距爲1 8 μιη，則此實施例 模式中之節距可被升高至20μΠι。 實施例模式2 -17- (14) (14)200423395 接下來描述依據本發明之實施例模式2的液晶顯示裝 置。 於此實施例模式中，TFTs之閘極電極被彼此隔離地 形成。換言之，TFT中之一閘極電極及另一 TFT中之一 閘極電極被分別地形成。這表示，取代導引一位於與一閘 極電極相同層中且被連接至閘極電極之佈線，一形成於閘 極電極之上或下層中的佈線被連接至閘極電極及引線。此 免除了降低閘極電極之電阻的需求且使其得以減薄閘極電 極。下層佈線之一範例係一插入於一基底與一 S i活性層 之間的佈線。可利用於閘極電極之材料爲N+多晶矽及耐 火金屬，如同習知技術中所使用者。藉由因而減薄了閘極 電極，則由閘極電極之厚度所造成的位準差異可被減少。 如此使其易於撫平閘極電極上之一絕緣膜並協助閘極電極 上之一層中的佈線形成。 實施例模式3 .接下來描述依據本發明之實施例模式2的液晶顯示裝 置。 於此實施例模式中，一閘極電極僅被賦予一閘極電極 之功能且被形成爲不具有佈線之功能，藉由將一 TFT中 之閘極電極隔離自另一 TFT中之閘極電極。一佈線被形 成於一閘極電極之上或下層中且被電連接至閘極電極以賦 予佈線有習知技術中之閘極電極的佈線功能以及短距離佈 線的功能，習知技術的佈線之一係具有一短的佈線長度。 -18* (15) (15)200423395 類似於實施例模式2，下層佈線之一範例係一插入於一基 底與一 S i活性層之間的佈線。 如上所述，藉由去除習知技術之閘極電極的佈線功能 並將此功能賦予給閘極電極上之一層中的佈線，則此實施 例模式使其得以於閘極電極上之層中的佈線使用一種無法 抵抗熱啓動的材料，不同於習知技術中閘極電極需被形成 自一種能抵抗熱啓動之材料。因此，佈線材料之選擇範圍 變寬了。例如’鋁、含鋁合金、銅、含銅合金、金、含金 合金、銀、或含銀合金均可被選取爲佈線材料。 短距離佈線（於，例如，一液晶顯示裝置中）爲一種 佈線’其係等於或長於一被導出於一像素之佈線且等於或 短於一用以導引一功能區塊之佈線。通常，短距離佈線之 長度係2 // m或更長並短於2 cm。短距離佈線之範例包含 用以彼此電連接數至數十TFTs之佈線、用以將那些TFT s 電連接至佈線之佈線、用以彼此電連接佈線（其係電連接 至T F T s )之佈線、導出於一驅動器電路之功能區塊中的 佈線、及用以電連接活性層至源極電極或至汲極電極之導 電膜。 短距離佈線之另一範例係一種佈線，其僅用於導引一 閘極電極、一源極區、及一汲極區之佈線於一相當窄的範 圍內。“相當窄的範圍”是指一功能區塊之內部（通常爲： 一偏移暫存器電路、一位準偏移器電路、一緩衝器電路、 或者一取樣電路之內部）。短距離佈線之電阻無須被降 低’當用以導引此等佈線時，且如此容許短距離佈線變 -19- (16) 200423395 薄。藉由利用減薄的短距離佈線，則介於相同 離佈線間之寄生電容可被減少，而因此可抑制 增加，當佈線整合之程度被提升時。因而去除 之佈線整合的障礙。 最好是，短距離佈線被疊層於多層佈線。 線型態之突出區域，短距離佈線之一多層佈線 合之程度超過其由光微影術系統等所加諸的限 佈線所佔據之面積被明顯地減少。此外，多層 線程度變短，且因而得以抑制不同層中的短距 寄生電容的增加。 假如短距離佈線具有一堆疊結構（其包括 一障蔽金屬層）、或者單獨具有一障蔽金屬層 佈線可被減薄。以此實施例模式之佈線結構， 之導出佈線可利用一種材料，其具有於某些情 材料更低電阻的材料。 最好是設置一長距離佈線於短距離上方之 距離佈線係一獨立的佈線，其需具有長的佈線 疊層以供多層佈線佈線。例如，於一液晶顯示 長距離佈線具有較像素節距更長！ 00倍或更多 常’穿越（或下）整個像素區之閘極電極、閘 極佈線、及汲極佈線爲長距離佈線。明確地， 係等於或長於2 cm且等於或短於1 0 cm。長 範例包含用以彼此電連接數百至數千TFTs之 將那些TFTs電連接至佈線之佈線、用以彼此 層中的短距 寄生電容之 了較高程度 考慮到一佈 推使佈線整 制，而因此 佈線使得佈 離佈線間之 一 A1層及 ，則短距離 則閘極電極 況下較習知 一層中。長 距離且其被 裝置中，一 的長度。通 極佈線、源 長距離佈線 距離佈線之 佈線、用以 電連接佈線 -20- (17) (17)200423395 (其係電連接至T F T s )之佈線、及連接至閘極電極和源 極區且導出於像素區中之佈線。 長距離佈線最好是佔據相鄰佈線間之一大空間，以避 免佈線間之寄生電容的增加。諸如銅之低電阻材料最好是 被使用於長距離佈線之材料。 藉由設置一多層長距離佈線於一短距離佈線上，則佈 線所佔據之區域可考量突出區域而被減少。 實施例 圖2至5顯示一種製造依據本發明之實施例的液晶顯 示裝置之方法。 首先，如圖2中之一驅動器電路區及一像素區的橫斷 面圖所示，一石英基底Π被提供爲一基底，而一具有 2 0 n m厚度之氧化矽膜1 2被形成於其上。接下來，一非晶 矽膜被形成於氧化矽膜1 2之上。 注意，於此實施例中，使用一非晶矽膜；然而，亦可 替代地使用其他的半導體膜。例如，可使用微晶矽膜或非 晶矽鍺膜。此外’該膜被形成以具有從25 nm至40 nm之 厚度以考量後續的熱氧化。 接者’非晶砂膜被結晶化。於此實施例中，日本未審 查專利公告編號9-3 1 2260中所述之一種技術被應用爲— 種結晶化方法。於該專利公告案中，一非晶矽膜被結晶化 以固體相磊晶，其係使用一種選自下列元素之一元素以當 作觸媒元素：鎳（Ni )、鈷（Co )、鈀（Pd )、鍺 -21 - (18) (18)200423395 (Ge )、鉑（Pt)、鐵（Fe)、及銅（Cn ) c 方々此貫施例中’ Ni被選擇爲一觸媒元素。一含有Ni (未顯示）之層被形成於一非晶矽膜上，並於5 5 〇艺執行 熱處理4小時以利結晶化。因此，一結晶矽（多晶矽）膜 被形成於氧化矽膜1 2之上。 接下來，在吸氣於結晶矽膜中之後，藉由圖案化以形 成一結晶半導體膜1 3 ’其包括一僅包含吸氣區之活性 層。因此，獲得具有一描繪於圖2A (其顯示一頂視圖） 中之圖案的結晶半導體膜13。 之後，如圖2B中所示，一閘極絕緣膜】4被形成於結 晶半導體膜13及氧化矽膜12之上，藉由電漿CVD或濺 射。閘極絕緣膜個別作用爲一驅動器電路之像素TFT、及 N型TFT與P型TFT的閘極絕緣膜。此外，閘極絕緣膜 具有50 nm至2 00 nm之厚度。於此實施例中，一具有厚 度7 5 nm之氧化矽膜被使用。此外，其他含有矽之絕緣膜 可被使用以單層或多層之形式。 在閘極絕緣膜1 4被形成如上以後，具有厚度從5 nm 至50 nm(最好是，從10 nm至30 nm)之氧化砂（熱氧 化物）膜（未顯示）係藉由熱氧化而被形成於結晶半導體 膜1 3與閘極絕緣膜1 4之間的介面上。 之後，包括一第一導電膜之閘極電極28至30被形成 於閘極絕緣膜1 4之上。閘極電極2 8至3 0被個別地形成 於個別TFTs之上。換言之，其被分別形成於個別；s之 上。於此實施例中，此底部起依序之一矽膜（植入導電 -22- (19) (19)200423395 性）/一氮化鉅膜/一鎢膜的疊層膜（或者從底部起依序之 一矽膜/~矽化鎢膜的疊層）被使用於閘極電極。無須贅 述，可替代地使用其他的導電膜，例如，一包含選自T a · Ti· Mo，C11等之元素的膜、及包括上述元素爲主成分的金 屬合金或化合物。注意其個別閘極電極之厚度應爲 2 5 0 nm ° 此外，於本實施例中，最好是其底部上之矽膜係使用 低壓CVD而被形成。因爲CMOS電路之一閘極絕緣膜 (例如）具有薄如從5 nm至3 0 nm之膜厚度，所以一半 導體膜（一活性層）可能根據當執行濺射或電漿CVD時 之條件而受損。因此，最好是施加熱CVD，其容許藉由 氣體-相化學反應之膜形成。 接下來，具有厚度從25 nm至50 nm之SiNxOy (通 常’ X = 0.5, y = 0.1至0.8)膜被形成爲一保護膜（未顯 示）以覆蓋閘極電極2 8至3 0。此保護膜被形成以保護閘 極電極2 8至3 0免於氧化。注意，以兩次形成一膜係有效 且有利的方式以使其無針孔。 於此，亦有利的是使用含有氣體（於此實施例中爲氨 氣）之氫以執行電漿處理而成爲一種用以形成保護膜之預 處理。此預處理達成有效的氫終止，因爲由電漿所啓動 (激發）之氫被侷限於結晶半導體膜之內部。 接下來，對結晶半導體膜1 3執行一雜質摻雜程序。 源極區1 6至1 8及汲極區1 9至2 1被以此形成於結晶.半導 體膜1 3中。此步驟可被執行以任一具質量分離之離子植 •23- (20) (20)200423395 入或不具質量分離之電漿摻雜。此外，加速電壓、劑量等 之條件可由一操作者適當地設定。 接著，對結晶半導體膜1 3執行另一雜質摻雜程序。 於此步驟中，雜質被摻雜以較前述步驟更低的劑量。因 此，輕摻雜區2 2至2 4被形成於結晶半導體膜1 3中。此 步驟可被執行以任一具質量分離之離子植入或不具質量分 離之電漿摻雜。此外，加速電壓、劑量等之條件可由一操 作者適當地設定。 此步驟決定一 TFT中之源極區16至18、汲極區19 至21、LDD區22至24、及通道形成區25至27的配 置。 接下來，於一氮氣氛中執行熱處理以3 00 °C至5 5 0 °C 之溫度範圍1至1 2小時。於此實施例中，係於一氮氣氛 中執行熱處理以4 1 0 °C —小時。 注意，一依據本實施例而形成於閘極電極上之保護膜 被提供以保護閘極電極免於此熱啓動程序中之氧化。然 而，此保護膜不一定被提供緊接於閘極電極之形成後。因 此，相同效果可被達成，藉由在一第一層間絕緣膜上形成 一保護膜後之雜質元素的熱啓動，該第一層間絕緣膜被形 成於閘極電極被形成之後。 因此，在獲得圖2B中所示之狀況後，一第一層間絕 緣膜3 1被形成於保護膜之上，如圖2C中所示。於此實施 例中’由電漿CVD所形成之氧化矽膜被用於層間絕緣 膜。 - 24- (21) (21)200423395 接下來，接觸孔被形成至第.一層間絕緣膜.3 I、一保 護膜、及一閘極絕緣膜1 2，其接觸孔係個別位於源極區 及汲極區之上。接著，一第二導電膜被沈積於接觸孔中且 於第一層間絕緣膜3 1之上；之後，第二導電膜被圖案化 於接觸孔中且於第一層間絕緣膜3 1之上。因此，源極電 極32至34、及汲極電極35與36被形成。於其上，源極 電極32至34被電連接至源極區16至18，而汲極電極35 及3 6被電連接至汲極區1 9至2 1，個別地。因此，獲得 圖 C中所示之狀況。注意，驅動器電路區之源極電極32 及3 3被連接至佈線（未顯示）。驅動器電路之汲極電極 3 5被連接至佈線（未顯示）。 之後，如圖3 A中所示，一第二層間絕緣膜3 7被整 個形成於其包含源極電極及汲極電極之表面上。由電漿 CVD所形成之一氧化矽膜被使用於第二層間絕緣膜37。 接著，藉由蝕刻第二層間絕緣膜3 7，一汲極接觸孔 3 7 a被形成於第二層間絕緣膜3 7中的汲極電極3 6之上。 注意，以下可被提供爲蝕刻方法之一範例：首先，第二層 間絕緣膜3 7被塗敷以一抗蝕劑膜；之後一抗蝕劑圖案 (未顯示）係藉由暴露及顯影抗蝕劑膜而被形成於第二層 間絕緣膜之上；及第二層間絕緣膜係藉由使用抗蝕劑圖案 以當作一遮罩而被蝕刻。此係應用於下述之蝕刻程序。 之後，一第三層間絕緣膜3 8被形成於汲極接觸孔 3 7a中及第二層間絕緣膜37之上。對於第三層間絕緣膜 38，可應用一由電漿CVD所形成之氧化矽。亦可替代地 -25- (22) (22)200423395 應用藉由其他膜形成方法所形成之一包含其他材料的膜。 注意，第三層間絕緣膜38係作用爲汲極接觸孔37a中之 電容元件的介電質。 之後，如圖3 B中所示，藉由蝕刻第二及第三層間絕 緣膜3 7及3 8 ;於層間絕緣膜中，則一接觸孔被形成於驅 動器電路區中之一 TFT的汲極電極35之上。 接著，一第三導電膜被沈積於接觸孔中且於第三層間 絕緣膜38之上；之後第三導電膜被圖案化。因此，由第 三導電膜所形成之一第一佈線3 9被形成於接觸孔中且於 第三層間絕緣膜3 8之上；第一佈線3 9被電連接至閘極電 極35。同時，由第三導電膜所形成之一第一電容電極40 被形成於汲極接觸孔3 7 a中且於第三層間絕緣膜3 8之 上，於像素區中。第一電容電極40被連接至電容佈線 40a，如圖3B中之像素區的頂視圖中所示。電容佈線40a 係由第三導電膜所形成。 接下來，如圖4A中所示，藉由蝕刻第一電容電極 4 0，則汲極接觸孔3 7 a之底部的一部分被暴露。因此，一 第一電容元件被形成於汲極接觸孔3 7 a中。因此，第一電 容元件包含汲極電極3 6(其亦作用爲一電容電極）'第 三層間絕緣膜38(其亦作用爲一介電質）、及第一電容 電極4 0。 因此，第一電容元件被形成於汲極接觸孔3 7 a中。於 是’相較於現存的電容佈線（其中電容元件並未被形成於 汲極接觸孔中且佈線並非多層的），本實施例中之電容佈 -26- (23) (23)200423395 線4 0 a可被變薄且一像素區之孔徑比可被提升。 之後’如圖4 B中所示，一第四層間絕緣膜4 1被形成 於第一電容電極4 0、第一佈線3 9及第三層間絕緣膜3 8 之上。對於第四層間絕緣膜41，可應用由電漿CVD所形 成之氧化矽膜。亦可替代地應用藉由其他膜形成方法所形 成之一包含其他材料的膜。 接著，藉由蝕刻第四層間絕緣膜4 1，一接觸孔4 1 a 被形成於層間絕緣膜4 1中的汲極接觸孔3 7a及第一電容 電極40之上。 接下來，一第五層間絕緣膜42被形成於接觸孔41a 中且於第四層間絕緣膜4 1之上。對於第五層間絕緣膜 42，可應用由電漿CVD所形成之氧化矽膜。亦可替代地 應用藉由其他膜形成方法所形成之一包含其他材料的膜。 此外，第五層間絕緣膜42作用爲接觸孔4 1 a中之介電 質。 之後，如圖5 A中所示，藉由蝕刻第三及第五層間絕 緣膜3 8及42於接觸孔4 1 a之底部上，則汲極電極3 6之 一部分被暴露於接觸孔4 1 a之底部上。然後，藉由蝕刻第 四及第五層間絕緣膜4 1及42，一接觸孔被形成於層間絕 緣膜之驅動器電路區中的第一佈線3 9之上。於此實施例 中，用以暴露汲極電極3 6之一部分的蝕刻及用以形成一 接觸孔於驅動器電路中的蝕刻被分別執行於個別步驟中； 然而，兩個蝕刻亦可被執行於一蝕刻步驟。 接著，一第四導電膜被沈積於接觸孔中且於第五層間 -27- (24) (24)200423395 絕緣膜42之上，而之後第四導電膜被圖案化。因此，由 第四導電膜所形成之一第二佈線4 3被形成於接觸孔中且 於驅動器電路區中之第五層間絕緣膜4 2上，且第二佈線 4 3被電連接至桌一佈線3 9。同時，由第四導電膜所形成 之一第二電容電極44被形成於接觸孔41a中且於第五層 間絕緣膜4 2之上，於像素區中；第二電容電極4 4被電連 接至汲極電極36;及由第四導電膜所形成之一黑色遮罩 45被形成於像素區中之一像素TFT之上的第五層間絕緣 膜42之上。 因此，一第二電容元件被形成於接觸孔4 1 a中。因 此’桌一電谷兀件包含第一電容電極40、第五層間絕緣 膜42 (其亦作用爲介電質）、及第二電容電極44。 之後，如圖5 B中所示，一第六層間絕緣膜4 6被形成 於其包含第二佈線43、黑色遮罩45、及第二電容電極44 的整個表面之上。對於第六層間絕緣膜4 6，可應用一種 有機樹脂膜，諸如丙烯酸樹脂膜及聚醯亞胺膜，等等。 接著，第六層間絕緣膜46被蝕刻。於此，蝕刻係由 乾式蝕刻所執行。一接觸孔係藉此而被形成於第六層間絕 緣膜46中的第二電容電極44之上。 之後’藉由濺射以形成一導電膜於接觸孔中且於第六 層間絕緣膜46之上。然後，藉由圖案化導電膜，則由導 電膜所形成之一像素電極47被形成於像素區中的第六層 間絕緣膜之上。當製造一種傳輸液晶顯示裝置時，使用透 明或半透明膜，典型地爲氧化銦錫（ITO )被使用於導電 -28- (25) (25)200423395 膜。另一方面，當製造一種反射液晶顯示裝置時，係使用 一反射膜，通常爲包括A1或Ag之膜。像素電極47係透 過第二電容電極44而被電連接至汲極電極36。 依據上述實施例，藉由透過驅動器電路區中之多層佈 線以賦予驅動器電路區之面積一較小的寬度，則周邊電路 區之面積可被減少而不降低像素區之孔徑比。因此，像素 尺寸可被增加而不改變液晶面板之晶片尺寸，且可增進發 光性。反之，當像素尺寸未改變時，液晶顯示面板之晶片 尺寸可被變小，藉此增進生產率。 再者，除了周邊電路之寬度被減少以外，第一及第二 電容元件被形成於像素區中之像素T F T的汲極接觸孔3 7 a 中。此減少像素區中之無效空間，並增進像素區之孔徑 比。 換言之，當多層佈線被應用於驅動器電路區中時；因 此’像素區中之佈線亦需爲多層的。此外，於該情況下， 當電容元件未被形成於汲極接觸孔3 7 a中時，則無效空間 被形成於利用多層佈線在像素區中之情況下。亦即，難以 形成一接觸孔於另一接觸孔之上，以致其接觸孔被水平地 偏移並形成。結果形成一無效空間。然而，藉由形成第一 及第二電容元件於一像素TFT之汲極接觸孔37a中，則 像素區中之無效空間可被減少且像素區之孔徑比亦可被增 進。 此外，於此實施例中，閘極電極3 5、第一及第二佈 線39及43整個可爲一多層佈線，其具有如實施例模式3 -29- (26) (26)200423395 中所述之短長度佈線的短距離佈線之功能。因此，短距.離 佈線之膜厚度可被變薄。藉由使短距離佈線成爲薄膜形 式’則可減少於一層中的短距離佈線間之寄生電容，以致 其寄生電容不會增加，雖然佈線整合之程度增加。因此， 可減少阻礙高程度佈線整合之原因。 再者’於此實施例中，實施例模式3中所述之長距離 佈線可被形成於個別如第一及第二佈線3 9及4 3的相同層 上。 再者’於此實施例中，佈線被多層化以具有兩或更多 層且多層佈線被配置於TFT之上側上，以致其佈線部分 之面積可被減少。因此，像素區之面積可被擴大而不改變 液晶面板之晶片尺寸，藉此增進發光性。再者，當像素尺 寸係相反地未改變時，則液晶顯示面板之晶片尺寸可被變 小且形成於一基底之上的晶片數可被增加，藉此增進生產 率。 再者，於此實施例中，第二至第四導電膜可由實施例 模式1中所述之低電阻佈線材料來形成。因此，佈線之線 寬度可被變小。 再者，於此實施例中’因爲電容元件被形成於汲極接 觸孔37a中，所以電容佈線40a之寬度可被變小且像素區 之孔徑比可被增進。 注意到，本發明並不限定於上述實施例模式及實施 例，而可被改變於其實施中。 上述實施例中所述之液晶顯示裝置可並應用於電子器 -30- (27) (27)200423395 具之各種顯示。注意，電子器具被界定爲設有液晶顯示裝 置之產品。電子器具之範例包含：視頻相機、靜態相機、 投影機、投影電視、頭戴式顯示器、汽車導航系統、個人 笔I (包a筆δΞ型）、個人數位助理（行動電腦、行動電 話等等）。 如上所述’依據本發明，可減少周邊電路區相對於像 素區之面積。此外’像素區之孔徑比可藉由利用多層佈線 並窄化周邊電路區之寬度而被增進，藉此將電路聚集沿著 一像素之側邊。 【圖式簡單說明】 圖1顯示依據實施例模式〗之液晶顯示裝置中的晶片 之框格式。 圖2Α至2C顯示一驅動電路及一像素區之橫斷面 圖、以及一液晶顯示裝置之像素區的頂視圖，依據本發 明。 圖3Α及3Β顯示接在圖2C後之一步驟，且其顯示一 驅動電路區及一像素區之橫斷面圖、以及一液晶顯示裝置 之像素區的頂視圖。 圖4Α及4Β顯示接在圖3Β後之一步驟，且其顯示一 驅動電路區及一像素區之橫斷面圖、以及一液晶顯示裝置 之像素區的頂視圖。 圖5Α及5Β顯示接在圖4Β後之一步驟，且其顯示一 驅動電路區及一像素區之橫斷面圖、以及一液晶顯示裝置 -31 - (28) 200423395 之像素區的頂視圖。 圖6顯示一種習知液晶顯示裝置中之晶片的框格式。 【符號說明】 1 像素區 2a- 2c 周 邊 電 路 11 石英基 底 12 氧化5夕 膜 13 結晶半 導 髀 膜 14 閘極絕 緣 膜 16- 18 源 極 19- 2 1 汲 極 區 22- 24 輕 摻 雜 區 25- 27 通 道 形 成 區 28- 30 閘 極 電 極 3 1 第- -層 間 絕 緣 膜 32- 34 源 極 電 極 35, 36 汲 極 電 極 37 第二 二層 間 絕 緣 膜 37a 1汲極接 觸 孔 38 第三 三層 間 絕 緣 膜 39 第- -佈 線 40 第- -電 容 電 極 40a 1電容佈 線Embodiment Mode I FIG. 1 is a plan view which schematically shows a wafer in a liquid crystal display device according to Embodiment Mode 1 of the present invention. The wafer in a liquid crystal display device has a pixel region, which has a substantially square shape in a plan view. The pixel area 1 includes one or more pixels. Peripheral circuits 2a to 2c are provided on the periphery (top, left, and right) of the pixel area 1. These wafers are arranged on a substrate. The peripheral circuits 2a to 2c each have a substantially thin rectangular shape in a plan view, and the shorter side length of each rectangle is 1 to 1.5 mm. The peripheral circuits 2a to 2c thus have a smaller width than the conventional liquid crystal display device. In order to give the peripheral circuit a smaller width and reduce the area of the peripheral circuit area (boundary box) relative to the pixel area to improve the aperture ratio, the following method can be used. The first method is to reduce the width of a wiring by forming the wiring from a wiring material having a lower resistance than conventional wiring materials (for example, A1 contains a single layer or multiple layers of an alloy of A1). The use of a wiring formed of a low resistance material can suppress an increase in wiring resistance when the line width of the wiring decreases. Examples of low-resistance materials include copper, copper alloys, gold, gold, silver, and silver alloys. The second method is a multilayer wiring to provide two or more layers of one wiring. In this case, an A1-based wiring material may be used. Examples of based wiring materials include A1 and A1 alloys. In a multilayer wiring having one or more layers, at least one layer may be formed from a low-resistance wire material. A multilayer wiring with two or more layers can be placed on a transistor. The area of the wiring in the peripheral circuit can be reduced by the above-mentioned first or second method. This makes it possible to increase the pixel size without changing the wafer size of the liquid crystal surface and thus increase the brightness. On the other hand, when the faces of the pixel area remain the same, the wafer size can be reduced and the number of crystals formed on a substrate can be increased, and the wafer becomes suitable for mass production. In the conventional technology, the clock lines of the power supply lines and other wirings formed in the peripheral circuits are two-dimensionally arranged in a single layer, so that the lines become longer and the protruding areas of the wirings become larger. . On the other hand, this material is made of A1 two cloth body boards. -16- (13) (13) 200423395 The embodiment mode uses multi-layer wiring with two or more layers, so that its wiring can be The protruding area placed on a driver circuit and wiring can thus be reduced. In addition, this embodiment mode uses a low-resistance material in the wiring to make the width of the wiring narrower. The conventional technique uses a single wiring with a large line width to each power supply line, clock line, etc., and this also makes the protruding area of the wiring larger. Therefore, in this embodiment mode, the power supply line, clock line, or other wiring is formed from a wiring combination having a small line width, and the narrow wiring is three-dimensionally arranged on a multilayer wiring. The protruding area of the wiring is thus reduced. In addition, by using a low-resistance material for the wiring, the width of the wiring can be made narrower. The conventional technique has a wiring structure in which a large number of wirings are arranged in parallel with each other, and this wiring structure makes a protruding area of the wiring large. Therefore, the number of wirings per layer in this embodiment mode can be reduced by multi-layer wiring and thus the protruding area of the wiring can be reduced. In addition, by using a low-resistance material for the wiring, the width of the wiring can be made narrower. As shown in Fig. 1, the width of the peripheral circuits 2a to 2c is reduced to half the width of the conventional technique by the above method. For example, if the peripheral circuit width in the conventional technology is 2 mm, the width in this embodiment mode can be reduced to 1 mm. Therefore, an increase of about 2 μm per pixel can be achieved, and if the pixel pitch in the conventional technology is 18 μm, the pitch in this embodiment mode can be increased to 20 μm. Embodiment Mode 2 -17- (14) (14) 200423395 Next, a liquid crystal display device according to Embodiment Mode 2 of the present invention will be described. In this embodiment mode, the gate electrodes of the TFTs are formed separately from each other. In other words, one gate electrode in the TFT and one gate electrode in the other TFT are formed separately. This means that instead of guiding a wiring located in the same layer as a gate electrode and connected to the gate electrode, a wiring formed above or below the gate electrode is connected to the gate electrode and the lead. This eliminates the need to reduce the resistance of the gate electrode and enables it to thin the gate electrode. An example of the lower layer wiring is a wiring interposed between a substrate and a Si active layer. The materials that can be used for the gate electrode are N + polycrystalline silicon and refractory metal, as used in the conventional technology. By thus thinning the gate electrode, the level difference caused by the thickness of the gate electrode can be reduced. This makes it easy to smooth an insulating film on the gate electrode and assist in the formation of wiring in a layer on the gate electrode. Embodiment Mode 3. Next, a liquid crystal display device according to Embodiment Mode 2 of the present invention will be described. In this embodiment mode, a gate electrode is only given the function of a gate electrode and is formed to have no wiring function. By isolating the gate electrode in one TFT from the gate electrode in another TFT . A wiring is formed on or under a gate electrode and is electrically connected to the gate electrode to give the wiring the wiring function of the gate electrode in the conventional technology and the function of short-distance wiring. The wiring of the conventional technology One series has a short wiring length. -18 * (15) (15) 200423395 Similar to Embodiment Mode 2, an example of the lower-layer wiring is a wiring inserted between a substrate and a Si active layer. As described above, by removing the wiring function of the gate electrode of the conventional technology and assigning this function to the wiring in one layer on the gate electrode, this embodiment mode enables it to be used in the layer on the gate electrode. The wiring uses a material that cannot resist hot start, unlike the gate electrode in the conventional technology, which needs to be formed from a material that can resist hot start. Therefore, the selection range of wiring materials is widened. For example, 'aluminum, aluminum alloy, copper, copper alloy, gold, gold alloy, silver, or silver alloy can be selected as the wiring material. A short-distance wiring (in, for example, a liquid crystal display device) is a wiring that is equal to or longer than a wiring derived from a pixel and equal to or shorter than a wiring for guiding a functional block. Generally, the length of short-distance wiring is 2 // m or longer and shorter than 2 cm. Examples of short-distance wiring include wiring for electrically connecting several tens of TFTs to each other, wiring for electrically connecting those TFTs to wiring, wiring for electrically connecting wiring to each other (which is electrically connected to TFT s), The wiring derived in the functional block of a driver circuit and a conductive film for electrically connecting the active layer to the source electrode or to the drain electrode. Another example of short-distance wiring is a wiring that is only used to guide the wiring of a gate electrode, a source region, and a drain region within a relatively narrow range. "A fairly narrow range" refers to the inside of a functional block (usually: an offset register circuit, a quasi-offset circuit, a buffer circuit, or a sampling circuit). The resistance of the short-distance wiring does not need to be reduced 'when used to guide these wirings, and thus allows the short-distance wiring to become thin -19- (16) 200423395. By using a thinner short-distance wiring, the parasitic capacitance between the same distance wiring can be reduced, and therefore the increase can be suppressed when the degree of wiring integration is improved. This removes the barriers to wiring integration. Preferably, the short-distance wiring is laminated on the multilayer wiring. The protruding area of the line type, the multilayer wiring, which is one of the short-distance wiring, exceeds the limit occupied by the photolithography system, etc., and the area occupied by the wiring is significantly reduced. In addition, the degree of the multilayer line becomes shorter, and thus it is possible to suppress an increase in short-distance parasitic capacitance in different layers. If the short-distance wiring has a stacked structure (which includes a barrier metal layer), or the wiring has a barrier metal layer alone, the wiring can be thinned. In the wiring structure of this embodiment mode, the derived wiring can use a material that has a material with lower resistance than some materials. It is preferable to provide a long-distance wiring over a short distance. The distance wiring is an independent wiring which requires a long wiring stack for multi-layer wiring. For example, long-distance wiring on a liquid crystal display has a longer pitch than pixels! 00 times or more Often the gate electrode, gate wiring, and drain wiring across the entire pixel area are long-distance wiring. Specifically, is equal to or longer than 2 cm and equal to or shorter than 10 cm. The long example includes wiring for electrically connecting hundreds to thousands of TFTs to each other, wiring for electrically connecting those TFTs to wiring, and short-distance parasitic capacitance in each other's layers. A higher degree of consideration is given to the layout of wiring, Because of this, the wiring is located away from one of the wiring layers, A1, and the gate electrode is shorter than the conventional one in a short distance. Long distance and its length in the device. Pass-through wiring, wiring for source long-distance wiring, wiring for electrical connection -20- (17) (17) 200423395 (which is electrically connected to TFT s), and connection to gate electrode and source region And derived from the wiring in the pixel area. Long-distance wiring is best to occupy a large space between adjacent wirings to avoid the increase of parasitic capacitance between wirings. Low-resistance materials such as copper are preferably used for long-distance wiring. By providing a multilayer long-distance wiring on a short-distance wiring, the area occupied by the wiring can be reduced in consideration of the protruding area. Embodiments Figs. 2 to 5 show a method of manufacturing a liquid crystal display device according to an embodiment of the present invention. First, as shown in a cross-sectional view of a driver circuit region and a pixel region in FIG. 2, a quartz substrate Π is provided as a substrate, and a silicon oxide film 12 having a thickness of 20 nm is formed thereon. on. Next, an amorphous silicon film is formed on the silicon oxide film 12. Note that in this embodiment, an amorphous silicon film is used; however, other semiconductor films may be used instead. For example, a microcrystalline silicon film or an amorphous silicon germanium film can be used. In addition, the film is formed to have a thickness from 25 nm to 40 nm in consideration of subsequent thermal oxidation. Then, the amorphous sand film is crystallized. In this embodiment, a technique described in Japanese Unexamined Patent Publication No. 9-3 1 2260 is applied as a crystallization method. In this patent publication, an amorphous silicon film is crystallized to solid-phase epitaxially, which uses one element selected from the following elements as a catalyst element: nickel (Ni), cobalt (Co), palladium (Pd), germanium-21-(18) (18) 200423395 (Ge), platinum (Pt), iron (Fe), and copper (Cn) c In this example, 'Ni was selected as a catalyst element . A layer containing Ni (not shown) was formed on an amorphous silicon film, and a heat treatment was performed at 5500 ° C for 4 hours to facilitate crystallization. Therefore, a crystalline silicon (polycrystalline silicon) film is formed on the silicon oxide film 12. Next, after gettering in the crystalline silicon film, it is patterned to form a crystalline semiconductor film 1 3 'which includes an active layer including only a gettering region. Thus, a crystalline semiconductor film 13 having a pattern depicted in FIG. 2A (which shows a top view) is obtained. Thereafter, as shown in FIG. 2B, a gate insulating film 4 is formed on the crystalline semiconductor film 13 and the silicon oxide film 12 by plasma CVD or sputtering. The gate insulating film individually functions as a pixel TFT of a driver circuit, and a gate insulating film of an N-type TFT and a P-type TFT. In addition, the gate insulating film has a thickness of 50 nm to 200 nm. In this embodiment, a silicon oxide film having a thickness of 75 nm is used. In addition, other silicon-containing insulating films can be used in the form of single or multiple layers. After the gate insulating film 14 is formed as described above, a sand oxide (thermal oxide) film (not shown) having a thickness from 5 nm to 50 nm (preferably, from 10 nm to 30 nm) is formed by thermal oxidation. It is formed on the interface between the crystalline semiconductor film 13 and the gate insulating film 14. Thereafter, gate electrodes 28 to 30 including a first conductive film are formed on the gate insulating film 14. The gate electrodes 28 to 30 are individually formed on the individual TFTs. In other words, it is formed separately on individual; s. In this embodiment, a silicon film (implanted conductive -22- (19) (19) 200423395) / a nitrided film / a tungsten film is sequentially laminated from the bottom (or from the bottom) One of a sequence of a silicon film / ~ tungsten silicide film) is used for the gate electrode. Needless to say, other conductive films may be used instead, for example, a film containing an element selected from Ta, Ti, Mo, C11, and the like, and a metal alloy or compound containing the above elements as a main component. Note that the thickness of the individual gate electrodes should be 250 nm. In addition, in this embodiment, it is preferable that the silicon film on the bottom is formed using low-pressure CVD. Since a gate insulating film of, for example, a CMOS circuit has a film thickness as thin as 5 nm to 30 nm, a semiconductor film (an active layer) may be affected depending on conditions when performing sputtering or plasma CVD. damage. Therefore, it is preferable to apply thermal CVD, which allows film formation by a gas-phase chemical reaction. Next, a SiNxOy (usually 'X = 0.5, y = 0.1 to 0.8) film having a thickness from 25 nm to 50 nm is formed as a protective film (not shown) to cover the gate electrodes 28 to 30. This protective film is formed to protect the gate electrodes 28 to 30 from oxidation. Note that it is effective and advantageous to form a film system twice without pinholes. Here, it is also advantageous to use hydrogen containing a gas (in this embodiment, ammonia gas) to perform a plasma treatment to become a pre-treatment for forming a protective film. This pretreatment achieves effective hydrogen termination because the hydrogen initiated (excited) by the plasma is confined inside the crystalline semiconductor film. Next, an impurity doping process is performed on the crystalline semiconductor film 13. The source regions 16 to 18 and the drain regions 19 to 21 are thus formed in the crystalline semiconductor film 13. This step can be performed with any ion implantation with mass separation • 23- (20) (20) 200423395 with or without plasma separation. In addition, the conditions of the acceleration voltage, the dose, and the like can be appropriately set by an operator. Next, another impurity doping procedure is performed on the crystalline semiconductor film 13. In this step, impurities are doped at a lower dose than in the previous step. Therefore, lightly doped regions 22 to 24 are formed in the crystalline semiconductor film 13. This step can be performed with either ion implantation with mass separation or plasma doping without mass separation. In addition, the conditions of the acceleration voltage, dose, etc. can be appropriately set by an operator. This step determines the configurations of the source regions 16 to 18, the drain regions 19 to 21, the LDD regions 22 to 24, and the channel formation regions 25 to 27 in a TFT. Next, a heat treatment is performed in a nitrogen atmosphere at a temperature range of 3 00 ° C to 5 50 ° C for 1 to 12 hours. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 4 10 ° C for one hour. Note that a protective film formed on the gate electrode according to the present embodiment is provided to protect the gate electrode from oxidation in this hot start process. However, this protective film is not necessarily provided immediately after the formation of the gate electrode. Therefore, the same effect can be achieved by thermal activation of the impurity element after forming a protective film on a first interlayer insulating film, the first interlayer insulating film is formed after the gate electrode is formed. Therefore, after the condition shown in Fig. 2B is obtained, a first interlayer insulating film 31 is formed on the protective film, as shown in Fig. 2C. In this embodiment, a silicon oxide film formed by plasma CVD is used for the interlayer insulating film. -24- (21) (21) 200423395 Next, contact holes are formed to the first interlayer insulating film. 3 I, a protective film, and a gate insulating film 12 whose contact holes are individually located in the source region. And above the drain region. Next, a second conductive film is deposited in the contact hole and on the first interlayer insulating film 31; thereafter, the second conductive film is patterned in the contact hole and on the first interlayer insulating film 31. on. Therefore, the source electrodes 32 to 34 and the drain electrodes 35 and 36 are formed. On it, the source electrodes 32 to 34 are electrically connected to the source regions 16 to 18, and the drain electrodes 35 and 36 are electrically connected to the drain regions 19 to 21, individually. Therefore, the condition shown in Fig. C is obtained. Note that the source electrodes 32 and 33 of the driver circuit area are connected to wiring (not shown). The drain electrodes 35 of the driver circuit are connected to wiring (not shown). Thereafter, as shown in FIG. 3A, a second interlayer insulating film 37 is entirely formed on the surface including the source electrode and the drain electrode. A silicon oxide film formed by plasma CVD is used for the second interlayer insulating film 37. Next, by etching the second interlayer insulating film 37, a drain contact hole 37a is formed on the drain electrode 36 in the second interlayer insulating film 37. Note that the following can be provided as an example of an etching method: first, a second interlayer insulating film 37 is coated with a resist film; thereafter, a resist pattern (not shown) is formed by exposing and developing the resist An agent film is formed on the second interlayer insulating film; and the second interlayer insulating film is etched by using a resist pattern as a mask. This applies to the etching process described below. After that, a third interlayer insulating film 38 is formed in the drain contact hole 37a and over the second interlayer insulating film 37. For the third interlayer insulating film 38, a silicon oxide formed by plasma CVD can be applied. Alternatively, -25- (22) (22) 200423395 can be applied to a film containing other materials formed by one of the other film forming methods. Note that the third interlayer insulating film 38 functions as a dielectric of the capacitor element in the drain contact hole 37a. Thereafter, as shown in FIG. 3B, by etching the second and third interlayer insulating films 37 and 38; in the interlayer insulating film, a contact hole is formed in a drain electrode of one of the TFTs in the driver circuit region. On the electrode 35. Next, a third conductive film is deposited in the contact hole and above the third interlayer insulating film 38; thereafter, the third conductive film is patterned. Therefore, one first wiring 39 formed by the third conductive film is formed in the contact hole and above the third interlayer insulating film 38; the first wiring 39 is electrically connected to the gate electrode 35. At the same time, a first capacitor electrode 40 formed of a third conductive film is formed in the drain contact hole 37a and above the third interlayer insulating film 38 in the pixel region. The first capacitor electrode 40 is connected to a capacitor wiring 40a, as shown in a top view of a pixel region in FIG. 3B. The capacitor wiring 40a is formed of a third conductive film. Next, as shown in FIG. 4A, by etching the first capacitor electrode 40, a part of the bottom of the drain contact hole 37a is exposed. Therefore, a first capacitive element is formed in the drain contact hole 37a. Therefore, the first capacitor element includes a drain electrode 36 (which also functions as a capacitor electrode), a third interlayer insulating film 38 (which also functions as a dielectric), and a first capacitor electrode 40. Therefore, the first capacitance element is formed in the drain contact hole 37a. Therefore, compared to the existing capacitor wiring (where the capacitor element is not formed in the drain contact hole and the wiring is not multilayered), the capacitor wiring in this embodiment is -26- (23) (23) 200423395 line 4 0 a can be thinned and the aperture ratio of a pixel region can be improved. After that, as shown in FIG. 4B, a fourth interlayer insulating film 41 is formed on the first capacitor electrode 40, the first wiring 39, and the third interlayer insulating film 38. As the fourth interlayer insulating film 41, a silicon oxide film formed by plasma CVD can be applied. Alternatively, a film containing other materials formed by one of the other film forming methods may be used. Next, by etching the fourth interlayer insulating film 41, a contact hole 41a is formed over the drain contact hole 37a in the interlayer insulation film 41 and the first capacitor electrode 40. Next, a fifth interlayer insulating film 42 is formed in the contact hole 41a and above the fourth interlayer insulating film 41. As the fifth interlayer insulating film 42, a silicon oxide film formed by plasma CVD can be applied. Alternatively, a film containing other materials formed by one of the other film forming methods may be used. In addition, the fifth interlayer insulating film 42 functions as a dielectric in the contact hole 41a. After that, as shown in FIG. 5A, by etching the third and fifth interlayer insulating films 3 8 and 42 on the bottom of the contact hole 4 1 a, a part of the drain electrode 36 is exposed to the contact hole 4 1 a on the bottom. Then, by etching the fourth and fifth interlayer insulating films 41 and 42, a contact hole is formed over the first wiring 39 in the driver circuit region of the interlayer insulating film. In this embodiment, the etching to expose a portion of the drain electrode 36 and the etching to form a contact hole in the driver circuit are performed in separate steps; however, two etchings can also be performed in one Etching step. Next, a fourth conductive film is deposited in the contact hole and above the fifth interlayer -27- (24) (24) 200423395 insulating film 42, and then the fourth conductive film is patterned. Therefore, a second wiring 43 formed by the fourth conductive film is formed in the contact hole and on the fifth interlayer insulating film 42 in the driver circuit area, and the second wiring 43 is electrically connected to the first table Wiring 3 9. At the same time, a second capacitor electrode 44 formed of a fourth conductive film is formed in the contact hole 41a and above the fifth interlayer insulating film 42 in the pixel region; the second capacitor electrode 44 is electrically connected to The drain electrode 36; and a black mask 45 formed of a fourth conductive film are formed on a fifth interlayer insulating film 42 over a pixel TFT in the pixel region. Therefore, a second capacitance element is formed in the contact hole 41a. Therefore, the electric table element includes a first capacitor electrode 40, a fifth interlayer insulating film 42 (which also functions as a dielectric), and a second capacitor electrode 44. Thereafter, as shown in FIG. 5B, a sixth interlayer insulating film 46 is formed over the entire surface including the second wiring 43, the black mask 45, and the second capacitor electrode 44. For the sixth interlayer insulating film 46, an organic resin film such as an acrylic resin film and a polyimide film can be applied. Next, the sixth interlayer insulating film 46 is etched. Here, the etching is performed by dry etching. A contact hole is thereby formed on the second capacitor electrode 44 in the sixth interlayer insulating film 46. After that, a conductive film is formed in the contact hole and is formed on the sixth interlayer insulating film 46 by sputtering. Then, by patterning the conductive film, a pixel electrode 47 formed by the conductive film is formed on the sixth interlayer insulating film in the pixel region. When manufacturing a transmission liquid crystal display device, a transparent or translucent film is used, typically indium tin oxide (ITO) is used for the conductive -28- (25) (25) 200423395 film. On the other hand, when manufacturing a reflective liquid crystal display device, a reflective film is used, usually a film including A1 or Ag. The pixel electrode 47 is electrically connected to the drain electrode 36 through the second capacitor electrode 44. According to the above embodiment, by giving the driver circuit area a smaller width through the multilayer wiring in the driver circuit area, the area of the peripheral circuit area can be reduced without reducing the aperture ratio of the pixel area. Therefore, the pixel size can be increased without changing the wafer size of the liquid crystal panel, and the light emitting property can be improved. Conversely, when the pixel size is not changed, the wafer size of the liquid crystal display panel can be reduced, thereby improving productivity. Furthermore, in addition to the reduction in the width of the peripheral circuits, the first and second capacitive elements are formed in the drain contact holes 37a of the pixels TFT in the pixel area. This reduces the void space in the pixel area and increases the aperture ratio of the pixel area. In other words, when the multilayer wiring is applied in the driver circuit region; therefore, the wiring in the 'pixel region also needs to be multilayered. In addition, in this case, when the capacitive element is not formed in the drain contact hole 37a, an ineffective space is formed in a case where a multilayer wiring is used in the pixel region. That is, it is difficult to form a contact hole over another contact hole so that its contact hole is horizontally shifted and formed. The result is an invalid space. However, by forming the first and second capacitor elements in the drain contact hole 37a of a pixel TFT, the ineffective space in the pixel region can be reduced and the aperture ratio of the pixel region can be increased. In addition, in this embodiment, the gate electrode 35, the first and second wirings 39 and 43 may be a multilayer wiring as a whole, which has the same structure as in the embodiment mode 3 -29- (26) (26) 200423395 The short-distance wiring function described in the short-length wiring. Therefore, the film thickness of the short-distance wiring can be made thin. By making the short-distance wiring into a thin film form, the parasitic capacitance between the short-distance wirings in one layer can be reduced, so that the parasitic capacitance will not increase, although the degree of wiring integration is increased. Therefore, it is possible to reduce the causes that hinder high-level wiring integration. Furthermore, in this embodiment, the long-distance wiring described in Embodiment Mode 3 may be formed on the same layer individually as the first and second wirings 39 and 43. Further, in this embodiment, the wiring is multilayered to have two or more layers and the multilayer wiring is arranged on the upper side of the TFT so that the area of the wiring portion can be reduced. Therefore, the area of the pixel region can be enlarged without changing the wafer size of the liquid crystal panel, thereby improving the luminescence. Furthermore, when the pixel size is not changed on the contrary, the wafer size of the liquid crystal display panel can be reduced and the number of wafers formed on a substrate can be increased, thereby improving the productivity. Furthermore, in this embodiment, the second to fourth conductive films may be formed of the low-resistance wiring material described in Embodiment Mode 1. Therefore, the wiring line width can be reduced. Furthermore, in this embodiment ', since the capacitor element is formed in the drain contact hole 37a, the width of the capacitor wiring 40a can be made smaller and the aperture ratio of the pixel region can be improved. Note that the present invention is not limited to the above-mentioned embodiment modes and embodiments, but may be changed in its implementation. The liquid crystal display device described in the above embodiment can be applied to various displays of the electronic device -30- (27) (27) 200423395. Note that an electronic appliance is defined as a product provided with a liquid crystal display device. Examples of electronic appliances include: video cameras, still cameras, projectors, projection televisions, head-mounted displays, car navigation systems, personal pens I (including a pen δΞ type), personal digital assistants (mobile computers, mobile phones, etc.) . As described above 'according to the present invention, the area of the peripheral circuit area with respect to the pixel area can be reduced. In addition, the aperture ratio of the 'pixel region can be enhanced by using multilayer wiring and narrowing the width of the peripheral circuit region, thereby concentrating the circuit along the side of a pixel. [Brief Description of the Drawings] FIG. 1 shows a frame format of a chip in a liquid crystal display device according to an embodiment mode. 2A to 2C show cross-sectional views of a driving circuit and a pixel region, and a top view of a pixel region of a liquid crystal display device according to the present invention. 3A and 3B show a step subsequent to FIG. 2C, and it shows a cross-sectional view of a driving circuit area and a pixel area, and a top view of a pixel area of a liquid crystal display device. 4A and 4B show a step subsequent to FIG. 3B, and it shows a cross-sectional view of a driving circuit area and a pixel area, and a top view of a pixel area of a liquid crystal display device. 5A and 5B show a step subsequent to FIG. 4B, and it shows a cross-sectional view of a driving circuit area and a pixel area, and a top view of a pixel area of a liquid crystal display device -31-(28) 200423395. FIG. 6 shows a frame format of a wafer in a conventional liquid crystal display device. [Symbol description] 1 Pixel area 2a- 2c Peripheral circuit 11 Quartz substrate 12 Oxidation film 13 Crystalline semiconductor film 14 Gate insulation film 16-18 Source 19-2 1 Drain area 22-24 Lightly doped area 25- 27 Channel formation area 28- 30 Gate electrode 3 1 First-interlayer insulating film 32- 34 Source electrode 35, 36 Drain electrode 37 Second and second interlayer insulating film 37a 1 Drain contact hole 38 Third and third layer Insulating film 39th--wiring 40th--capacitor electrode 40a 1 capacitor wiring
-32- (29) (29)200423395 4 1 第四層間絕緣膜 4 1 a接觸孔 42 第五層間絕緣膜 43 第二佈線 44 第二電容電極 45 黑色遮罩 46 第六層間絕緣膜 47 像素電極 1 0 1像素區 1 02a-l 02c 周邊電路 -33--32- (29) (29) 200423395 4 1 Fourth interlayer insulating film 4 1 a contact hole 42 fifth interlayer insulating film 43 second wiring 44 second capacitor electrode 45 black mask 46 sixth interlayer insulating film 47 pixel electrode 1 0 1 pixel area 1 02a-l 02c Peripheral circuit -33-