JP2004193624A - Semiconductor circuit, display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit having a new electrode structure in accordance with necessity of an electrode structure which has low specific resistance and which is sufficiently proof against a heating process not less than 400°C. <P>SOLUTION: A configuration has a gate electrode of a laminated structure which is formed on a substrate, a protection film covering an upper face and sides of the gate electrode and the substrate, a gate insulating film formed by covering the protection film, and a semiconductor film formed on the gate insulating film. As a result, the gate electrode is not oxidized but can be maintained to low resistance. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a structure of a semiconductor device including a semiconductor circuit including a semiconductor element such as an insulated gate transistor. The semiconductor device of the present invention includes not only elements such as thin film transistors (TFTs) and MOS transistors but also electro-optical devices such as display devices and image sensors having a semiconductor circuit composed of these insulated gate transistors. In addition, the semiconductor device of the present invention includes an electronic device equipped with the display device and the electro-optical device.

  Active matrix liquid crystal displays, in which a pixel matrix circuit and a driving circuit are formed using thin film transistors (TFTs) formed over an insulating substrate, have attracted attention. Liquid crystal displays up to about 0.5 to 20 inches are used as display displays.

  One area of liquid crystal display development is to increase the area. However, as the area increases, the pixel matrix circuit serving as a pixel display section also increases in area, and accordingly, the source wiring and the gate wiring arranged in a matrix become longer, and the wiring resistance increases. Furthermore, since higher definition is required, it is necessary to make the wiring thinner, and the increase in wiring resistance has become more apparent. Further, a TFT is connected to the source wiring and the gate wiring for each pixel, and the number of pixels increases, so that an increase in parasitic capacitance also poses a problem. In a liquid crystal display, generally, a gate wiring and a gate electrode are integrally formed, and a delay of a gate signal has become conspicuous with an increase in the area of a panel.

  Therefore, as the resistivity of the gate electrode wiring material is lower, the gate wiring can be made thinner and longer, thereby increasing the area. Conventionally, Al, Ta, Ti, and the like have been used as a gate electrode wiring material. Among them, Al has been used frequently because it has the lowest resistivity and is an anodizable metal. However, although Al can improve heat resistance by forming an anodic oxide film, even at a process temperature of 300 ° C. to 400 ° C., whiskers and hillocks are generated, wiring is deformed, and an insulating film or an active layer is formed. Diffusion has been a major cause of TFT malfunction and degradation of TFT characteristics.

  In order to achieve a larger area and higher definition, an electrode structure having lower specific resistance and high heat resistance is required.

  At present, TFTs are required to have high mobility, and it is expected that a crystalline semiconductor film having higher mobility than an amorphous semiconductor film is used as an active layer. Conventionally, in order to obtain a crystalline semiconductor film by heat treatment, a quartz substrate having a high strain point had to be used. Since a quartz substrate is expensive, there is a demand for a lower crystallization temperature at which an inexpensive glass substrate can be used.

  Therefore, the present applicant introduces a small amount of a metal element into an amorphous semiconductor film (typically, an amorphous silicon film, an amorphous silicon film containing Ge, or the like), and then performs heat treatment. Accordingly, a technique for obtaining a crystallized semiconductor film (JP-A-6-232059, JP-A-7-321339, etc.) has been developed. As the metal element that promotes crystallization, one or a plurality of elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used. By using this technology, a crystalline semiconductor film can be manufactured by a process (a low-temperature process) at a temperature at which a glass substrate can withstand. Ge or Pb in which the diffusion in the amorphous semiconductor film is substitutional diffusion can also be used.

  However, the problem with this technique is that the metal element used for crystallization remains in the crystalline semiconductor film, which has adversely affected the device characteristics (particularly, reliability, uniformity, etc.) of the TFT. Therefore, the present applicants have further developed a technique (Japanese Patent Laid-Open No. 8-330602) for forming a wiring using an aluminum material and then gettering a metal element in the crystalline semiconductor film. This publication discloses a technique in which a catalyst element in a channel formation region is gettered to a source region and a drain region by performing heat treatment using a source region and a drain region to which phosphorus is added as a getter link sink. Has been described.

  However, in the above-mentioned publication technology, since the aluminum material having low heat resistance is used for the wiring, the heat treatment is limited to the temperature range (about 300 to 450 ° C.). In order to obtain a sufficient gettering effect, heat treatment at 400 ° C. or higher, preferably 550 ° C. or higher was required.

  As described above, the present invention provides a semiconductor device having a novel electrode structure and a method for manufacturing the same, as required, for an electrode structure having a low specific resistance and sufficiently withstanding the gettering step. .

A first configuration of the invention disclosed in this specification is as follows.
On a substrate having an insulating surface, a gate electrode having a multilayer structure,
A protective film covering the upper surface and side surfaces of the substrate and the gate electrode;
A gate insulating film formed to cover the protective film;
A semiconductor circuit comprising a semiconductor element, comprising: a source region, a drain region, and a channel formation region formed between the source region and the drain region, in contact with the gate insulating film. Semiconductor device.

  Further, in the above structure, the gate electrode having the multilayer structure includes at least one layer mainly containing one element selected from tantalum, molybdenum, titanium, chromium, and silicon.

  In the above structure, the gate electrode having the multilayer structure includes, in order from the substrate side, a first layer mainly containing tantalum containing nitrogen, a second layer mainly containing tantalum, and a second layer containing nitrogen. It has a three-layer structure composed of three layers mainly containing tantalum.

Further, a second configuration, which is a configuration of another invention disclosed in this specification, is as follows:
A gate electrode on a substrate having an insulating surface;
A protective film covering the upper surface and side surfaces of the substrate and the gate electrode;
A gate insulating film formed to cover the protective film;
In contact with the gate insulating film, a source region, a drain region, and a channel formation region formed between the source region and the drain region;
An inorganic insulator in contact with the channel formation region;
A semiconductor device comprising a semiconductor element comprising: an organic resin film in contact with the source region and the drain region.

  In the second structure, the gate electrode includes a first layer mainly containing tantalum containing nitrogen, a second layer mainly containing tantalum, and a main layer mainly containing tantalum containing nitrogen. It has a three-layer structure including a third layer.

In each of the above structures, the protection film is a silicon nitride film.
The thickness of the protective film is 10 to 100 nm.

  In each of the above structures, at least a part of the source region and the drain region is silicide.

  Each of the above structures is characterized in that the source region and the drain region are doped with an impurity imparting N-type conductivity.

  In each of the above structures, an impurity imparting an N-type conductivity and an impurity imparting a P-type conductivity are added to the source region and the drain region.

  In each of the above structures, the channel formation region contains a catalyst element that promotes crystallization of silicon, and the concentration of the catalyst element is higher in the source region and the drain region than in the channel formation region.

  In each of the above structures, the catalyst element is characterized in that it is at least one element selected from Ni, Fe, Co, Pt, Cu, Au, and Ge.

Further, a third configuration, which is a configuration of another invention disclosed in this specification, is:
Forming wiring on a substrate having an insulating surface;
Forming a protective film covering the wiring,
Forming a gate insulating film on the protective film;
Forming a crystalline semiconductor film containing a catalytic element that promotes crystallization of silicon on the gate insulating film;
Irradiating the crystalline semiconductor film with laser light,
Forming a mask made of an insulating film on a part of the crystalline semiconductor film;
A step of doping a region to be a source region or a drain region with phosphorus element,
Performing a heat treatment to getter the catalyst element;
Patterning the crystalline semiconductor film to form an active layer;
This is a method for manufacturing a semiconductor device including a semiconductor circuit including a semiconductor element having the following.

Further, a fourth configuration, which is a configuration of another invention disclosed in this specification, is:
Forming wiring on a substrate having an insulating surface;
Forming a protective film covering the wiring,
Forming a gate insulating film on the protective film;
Forming a crystalline semiconductor film containing a catalytic element that promotes crystallization of silicon on the gate insulating film;
Patterning the crystalline semiconductor film to form an active layer;
Irradiating the crystalline semiconductor film with laser light,
Forming a mask made of an insulating film on a part of the crystalline semiconductor film;
A step of doping a region to be a source region or a drain region with phosphorus element,
Performing a heat treatment to getter the catalyst element;
This is a method for manufacturing a semiconductor device including a semiconductor circuit including a semiconductor element having the following.
The step of forming wiring on a substrate having an insulating surface,
Forming a first tantalum layer containing nitrogen, a second tantalum layer, and a third tantalum layer containing nitrogen successively from the substrate side and patterning the same. This is a method for manufacturing a semiconductor device having a semiconductor circuit.

Forming the crystalline semiconductor film on the gate insulating film in the third configuration or the fourth configuration includes forming an amorphous semiconductor film in contact with the gate insulating film surface;
Holding a catalytic element that promotes crystallization of silicon in the amorphous semiconductor film;
A step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film.

Forming the crystalline semiconductor film on the gate insulating film in the third configuration or the fourth configuration includes forming an amorphous semiconductor film in contact with the gate insulating film surface;
Holding a catalytic element that promotes crystallization of silicon in the amorphous semiconductor film;
A step of crystallizing the amorphous semiconductor film by laser light irradiation to form a crystalline semiconductor film.

  By utilizing the invention disclosed in this specification, even when a gate wiring and an electrode (wiring width: 0.1 μm to 5 μm) are manufactured and then heat treatment is performed at a high temperature (400 ° C. or higher), good results can be obtained. A semiconductor device having excellent TFT characteristics can be obtained.

  In addition, the protective film disclosed in this specification can suppress diffusion of impurities from a substrate when subjected to high-temperature treatment, and can obtain favorable TFT characteristics without being affected by the impurity concentration of the substrate. it can.

  In particular, in the high-temperature treatment (400 ° C. or more) after the step of adding the impurity imparting the P-type or N-type conductivity in the invention disclosed in this specification, the impurity was activated and the addition step was damaged. An annealing effect of the crystalline semiconductor film and a gettering effect of reducing a catalytic element remaining in the crystalline semiconductor film can be obtained.

In this embodiment mode, tantalum or a material containing tantalum as a main component is used as a gate wiring and gate electrode material. Since tantalum has a work function close to that of silicon, tantalum has a small shift in the threshold value of a TFT and is one of the preferable materials.

It is known that Ta has two types of crystal structures (body-centered cubic lattice [α─Ta] and square lattice structure [β─Ta]). The resistivity of the thin film having the square lattice structure [β─Ta] is about 170 to 200 μΩcm, and the resistivity of the thin film having the body-centered cubic lattice [α─Ta] is 13 to 15 μΩcm. Generally, most of the Ta thin film has β─Ta, but it is known that α─Ta (also referred to as bcc-Ta) can be formed by adding a small amount of impurities, for example, N ₂ at the time of film formation.

In this embodiment, when a TaN film is formed and then a Ta film is continuously laminated on the TaN film, α─Ta can be obtained. In particular, α─Ta could be obtained by setting the thickness of the TaN film to 30 nm or more, preferably 40 nm or more, depending on the composition of the TaN film and laminating the Ta film.

  However, since tantalum or a material containing tantalum as a main component easily absorbs hydrogen and is easily oxidized, a change in film quality such as oxidation or occlusion of hydrogen occurs after film formation, and a problem that resistance increases occurs. .

Therefore, in the present embodiment, as a structure of the gate wiring and the gate electrode, a Ta film is continuously laminated on a TaN film (thickness of 30 nm or more, preferably 40 nm or more), and further on this Ta film. It has a three-layer structure in which a TaN film is laminated, and then is patterned and then covered with a protective film.

  By forming a three-layer structure by successively forming a film and covering the structure with a protective film in this manner, occlusion and oxidation of hydrogen are prevented.

  Table 1 shows the change in the resistance value of the tantalum multilayer film (TaN / Ta / TaN; film thickness 50 nm / 250 nm / 50 nm) before and after the heat treatment (450 ° C., 500 ° C., 550 ° C., 600 ° C.) for 2 hours. The temperature history in this experiment was as follows: the temperature was raised from 400 ° C. to 10 ° C. below the processing temperature at 9.9 ° C./min, then raised to the processing temperature at 5 ° C./min, held for 2 hours, and gradually cooled. Next, the measurement was performed.

  From Table 1, it can be seen that the resistance value and the film thickness increased because the tantalum multilayer film deteriorated (oxidized etc.) as the heating temperature increased.

  Next, Table 2 shows the resistance of the tantalum multilayer film (TaN / Ta / TaN) covered with the protective film (SiN: 25 nm thick) before and after the heat treatment for 2 hours (450 ° C., 500 ° C., 550 ° C., and 600 ° C.). Indicates a change in value. The temperature history was the same as in Table 1.

  From Table 2, it can be seen that the addition of the protective film (SiN) can suppress an increase in the resistance value and the film thickness due to the heat treatment.

  From the above, it is possible to perform a heat treatment at a high temperature (400 to 700 ° C.) by using a Ta film having high heat resistance or a film containing Ta as a main component as a wiring material and further covering with a protective film. For example, a treatment for gettering a metal element in the crystalline semiconductor film can be performed. Even if such a heat treatment is applied, the gate wiring (wiring width: 0.1 μm to 5 μm) is within the temperature range that can be endured, and is protected by the protective film. Can be maintained.

  Further, the nitrogen composition ratio in the TaN film is in the range of 5 to 60%, but is not necessarily limited to the above numerical value because it depends on the sputtering apparatus, sputtering conditions and the like. Note that it is preferable to obtain the α─Ta film using plasma using Ar (argon) or Xe (xenon).

  Further, instead of tantalum, for example, a material such as Mo, Ti, Nb, W, a Mo—Ta alloy, an Nb—Ta alloy, or a W—Ta alloy can be used. It is also possible to use a metal material containing nitrogen in these materials or a silicide which is a compound of these materials and silicon.

As the protective film in this embodiment, an inorganic insulating film, for example, a silicon nitride film, a silicon nitride oxide film, a stacked film thereof, or the like can be used. When the thickness of the protective film is in the range of 10 to 100 nm, the protective film functions as a protective film. Further, an amorphous silicon film or a crystalline silicon film can be used as the protective film.

  In addition, since the TaN film is less likely to occlude and oxidize hydrogen than the Ta film, when forming a contact hole, a TaN film is laminated as an uppermost layer so that Ta is not exposed, and a good ohmic contact is formed. Configuration was obtained.

  Further, as another structure for obtaining a good ohmic contact in connection between wirings, as shown in FIG. 11, a multilayer wiring in which a layer 1102 mainly containing titanium is stacked on a layer 1101 mainly containing tantalum as shown in FIG. Is preferably provided. The layer mainly containing titanium prevents oxidation and occlusion of hydrogen of the layer 1101 mainly containing tantalum when forming a contact hole. Further, the layer containing titanium as a main component does not become an insulator even when exposed and oxidized, and is easily removed, so that a favorable ohmic contact can be obtained. That is, the layer containing titanium as a main component protects the layer containing tantalum as a main component, and a sufficient margin can be obtained at the time of an etching step, thereby facilitating formation of a contact hole (opening portion).

  By using a Ta film having high heat resistance or a film containing Ta as a main component as a wiring material, heat treatment at a high temperature (400 to 700 ° C.) can be performed. Gettering processing or the like can be performed. Note that when high-temperature treatment is performed, the protective film suppresses diffusion of impurities from the substrate due to heating, and can maintain a gate insulating film having favorable insulating properties. Therefore, a TFT having excellent characteristics can be manufactured without being affected by the concentration of impurities contained in the substrate.

  In this manner, the semiconductor device of the present invention can have a lower specific resistance than the conventional (Ta film [β─Ta]), and is subjected to heat treatment at a high temperature (400 to 700 ° C.). In this case, it is possible to obtain good TFT characteristics without being affected by the concentration of impurities contained in the substrate.

  Examples will be described below, but it goes without saying that the present invention is not particularly limited to these examples.

  An example of a structure of a semiconductor device including a semiconductor circuit including a semiconductor element using the invention described in this specification will be described with reference to FIGS. Note that such a semiconductor device includes a peripheral driver circuit portion and a pixel matrix circuit portion on the same substrate. In this embodiment, for the sake of simplicity of illustration, a CMOS circuit 202 forming a part of a peripheral driving circuit part and a pixel TFT 203 (N-channel TFT) forming a part of a pixel matrix circuit part are formed on the same substrate. It is shown.

  2 is a diagram corresponding to the top view of FIG. 1. In FIG. 2, a portion cut along a thick line AA ′ corresponds to a cross-sectional structure of the pixel matrix circuit 201 of FIG. The portion cut at 'corresponds to the cross-sectional structure of the CMOS circuit 202 in FIG.

  On the substrate 100, the gate electrodes of all the thin film transistors (TFTs) 203 to 205 are formed by patterning in a predetermined shape. The gate electrodes 101 to 104 are provided on a base film (not shown) and have a multilayer structure. In this embodiment, an increase in resistance is prevented by adopting a structure sandwiching the Ta film (TaN [film thickness 50 nm] / Ta [film thickness 250 nm] / TaN [film thickness 50 nm]). Then, a protective film 105 made of an inorganic film is formed to cover the gate electrode and the substrate. The gate insulating films 106a and 106b are formed thereon. Further, active layers 107 to 114 made of a crystalline semiconductor film are formed thereon. Further, thin oxide films 115 to 117 are formed on the surface of the active layer by laser light irradiation in an oxidizing atmosphere.

In the case of a P-channel TFT 205 of a CMOS circuit, a P ⁺ -type high concentration impurity region (source region or drain region) 113 as an active layer, a channel forming region 110, the P ⁺ -type high concentration impurity region, Low-concentration impurity regions 114 are formed between the channel formation regions. Further, an etching stopper 118 is formed on the channel forming region. A contact hole is formed in the first interlayer insulating film 119 having a flatness to cover it, a wiring 124 is connected to the high-concentration impurity region 113, and a second interlayer insulating film 125 is further formed thereon. A wiring 128 is connected to 124, and a third interlayer insulating film 129 is formed so as to cover the wiring 128.

On the other hand, the active layer of the N-channel type TFT 204, the N ⁺ -type high concentration impurity region 111, a channel formation region 109, between the N ⁺ -type high concentration impurity region and the channel formation region of the N ^- type of A low concentration impurity region 112 is formed. The high-concentration impurity region in any of the active layers becomes a source region or a drain region. Wirings 122 and 123 are connected to these source or drain regions. Portions other than the active layer have the same structure as the P-channel TFT.

  The N-channel TFT 203 formed in the pixel matrix circuit 201 has the same structure as the N-channel TFT of the CMOS circuit up to the portion where the first interlayer insulating film 119 having flatness is formed. Finally, the wiring 121 is connected to the source region and the wiring 120 is connected to the drain region. A second interlayer insulating film 125 is formed thereon, and a black mask 126 is formed. The black mask covers the pixel TFT and forms an auxiliary capacitance with the wiring 120. Further, a third interlayer insulating film 129 is formed thereon, and the pixel electrode 130 made of a transparent conductive film such as ITO is connected.

  Next, a method for manufacturing the semiconductor device illustrated in FIG. 1 will be described in detail with reference to FIG.

  First, a substrate 100 having an insulating surface is prepared. As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or a semiconductor substrate can be used. In this embodiment, a quartz substrate is used as the substrate 100. Note that in order to improve flatness, it is preferable to provide a base film (made of a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like) over this substrate. In addition, peeling due to stress distortion between the substrate and the gate wiring material can be prevented.

  Next, a gate wiring and a gate electrode having a stacked structure are formed. In this embodiment, first, a tantalum nitride film (TaN) is formed on an insulating film, a tantalum film (Ta) is formed on the tantalum nitride film, and a tantalum nitride film (TaN) is formed on the tantalum film by a sputtering method. Form a continuous film. Then, patterning was performed to form a gate electrode having a three-layer structure. (FIG. 3 (A))

  In this embodiment, in order to form α─Ta having a low resistance, a structure in which a TaN film (preferably, a film thickness of 40 nm or more) is formed, and a Ta film is continuously stacked on the TaN film. .

  In addition, since the Ta film easily absorbs and oxidizes hydrogen as compared with the TaN film, in this embodiment, the structure (TaN [101a, 102a, 103a) sandwiching the Ta film as shown in FIG. , 104a; film thickness 50 nm] / Ta [101b, 102b, 103b, 104b; film thickness 250 nm] / TaN [101c, 102c, 103c, 104c; film thickness 50 nm]) to prevent an increase in resistance. In addition, the reason why the TaN film is laminated as the uppermost layer is to prevent the Ta film from being exposed to prevent oxidation and occlusion of hydrogen when forming a contact with another wiring, and to obtain a good ohmic contact. is there. Further, it is preferable to stack a TiN film as the uppermost layer because the TiN film does not become an insulator even if the TiN film is oxidized.

  Further, in place of tantalum as a wiring material, for example, Mo, Nb, W, Mo-Ta alloy, Nb-Ta alloy, W-Ta alloy, or the like can be used. Further, it is also possible to use a material in which nitrogen is added to these materials, or a silicide which is a compound of these materials and silicon.

  Next, a protective film 105 made of a silicon nitride film is formed to cover the gate electrode. Since the tantalum film used for the gate electrode in this example is liable to cause oxidation and occlusion of hydrogen, the gate electrode was covered with a protective film made of an inorganic film. In the case where high-temperature treatment (for example, a gettering step or the like) is performed, the protective film can suppress diffusion of impurities from the substrate due to heating, and can maintain a gate insulating film having favorable insulating properties. In addition, the protective film 105 can prevent the gate electrode and the wiring from laser light or heat. The thickness range of the protective film here is 10 to 100 nm, and in this example, 20 nm. (FIG. 3 (B))

Next, the gate insulating films 106a and 106b were formed to cover the protective film. In this embodiment, an insulating film 106a having a thickness of 125 nm and an insulating film 106b having a thickness of 75 nm formed of a silicon oxynitride film (SiO _x N _y ) are formed. The thickness of a region to be a gate insulating film of a high withstand voltage circuit is selectively made thicker than that of a region to be a gate insulating film of a high-speed driving circuit, so that a higher withstand voltage is obtained. As a method for forming insulating films having different thicknesses, known means may be used, for example, a method in which an insulating film having a thickness of 75 nm is formed over the entire surface, and an insulating film having a thickness of 50 nm is selectively stacked. May be used. As the insulating films 106a and 106b, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof can be used with a thickness of 50 to 300 nm.

  After the formation of the gate insulating film, an amorphous semiconductor film is continuously stacked, and an active layer is formed over the insulating films 106a and 106b. Note that in order to reduce impurities and improve throughput, it is preferable that the protective film 105, the insulating film 106, and the amorphous semiconductor film be successively formed. The active layer may be formed of a crystalline semiconductor film (typically, a crystalline silicon film) of 20 to 100 nm (preferably 25 to 70 nm). As a method for forming the crystalline semiconductor film, any known means, for example, laser crystallization, thermal crystallization, or the like may be used. In the present embodiment, a catalyst element that promotes crystallization during crystallization ( Nickel) was used. This technique is described in detail in JP-A-7-130652 and JP-A-9-312260.

  In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by a low pressure CVD method. Next, a Ni acetic acid solution was applied using a spinner and further dried to form a Ni layer 302. (FIG. 3C) However, the Ni layer does not form a complete layer. The Ni concentration of the Ni acetic acid solution is 1 to 1000 ppm in terms of weight. In this embodiment, it is set to 100 ppm. In this state, Ni is held on the surface of the amorphous silicon film. Next, a crystalline silicon film was obtained by heating at 550 ° C. for 8 hours in an inert or oxidizing atmosphere. (FIG. 3 (D))

  Next, laser irradiation is performed in an oxidizing atmosphere to form a thin oxide film 401 together with laser annealing. (FIG. 4 (A)) This thin oxide film is used to form a resist or an etching stopper in a later step in order to form an adhesive between the crystalline silicon film and the resist or an adhesive between the crystalline silicon film and the etching stopper. It plays the role of improving the character. However, when laser irradiation is performed in an inert atmosphere, no oxide film is formed.

  Next, a silicon oxide film is formed to a thickness of 120 nm and is patterned to form an etching stopper 118. Then, a doping mask 402 made of a resist is formed. Note that as another material used as the etching stopper 118, an amorphous silicon film, a crystalline silicon film, a silicon nitride film, or a silicon oxynitride film can be used.

The first doping of the phosphorus element was performed by a non-self-alignment process using the resist 402 as a mask. (FIG. 4B) In this embodiment, phosphorus is added to the N ⁺ type region 403 at a concentration of 1 × 10 ²⁰ to 8 × 10 ²¹ atoms / cm ³ .

After that, the resist mask 402 was removed, and second doping of the phosphorus element was performed using the etching stopper 118 as a mask. (FIG. 4 (C)) In the present embodiment, the phosphorus concentration of the N ⁻ type region indicated by 406 is adjusted so as to be 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ . Note that, in the N-channel TFT, the N ⁺ -type region 407 becomes a source region or a drain region, and the N ^-- type region becomes a low-concentration impurity region 406.

Next, the N-channel TFTs 203 and 204 are covered with a resist 501, and boron is added to the active layer of the P-channel TFT to form a P-type region 502 where phosphorus is present at a high concentration and a P-type region where phosphorus is present at a low concentration. A region 503 is formed. (FIG. 5A) The dose of boron is set so that the concentration of boron ions in the P-type region is about 1.3 to 2 times the concentration of phosphorus ions added to the N ⁺ -type region. Note that the method for adding phosphorus ions or boron ions in this embodiment is a known method, for example, an ion implantation method, a plasma doping method, a method of applying a solution containing phosphorus ions or boron ions, followed by heating, a film containing phosphorus ions or boron ions. Is performed by using a method of heating after film formation.

  The P-type regions 502 and 503 serve as a source region or a drain region of a P-channel TFT. In addition, a region into which phosphorus ions or boron ions are not implanted becomes an intrinsic or substantially intrinsic channel forming region which becomes a carrier movement path later.

Note that in this specification, intrinsic refers to a region which does not contain any impurity that can change the Fermi level of silicon, and a substantially intrinsic region is a region where electrons and holes are completely balanced to offset the conductivity type. Region, that is, a region containing an impurity imparting N-type or P-type in a concentration range (1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ ) in which threshold value control can be performed, or a reverse conductive intentionally 5 shows a region where the conductivity type is offset by adding a type impurity.

  Next, heat treatment was performed in an inert atmosphere or a dry oxygen atmosphere at 450 ° C. or higher for 0.5 to 12 hours, and in this example, 550 ° C. for 2 hours. (FIG. 5 (B))

  As a result of the above heating step, Ni intentionally added for crystallization of the amorphous silicon film is transferred from the channel formation region to the source region and the drain region as schematically shown by arrows in FIG. Spread to This is because these regions contain a high concentration of phosphorus element, and Ni that has reached the source region and the drain region is captured (gettered) there. Heat treatment at 400 to 600 ° C. for 0.5 to 4 hours can sufficiently getter Ni.

As a result, the Ni concentration in the channel formation region 110 can be reduced. The Ni concentration in the channel formation regions 107 to 110 can be set to 5 × 10 ¹⁷ atoms / cm ³ or less, which is the lower limit of SIMS detection. On the other hand, the Ni concentration in the source region and the drain region used for the gettering sink is higher than that in the channel formation region. (FIG. 5 (C))

  As an impurity imparting the N-type conductivity, antimony or bismuth can be used in addition to phosphorus. Phosphorus has the highest gettering ability, followed by antimony.

  In particular, the region 505 in which both the phosphorus and boron are added and the boron concentration is about 1.3 to 2 times that of phosphorus is higher than the gettering ability of the source and drain regions 504 of the N-channel TFT to which only phosphorus is added. Has been confirmed in experiments.

  Further, phosphorus and boron added to the source and drain regions and the low-concentration impurity regions are activated simultaneously with the gettering by this heat treatment. Conventionally, only heat treatment at about 450 ° C. was performed because the heat resistance of the wiring material (aluminum) was low. In this embodiment, by setting the heating temperature to 500 ° C. or higher, the dopant can be sufficiently activated, and the resistance of the source region and the drain region can be further reduced only by the heat treatment.

  Further, the heat treatment improves the crystallinity of the region where the crystallinity is destroyed during the ion doping step.

That is, in the heat treatment in the oxidizing atmosphere (FIG. 5B),
1) Gettering treatment to reduce the concentration of the catalyst element in the channel formation regions 107 to 110 2) Activation treatment of impurities in the source and drain regions 111, 114, 504, and 505 3) Damage to the crystal structure caused by ion implantation Annealing can be performed at the same time.

  Further, a step of performing optical annealing with laser light, infrared light, or ultraviolet light at the same time as or before or after this heat treatment step may be adopted.

  Next, the active layer is patterned into a desired shape to obtain a state shown in FIG.

  After that, in order to reduce the resistance of the high-concentration impurity region 111, a metal film for selective silicidation is formed on the active layer indicated by 111 and heat treatment is performed. It is preferable to silicide the set region. By adding this step, the resistance can be reduced, and an operating frequency on the order of several GHz can be realized. As the metal film for silicidation, a film made of a material containing cobalt, titanium, tantalum, tungsten, molybdenum, or the like as a main component can be used. Note that it is preferable to remove the thin oxide films 115 to 117 over the high-concentration impurity regions before forming the metal film in order to effectively silicide. Further, the etching stopper 118 may be removed.

  Then, a first interlayer insulating film 119 is formed on the entire surface of the substrate with a transparent organic resin film (acrylic resin). Here, a first interlayer insulating film 119 having a thickness of 1 μm is formed by spin coating. When a transparent organic resin film, for example, an acrylic resin, polyimide, or BCB (benzocyclobutene) is used, the surface can be flattened as illustrated. Further, as a material of another interlayer insulating film, a silicon oxide film or a silicon oxynitride film can be used.

  Then, a contact hole is formed, and a metal film (not shown) for forming a contact electrode is formed. Here, as the metal film, a three-layer film of a titanium film, an aluminum film, and a titanium film is formed by a sputtering method. Then, by patterning this metal film (laminated film), electrodes and wirings indicated by 120 to 124 are formed.

  Next, an organic resin film is formed as a second interlayer insulating film 125 to a thickness of 1 μm by spin coating. Then, in order to form an auxiliary capacitance, only a predetermined portion is etched to be thin. Then, a 300 nm thick metal film made of Ti was formed. Then, the metal film was patterned to form a black mask 126 and lead wires 127 and 128.

  Then, a third interlayer insulating film 129 is formed using an acrylic resin. Here, a 1 μm-thick third interlayer insulating film 129 is formed by spin coating. When a resin film is used, its surface can be flattened as shown.

  Next, a contact hole is formed, and a pixel electrode 130 is formed. Here, first, an ITO film having a thickness of 100 nm is formed by a sputtering method, and is patterned to form a pixel electrode denoted by 130.

  Finally, heat treatment is performed for one hour in a hydrogen atmosphere at 350 ° C. to reduce defects in the semiconductor layer. Thus, the state shown in FIG. 6B is obtained.

  In this embodiment, the gate electrode of the pixel TFT 203 of the pixel matrix circuit has a double gate structure. However, a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off-state current. Further, a single gate structure may be employed to improve the aperture ratio.

  The TFT structure shown in this embodiment is an example of a bottom gate type (etching stopper type), and is not particularly limited to the structure of this embodiment. For example, there is a channel etch type TFT structure and the like. Further, in this embodiment, an example in which a transmission type LCD is manufactured is shown, but this is merely an example of a semiconductor device. It is to be noted that the reflection type LCD can be easily manufactured by forming the pixel electrode with a highly reflective metal film in place of ITO, and appropriately changing the patterning of the pixel electrode by an operator. When a reflective LCD is manufactured, if a structure in which an insulating film is stacked on a heat-resistant metal film or a structure in which an insulating film is stacked on an aluminum nitride film is used as a base film, the metal film below the insulating film serves as a heat dissipation layer. Working and effective. It should be noted that the above sequence of steps can be appropriately changed by a practitioner.

  In the first embodiment, the patterning is performed in the step shown in FIG. 6A after the laser irradiation step. In the present embodiment, examples in which patterning is performed before the laser irradiation step are shown in FIGS. Show. Since the basic configuration is almost the same as that of the first embodiment, the following description focuses on the differences.

  This embodiment is the same as Embodiment 1 up to the step of obtaining the crystalline semiconductor film shown in FIG. After obtaining the state shown in FIG. 3D, patterning into a desired shape is performed, and then irradiation with laser light is performed in an oxidizing atmosphere to obtain the state shown in FIG. As shown in FIG. 7A, the surfaces of active layers 701 to 703 are covered with thin oxide films 704 to 706.

  Subsequent steps are the same as in the first embodiment, such as a high-concentration phosphorus doping step (FIG. 7B), a low-concentration phosphorus doping step (FIG. 7C), a boron doping step (FIG. 8A), The state of FIG. 8C is obtained through the ring process (FIG. 8B).

  Next, the etching stopper 707 disposed above the channel formation region is removed to obtain the state of FIG. Here, although the step of removing the etching stopper 707 is performed, it is not necessary to remove the etching stopper 707 in particular.

  Note that a step of removing the thin oxide films 704 to 706 before, after, or simultaneously with this step may be performed. Further, it is preferable to add a step of forming a metal film for silicidation over the high-concentration impurity region by removing the thin oxide film and then performing a heat treatment for silicidation. By doing so, the resistance of the source region and the drain region can be reduced, and an operating frequency on the order of several GHz can be realized. As the metal film for silicidation, a film made of a material containing cobalt, titanium, tantalum, tungsten, molybdenum, or the like as a main component can be used.

  Subsequent steps are the same as those in the first embodiment, and thus will not be described. Thus, the state shown in FIG. 9B was obtained. With such a configuration, the active layers 701 to 703 can be protected from diffusion of impurities from the interlayer insulating film by the thin oxide films 704 to 706.

  In the first embodiment, the thickness of the gate insulating film 106b of the CMOS circuit 202 and the gate insulating film 106a of the pixel matrix circuit 201, which constitute a part of the peripheral drive circuit unit, is different. FIG. 10 shows an example in which a gate insulating film having a thickness is used. Since the basic configuration is almost the same as that of the first embodiment, the following description focuses on the differences.

  This embodiment is the same as the first embodiment up to the step of forming the protective film shown in FIG. After obtaining the state shown in FIG. 3B according to Embodiment 1, a gate insulating film 1001 and an amorphous semiconductor film are continuously formed. After that, the active layer made of the crystalline semiconductor film is patterned through the same steps as in the first embodiment.

  After that, the thin oxide film and the etching stopper provided in contact with the active layer were removed, and a metal film was selectively formed on the high-concentration impurity region. By doing so, the resistance of the source region and the drain region can be reduced, and an operating frequency on the order of several GHz can be realized. As the metal film for silicidation, a film made of a material containing cobalt, titanium, tantalum, tungsten, molybdenum, or the like as a main component can be used. After that, an interlayer insulating film 1002 made of a silicon oxide film was formed. Thereafter, through the same steps as in the first embodiment, the configuration shown in FIG. 10 is obtained.

  This embodiment can be combined with the second embodiment.

  This embodiment is an example in which a crystalline semiconductor film is obtained by a method different from that of the first embodiment. This embodiment relates to a method for obtaining a crystalline semiconductor film by adding a catalytic element using a mask and performing heat treatment. Since the basic configuration is almost the same as that of the first embodiment, the following description focuses on the differences.

  This embodiment is the same as Embodiment 1 up to the step of forming the protective film shown in FIG. After obtaining the state of FIG. 3B according to the first embodiment, an amorphous semiconductor film is formed, and then a mask made of a silicon oxide film is formed. The mask is provided with openings. Next, a catalyst element (Ni) is held in a region where the opening is provided by using a nickel acetate salt solution.

  Next, the amorphous semiconductor film is crystallized by heating (400 to 700 ° C.). At this time, crystal growth proceeds from the region where the opening is provided in a direction parallel to the substrate surface. This crystal growth is called lateral growth or lateral growth. After that, the mask was removed. Good characteristics can be obtained by using the region crystallized by the lateral growth as a channel formation region of the TFT. By using the present invention, a heat treatment at 400 ° C. or more can be performed, and a crystalline semiconductor film can be obtained. Thereafter, the same configuration as that of FIG. 1 can be obtained through the same steps as those of the first embodiment (from FIG. 4A).

  This embodiment can be combined with other embodiments 2 and 3.

This embodiment is an example in which a crystalline semiconductor film is obtained by a method different from that of the first embodiment. In the present embodiment, a laser beam is shaped into a rectangle or a square using a catalytic element that promotes crystallization of silicon, and a single laser irradiation is performed in a region of several cm ² to several hundred cm ² by a single irradiation. The present invention relates to a method for obtaining a crystalline semiconductor film by a treatment. Since the basic configuration is almost the same as that of the first embodiment, the following description focuses on the differences.

  This embodiment is the same as the first embodiment up to the step of holding the catalytic element on the surface of the amorphous silicon film shown in FIG. The Ni concentration of the Ni acetic acid solution in the step shown in FIG. 3C is 1 to 1000 ppm in terms of weight. In this embodiment, it is set to 100 ppm. In this state, Ni is held on the surface of the amorphous silicon film. Next, a crystalline silicon film was obtained by irradiating an excimer laser beam (wavelength: 248 to 308 nm) in an inert or oxidizing atmosphere.

In the present embodiment, a laser device having a wavelength of 248 nm is shaped into a rectangle or a square, and a laser device (SAELC manufactured by Sopra, Inc.) capable of irradiating a uniform laser beam to a region of several cm ² to several hundred cm ² by one irradiation. ) Was used to obtain a crystalline silicon film. Thereafter, the same configuration as that of FIG. 1 can be obtained through the same steps as those of the first embodiment (after the step shown in FIG. 4A).

This embodiment can be combined with the other embodiments 2 to 4.

  In this embodiment, a configuration for obtaining a good ohmic contact in connection between wirings will be described with reference to FIG. Since the basic configuration of the pixel matrix circuit is almost the same as that of the first embodiment, the following description focuses on the differences.

First, a substrate having an insulating surface is prepared as in the first embodiment. Then, a base film (not shown) made of a silicon oxide film is formed. Then, a layer made of a metal material, typically, a layer 1102 (thickness: 20 nm to 100 nm) mainly containing titanium is continuously formed on the layer 1101 mainly containing tantalum and patterned to form a multilayer wiring. Was provided. Thereafter, as in Example 1, formation of a gate insulating film, formation of an active layer, formation of an interlayer insulating film, formation of a contact hole, and the like were performed.

This layer mainly containing titanium prevents oxidation and occlusion of hydrogen of the layer 1101 mainly containing tantalum when forming a contact hole (opening portion). In addition, a layer containing titanium as a main component may be partially removed at the same time as an interlayer insulating film is formed at the time of forming an opening portion. Can be obtained. In other words, the layer containing titanium as the main component protects the layer containing tantalum as the main component, and has a sufficient etching margin to facilitate the formation of the opening. Then, after forming the opening, a wiring 1103 was formed and connected to the multilayer wirings 1101 and 1102. Thereafter, the state of FIG. 11 was obtained in the same manner as in Example 1.

  Further, instead of the layer mainly containing titanium, a layer mainly containing one kind of element selected from Cr, Mn, Co, Ni, Cu, Mo, and W can be used.

  Note that, unlike the structure of the first embodiment, in this embodiment, the etching stopper and the thin oxide film are removed. Further, the configuration was such that no protective film was formed.

  This embodiment can be combined with the other embodiments 2 to 5.

  An example in which an AMLCD is configured by using a TFT substrate (substrate on the element formation side) including the configuration shown in the first to sixth embodiments will be described. FIG. 12 shows the appearance of the AMLCD of this embodiment.

  In FIG. 12A, reference numeral 1201 denotes a TFT substrate on which a pixel matrix portion 1202, a source driver circuit 1203, and a gate driver circuit 1204 are formed. The pixel matrix portion corresponds to FIGS. 2A and 1 and a part thereof is shown. The driving circuit corresponds to FIGS. 2B and 1 and preferably includes a CMOS circuit in which an N-type TFT and a P-type TFT are complementarily combined as partially shown. Reference numeral 1205 denotes a counter substrate.

  In the AMLCD shown in FIG. 12A, an active matrix substrate 1201 and a counter substrate 1205 are attached to each other with their end faces aligned. However, only a part of the counter substrate 1205 is removed, and an FPC (flexible print circuit) 1206 is connected to the exposed active matrix substrate. The FPC 1206 transmits an external signal to the inside of the circuit.

  Further, IC chips 1207 and 1208 are attached using a surface on which the FPC 1206 is attached. These IC chips are formed by forming various circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate. In FIG. 12A, two are attached, but one or more may be attached.

  Further, a configuration as shown in FIG. In FIG. 12B, the same parts as those in FIG. 12A are denoted by the same reference numerals. Here, FIG. 12A illustrates an example in which signal processing performed by an IC chip is performed by a logic circuit (logic circuit) 1209 formed using TFTs over the same substrate. In this case, the logic circuit 1209 is also configured based on a CMOS circuit similarly to the drive circuits 1203 and 1204.

  In addition, color display may be performed using a color filter, or a configuration in which a liquid crystal is driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like without using a color filter may be employed.

  The AMLCD described in Embodiment 7 is used as displays of various electronic devices. Note that an electronic device described in this embodiment is defined as a semiconductor device on which a semiconductor circuit is mounted.

  Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head-mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, and the like). . One example of these is shown in FIG.

  FIG. 13A illustrates a mobile computer (mobile computer), which includes a book 2001, a camera unit 2002, an image receiving unit 2003, operation switches 2004, and a display device 2005. The present invention can be applied to the image receiving unit 2003, the display device 2005, and the like.

  FIG. 13B illustrates a head-mounted display, which includes a main body 2101, a display device 2102, and a band portion 2103. The present invention can be applied to the display device 2102.

  FIG. 13C illustrates a mobile phone, which includes a main body 2201, an audio output unit 2202, an audio input unit 2203, a display device 2204, operation switches 2205, and an antenna 2206. The present invention can be applied to the audio output unit 2202, the audio input unit 2203, the display device 2204, and the like.

  FIG. 13D illustrates a video camera, which includes a main body 2301, a display device 2302, an audio input portion 2303, operation switches 2304, a battery 2305, and an image receiving portion 2306. The present invention can be applied to the display device 2302, the audio input unit 2303, and the image receiving unit 2306.

  FIG. 13E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.

  FIG. 13F illustrates a portable book, which includes a main body 2501, display devices 2502 and 2503, a storage medium 2504, operation switches 2505, and an antenna 2506. The data stored in the storage medium (MD, DVD, or the like) or the data obtained from an antenna (for example, a satellite antenna or the like) is displayed. The present invention can be applied to the display devices 2502 and 2503.

  As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. In addition, the present invention can also be used for an electronic bulletin board, a display for advertising, and the like.

Sectional view showing one example of the structure of the present invention (Example 1) Top view showing an example of the structure of the present invention (Example 1) Sectional view showing one example of a manufacturing process of the present invention (Example 1) Sectional view showing one example of a manufacturing process of the present invention (Example 1) Sectional view showing one example of a manufacturing process of the present invention (Example 1) Sectional view showing one example of a manufacturing process of the present invention (Example 1) Sectional drawing which shows an example of the manufacturing process of the present invention (Example 2) Sectional drawing which shows an example of the manufacturing process of the present invention (Example 2) Sectional drawing which shows an example of the manufacturing process of the present invention (Example 2) Sectional drawing which shows an example of the structure of this invention (Example 3) Sectional drawing which shows an example of the structure of this invention (Example 6) External view of AMLCD Electrical equipment

Explanation of reference numerals

100 Substrate 101, 102 Gate wiring or electrode (pixel matrix circuit)
103 gate wiring or electrode (N-channel TFT of CMOS circuit)
104 gate wiring or electrode (P-channel TFT of CMOS circuit)
105 Protective film 106 Gate insulating films 107 to 110 Channel formation region 111 High concentration impurity region 112 Low concentration impurity region 113 High concentration impurity region (N-channel TFT)
114 Low-concentration impurity region (P-channel TFT)
115-117 Oxide film 118 Etching stopper 119 First interlayer insulating film 120-124 Wiring 125 Second interlayer insulating film 126 Black mask 127, 128 Lead wiring 129 Third interlayer insulating film 130 Pixel electrode

Claims (7)

A gate electrode having a laminated structure formed on the substrate,
A protective film covering the top and side surfaces of the gate electrode and the substrate,
A gate insulating film formed to cover the protective film;
A semiconductor circuit using a semiconductor element having a semiconductor film formed on the gate insulating film. A gate electrode having a laminated structure formed on the substrate,
A protective film covering the top and side surfaces of the gate electrode and the substrate,
A gate insulating film formed to cover the protective film;
And a semiconductor film having a channel formation region formed on the gate insulating film. A gate electrode having a laminated structure formed on a substrate having an insulating surface,
An inorganic insulating film covering the top and side surfaces of the gate electrode and the substrate,
A gate insulating film formed over the inorganic insulating film,
A semiconductor film having a channel formation region formed on the gate insulating film;
A silicon nitride film formed in contact with the channel formation region;
A semiconductor circuit using a semiconductor element having an organic resin film formed on the silicon nitride film. A gate electrode formed by laminating three layers formed on a glass substrate;
A gate insulating film formed on the gate electrode;
A semiconductor film having a channel formation region formed on the gate insulating film;
A silicon nitride film formed in contact with the channel formation region;
An organic resin film formed on the silicon nitride film,
A semiconductor circuit using a semiconductor element, wherein a top layer of the gate electrode is made of a TiN film.   3. The semiconductor circuit according to claim 1, wherein the protective film is made of an inorganic film.   A display device comprising the semiconductor circuit according to claim 1.   A personal computer, a video camera, a mobile computer, a mobile phone, a mobile book, a head-mounted display, or a projector equipped with the display device according to claim 6.

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