JP2009135530A - Liquid crystal display and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display having a new electrode structure according to the need of an electrode structure that has a low resistance ratio and sufficiently withstands a gettering process. <P>SOLUTION: The liquid crystal display includes a semiconductor circuit having a semiconductor element. The semiconductor element includes, on a substrate having an insulation surface, a gate electrode having a multilayer structure, a protective film covering the substrate and the upper and side surfaces of the gate electrode, a gate insulation film formed while covering the protective film, and a source region, a drain region, and a channel formation region formed between the source and drain regions while they abut on the gate insulation film. The protective film restrains the diffusion of impurities from the substrate by performing high-temperature treatment, thus obtaining satisfactory TFT characteristics regardless of concentration of impurities of the substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a structure of a semiconductor device including a semiconductor circuit made of a semiconductor element such as an insulated gate transistor. The semiconductor device of the present invention includes not only an element such as a thin film transistor (TFT) and a MOS transistor but also an electro-optical device such as a display device and an image sensor having a semiconductor circuit composed of these insulated gate transistors. In addition, the semiconductor device of the present invention includes an electronic apparatus in which these display device and electro-optical device are mounted.

An active matrix liquid crystal display in which a pixel matrix circuit and a driving circuit are formed by thin film transistors (TFTs) formed over an insulating substrate has been attracting attention. Liquid crystal displays of up to about 0.5 to 20 inches are used as display displays.

There is an increase in area in one direction of liquid crystal display development. However, when the area is increased, the area of the pixel matrix circuit serving as a pixel display portion is also increased, and accordingly, the source wiring and the gate wiring arranged in a matrix become longer, and thus the wiring resistance is increased. Furthermore, since higher definition is required, it is necessary to make the wiring thinner, and an increase in wiring resistance has become more obvious.
In addition, TFTs are connected to the source wiring and the gate wiring for each pixel, and the number of pixels increases, which increases the parasitic capacitance. In a liquid crystal display, the gate wiring and the gate electrode are generally formed integrally, and the delay of the gate signal becomes obvious as the area of the panel increases.

Therefore, as the resistivity of the gate electrode wiring material is lower, the gate wiring can be made thinner and longer, thereby increasing the area. Conventionally, Al, Ta, Ti and the like have been used as a gate electrode wiring material. Among them, Al is frequently used because it has the lowest resistivity and can be anodized. However, although Al can improve heat resistance by forming an anodized film, whisker and hillock are generated, wiring is deformed, and an insulating film and an active layer are formed even at a process temperature of 300 ° C. to 400 ° C. This is the main cause of TFT malfunction and TFT characteristics degradation.

Further, in order to achieve a larger area and higher definition, an electrode structure having a lower specific resistance and higher heat resistance is required.

At present, TFTs are required to have high mobility, and it is considered promising to use a crystalline semiconductor film having higher mobility than an amorphous semiconductor film as an active layer. Conventionally, in order to obtain a crystalline semiconductor film by heat treatment, it is necessary to use a quartz substrate having a high strain point. Since quartz substrates are expensive, there is a need for low crystallization temperatures that allow the use of inexpensive glass substrates.

Therefore, the applicants introduce a trace amount of metal element into an amorphous semiconductor film (typically, an amorphous silicon film, an amorphous silicon film containing Ge, or the like), and then perform heat treatment. Technology for obtaining a crystallized semiconductor film by this method (JP-A-6-232059, JP-A-7-321339, etc.)
Developed. Examples of metal elements that promote crystallization include Fe, Co, Ni, Ru, Rh, and Pd.
, Os, Ir, Pt, Cu, Au, or one or more types selected from them.
By using this technique, it has become possible to produce a crystalline semiconductor film by a process (low temperature process) at a temperature that a glass substrate can withstand. Alternatively, Ge or Pb in which diffusion in the amorphous semiconductor film is substitutional diffusion can be used.

However, the problem with this technique is that the metal element used for crystallization remains in the crystalline semiconductor film, which adversely affects the device characteristics (especially reliability, uniformity, etc.) of the TFT. In view of this, the present applicants have also developed a technique (JP-A-8-330602) for gettering a metal element in a crystalline semiconductor film after forming a wiring using an aluminum material. This publication discloses a technique in which a catalytic element in a channel formation region is gettered to a source region and a drain region by performing heat treatment using a source region and a drain region to which phosphorus is added as a getter link sink. Are listed.

However, in the above-mentioned publication technique, an aluminum material having low heat resistance is used for the wiring, so that the heat treatment is limited to a temperature range (about 300 to 450 ° C.). In order to obtain a sufficient gettering effect, heat treatment at 400 ° C. or higher, preferably 550 ° C. or higher is required.

As described above, the present invention provides a semiconductor device having a novel electrode structure and a method for manufacturing the same according to the need for an electrode structure that has a low specific resistance and can sufficiently withstand the gettering step. .

The first configuration of the invention disclosed in this specification is:
A gate electrode having a multilayer structure over a substrate having an insulating surface;
A protective film covering the substrate and the upper and side surfaces of the gate electrode;
A gate insulating film formed to cover the protective film;
A semiconductor circuit including a semiconductor element, comprising a source region, a drain region, and a channel formation region formed between the source region and the drain region in contact with the gate insulating film. Semiconductor device.

In the above structure, the gate electrode having the multilayer structure includes at least one layer mainly composed of one kind of element selected from tantalum, molybdenum, titanium, chromium, and silicon.

Further, in the above structure, the gate electrode having the multilayer structure includes, in order from the substrate side, a layer mainly containing a first tantalum containing nitrogen, a layer mainly containing a second tantalum, and a first layer containing nitrogen. It is characterized in that it has a three-layer structure composed of three tantalum-based layers.

In addition, the second configuration which is the configuration of another invention disclosed in this specification is:
A gate electrode over a substrate having an insulating surface;
A protective film covering the substrate and the upper and side surfaces of the gate electrode;
A gate insulating film formed to cover the protective film;
A source region, a drain region, and a channel formation region formed between the source region and the drain region in contact with the gate insulating film;
An inorganic insulator in contact with the channel formation region;
An organic resin film in contact with the source region and the drain region is a semiconductor device including a semiconductor circuit including a semiconductor element.

In the second structure, the gate electrode has a first layer mainly containing tantalum containing nitrogen, a second layer mainly containing tantalum, and tantalum containing nitrogen as a main component. It has a three-layer structure composed of a third layer.

In each of the above structures, the protective film is a silicon nitride film.
The protective film has a thickness of 10 to 100 nm.

In each of the above structures, at least a part of the source region and the drain region is silicide.

In each of the above structures, an impurity imparting N-type conductivity is added to the source region and the drain region.

In each of the above structures, an impurity imparting an N-type conductivity type and an impurity imparting a P-type conductivity type are added to the source region and the drain region.

In each of the above structures, the channel formation region contains a catalytic element that promotes crystallization of silicon, and the concentration of the catalytic element is higher in the source region and the drain region than in the channel formation region.

In each of the above structures, the catalyst element is at least one element selected from Ni, Fe, Co, Pt, Cu, Au, and Ge.

In addition, the third configuration which is the configuration of another invention disclosed in this specification is:
Forming a wiring on a substrate having an insulating surface;
Forming a protective film covering the wiring;
Forming a gate insulating film on the protective film;
Forming a crystalline semiconductor film containing a catalytic element for promoting crystallization of silicon on the gate insulating film;
Irradiating the crystalline semiconductor film with laser light;
Forming a mask made of an insulating film on a part of the crystalline semiconductor film;
Doping with phosphorus in a region to be a source region or a drain region;
Applying heat treatment to getter the catalyst element;
Patterning the crystalline semiconductor film to form an active layer;
A method for manufacturing a semiconductor device including a semiconductor circuit including a semiconductor element including

In addition, the fourth configuration which is the configuration of another invention disclosed in this specification is:
Forming a wiring on a substrate having an insulating surface;
Forming a protective film covering the wiring;
Forming a gate insulating film on the protective film;
Forming a crystalline semiconductor film containing a catalytic element for promoting crystallization of silicon on the gate insulating film;
Patterning the crystalline semiconductor film to form an active layer;
Irradiating the crystalline semiconductor film with laser light;
Forming a mask made of an insulating film on a part of the crystalline semiconductor film;
Doping with phosphorus in a region to be a source region or a drain region;
Applying heat treatment to getter the catalyst element;
A method for manufacturing a semiconductor device including a semiconductor circuit including a semiconductor element including
The step of forming a wiring on a substrate having an insulating surface includes:
From the semiconductor element, which is a step of successively forming and patterning a first tantalum layer containing nitrogen, a second tantalum layer, and a third tantalum layer containing nitrogen in order from the substrate side This is a method for manufacturing a semiconductor device including the semiconductor circuit.

Forming the crystalline semiconductor film over the gate insulating film in the third configuration or the fourth configuration includes forming an amorphous semiconductor film in contact with the gate insulating film surface;
Holding the catalyst element for promoting crystallization of silicon in the amorphous semiconductor film;
The method includes a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film.

Forming the crystalline semiconductor film over the gate insulating film in the third configuration or the fourth configuration includes forming an amorphous semiconductor film in contact with the gate insulating film surface;
Holding the catalyst element for promoting crystallization of silicon in the amorphous semiconductor film;
The method includes a step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film by laser light irradiation.

By utilizing the invention disclosed in this specification, a gate wiring and an electrode (wiring width: 0.1 μm)
m.about.5 .mu.m), a semiconductor device having good TFT characteristics can be obtained even when heat treatment is performed at a high temperature (400.degree. C. or higher).

In addition, the protective film disclosed in this specification can suppress diffusion of impurities from the substrate when subjected to high-temperature treatment, and can obtain favorable TFT characteristics regardless of the impurity concentration of the substrate. it can.

In particular, in the high-temperature treatment (400 degrees or more) after the step of adding an impurity imparting P-type or N-type conductivity in the invention disclosed in this specification, the impurity was activated and damaged by the adding step. An annealing effect of the crystalline semiconductor film and a gettering effect of reducing the catalytic element remaining in the crystalline semiconductor film can be obtained.

Sectional drawing which shows an example of the structure of this invention (Example 1) Top view showing an example of the structure of the present invention (Example 1) Sectional drawing which shows an example of the preparation process of this invention (Example 1) Sectional drawing which shows an example of the preparation process of this invention (Example 1) Sectional drawing which shows an example of the preparation process of this invention (Example 1) Sectional drawing which shows an example of the preparation process of this invention (Example 1) Sectional drawing which shows an example of the preparation process of this invention (Example 2) Sectional drawing which shows an example of the preparation process of this invention (Example 2) Sectional drawing which shows an example of the preparation process of this invention (Example 2) Sectional drawing which shows an example of the structure of this invention (Example 3) Sectional drawing which shows an example of the structure of this invention (Example 6) AMLCD external view Electrical equipment

In this embodiment, tantalum or a material containing tantalum as a main component is used as a gate wiring and a gate electrode material. Since tantalum has a work function close to that of silicon,
This is one of the preferable materials with little shift of the threshold value of TFT.

Ta has two types of crystal structures (body-centered cubic lattice [α-Ta], tetragonal lattice structure [β-Ta])
It is known that there is. The specific resistance of a thin film having a square lattice structure [β-Ta] is 17
The resistance of a thin film having a body-centered cubic lattice [α-Ta] of about 0 to 200 μΩcm is 13
˜15 μΩcm. In general, most Ta thin films are β-Ta, but it is known that α-Ta (also referred to as bcc-Ta) can be formed by mixing a trace amount of impurities, for example, N ₂ during film formation.

In the present embodiment, α-Ta can be obtained by forming a TaN film and then successively laminating a Ta film on the TaN film. In particular, although depending on the component structure of the TaN film, the film thickness of the TaN film was 30 nm or more, preferably 40 nm or more, and when Ta films were laminated, α-Ta could be obtained.

However, since tantalum or a material containing tantalum as a main component easily absorbs hydrogen and easily oxidizes, there has been a problem that after film formation, a change in film quality such as oxidation or storage of hydrogen occurs and resistance increases. .

Therefore, in this embodiment, as a structure of the gate wiring and the gate electrode, a Ta film is continuously laminated on a TaN film (film thickness of 30 nm or more, preferably 40 nm or more), and further on this Ta film. A three-layer structure in which a TaN film is stacked is formed, and after that, a pattern is formed and then a structure is covered with a protective film.

In this way, the film was continuously formed into a three-layer structure, and further covered with a protective film to prevent hydrogen occlusion and oxidation.

Table 1 shows changes in the resistance value of the tantalum multilayer film (TaN / Ta / TaN; film thickness 50 nm / 250 nm / 50 nm) before and after heat treatment (450 ° C., 500 ° C., 550 ° C., 600 ° C.) for 2 hours. The temperature history in this experiment is that the temperature is increased from 400 ° C. to 10 ° C. below the processing temperature at 9.9 ° C./min, then the temperature is increased to the processing temperature at 5 ° C./min, held for 2 hours, and then gradually cooled. The measurement was performed.

From Table 1, it can be seen that the resistance value and the film thickness are increased because the tantalum multilayer film is altered (oxidized or the like) as the heating temperature is increased.

Next, Table 2 shows the resistance of a tantalum multilayer film (TaN / Ta / TaN) covered with a protective film (SiN: film thickness 25 nm) before and after heat treatment for 2 hours (450 ° C., 500 ° C., 550 ° C., 600 ° C.). Indicates a change in value. The temperature history was the same as in Table 1.

It can be seen from Table 2 that the increase in resistance value and film thickness due to heat treatment can be suppressed by applying a protective film (SiN).

From the above, using a highly heat-resistant Ta film or a film mainly composed of Ta as a wiring material,
Further, by covering with a protective film, a heat treatment at a high temperature (400 to 700 ° C.) can be performed. For example, a treatment for gettering a metal element in the crystalline semiconductor film can be performed. Even if such heat treatment is applied, the gate wiring (wiring width: 0.1 μm to 5 μm) is within a temperature range that can be withstood and is protected by a protective film, so that it is not oxidized and a low resistance wiring is formed. Can be maintained.

The nitrogen composition ratio in the TaN film is in the range of 5 to 60%, but is not necessarily limited to the above values because it depends on the sputtering apparatus, sputtering conditions, and the like. Ar
It is preferable to obtain an α-Ta film using plasma using (argon) or Xe (xenon).

Further, instead of tantalum, for example, Mo, Ti, Nb, W, Mo-Ta alloy, Nb-T
It is also possible to use materials such as an a alloy and a W—Ta alloy. It is also possible to use a metal material in which nitrogen is contained in these materials, or silicide which is a compound of these materials and silicon.

As the protective film in this embodiment, an inorganic insulating film such as a silicon nitride film, a silicon nitride oxide film, or a stacked film thereof can be used. The protective film has a thickness of 10 to 100 nm.
If it is in the range, it functions as a protective film. It is also possible to use an amorphous silicon film or a crystalline silicon film as the protective film.

In addition, since the TaN film is less likely to absorb hydrogen and oxidize compared to the Ta film, when forming a contact hole, a TaN film is laminated as the uppermost layer so that Ta is not exposed, and good ohmic contact is achieved. It was set as the structure to obtain.

Further, as another configuration for obtaining a good ohmic contact in connection between wirings, as shown in FIG. 11, a multilayer wiring in which a layer 1102 mainly containing titanium is laminated on a layer 1101 mainly containing tantalum. It is preferable to adopt a configuration in which This layer containing titanium as a main component prevents oxidation of the layer 1101 containing tantalum as a main component and occlusion of hydrogen when forming contact holes. Further, a layer containing titanium as a main component does not become an insulator even when exposed and oxidized, and can be easily removed, so that a good ohmic contact can be obtained. In other words, the layer containing titanium as a main component protects the layer containing tantalum as a main component, and also makes it easy to form a contact hole (opening portion) because a sufficient margin can be taken during the etching process.

By using a highly heat-resistant Ta film or a film mainly composed of Ta as a wiring material, high temperature (4
It is possible to perform a heat treatment at a temperature of 00 to 700 ° C., for example, a treatment of gettering a metal element in the crystalline semiconductor film can be performed. Note that when high-temperature treatment is performed, the protective film can suppress diffusion of impurities from the substrate due to heating, and can maintain a gate insulating film having favorable insulating properties. Therefore, a TFT having good characteristics can be manufactured regardless of the concentration of impurities contained in the substrate.

In this manner, the semiconductor device of the present invention can reduce the specific resistance as compared with the conventional (Ta film [β-Ta]), and the heat treatment is performed at a high temperature (400 to 700 ° C.). Even in this case, it was possible to obtain good TFT characteristics without being influenced by the concentration of impurities contained in the substrate.

  Examples will be described below, but it is needless to say that the present invention is not limited to these examples.

An example of a structure of a semiconductor device including a semiconductor circuit including a semiconductor element using the invention described in this specification will be described with reference to FIG. Such a semiconductor device includes a peripheral drive circuit portion and a pixel matrix circuit portion on the same substrate. In this embodiment, for ease of illustration, a CMOS circuit 202 that constitutes a part of the peripheral drive circuit portion on the same substrate, a pixel TFT 203 (N-channel TFT) that constitutes a part of the pixel matrix circuit portion, and It is shown.

2 is a diagram corresponding to the top view of FIG. 1. In FIG. 2, a portion cut by a thick line AA ′ corresponds to a cross-sectional structure of the pixel matrix circuit 201 of FIG. A portion cut by “′” corresponds to the cross-sectional structure of the CMOS circuit 202 of FIG.

On any of the thin film transistors (TFTs) 203 to 205, a gate electrode is patterned on the substrate 100 in a predetermined shape. The gate electrodes 101 to 1
04 is provided on a base film (not shown) and has a multilayer structure. In this embodiment, T
The structure of sandwiching the a film (TaN [film thickness 50 nm] / Ta [film thickness 250 nm] / TaN [film thickness 50 nm]) prevents an increase in resistance. A protective film 105 made of an inorganic film is formed so as to cover the gate electrode and the substrate. On the gate insulating films 106a, 106
b is formed. Furthermore, active layers 107 to 114 made of a crystalline semiconductor film are formed thereon. Thin oxide films 115 to 117 are formed on the surface of the active layer by laser light irradiation in an oxidizing atmosphere.

In the case of a P-channel TFT 205 of a CMOS circuit, a P ⁺ -type high concentration impurity region (source region or drain region) 113 as an active layer, a channel formation region 110, and the P
^A low concentration impurity region 114 is formed between the ⁺ type high concentration impurity region and the channel formation region. Further, an etching stopper 118 is formed on the channel formation region. A contact hole is formed in the first interlayer insulating film 119 having flatness to cover it, a wiring 124 is connected to the high-concentration impurity region 113, and a second interlayer insulating film 125 is further formed thereon.
Is formed, the wiring 128 is connected to the wiring 124, and the third interlayer insulating film 1 is covered thereover.
29 is formed.

On the other hand, for the active layer of the N-channel TFT 204, the N ⁺ -type high concentration impurity region 11 is used.
1, a channel formation region 109, and an N ⁻ type low concentration impurity region 112 is formed between the N ⁺ type high concentration impurity region and the channel formation region. The high concentration impurity region in any active layer becomes a source region or a drain region. Wirings 122 and 123 are connected to these source region or drain region. Portions other than the active layer are P channel type T
It has the same structure as FT.

For the N-channel TFT 203 formed in the pixel matrix circuit 201, the N-channel TF of the CMOS circuit is formed up to the portion where the first interlayer insulating film 119 having flatness is formed.
It has the same structure as T. Finally, the wiring 121 is connected to the source region, and the wiring 120 is connected to the drain region. A second interlayer insulating film 125 is formed thereon, and a black mask 126 is formed. This black mask covers the pixel TFT, and the wiring 120
And form an auxiliary capacity. Further, a third interlayer insulating film 129 is formed thereon, and ITO
A pixel electrode 130 made of a transparent conductive film is connected.

  Next, a method for manufacturing the semiconductor device illustrated in FIG. 1 will be described in detail with reference to FIGS.

First, the substrate 100 having an insulating surface is prepared. As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or a semiconductor substrate can be used. In this embodiment, the substrate 100
A quartz substrate was used. In order to improve flatness, it is preferable to provide a base film (made of a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like) over this substrate. Further, it is possible to prevent peeling due to stress distortion between the substrate and the gate wiring material.

Next, a gate wiring and a gate electrode having a stacked structure are formed. In this embodiment, first, a tantalum nitride film (TaN) is formed on the insulating film, and a tantalum film (TaN) is formed on the tantalum nitride film.
And a tantalum nitride film (TaN) are continuously formed on the tantalum film by a sputtering method. Then, patterning was performed to form a gate electrode having a three-layer structure. (Fig. 3 (A))

In this embodiment, in order to form low resistance α-Ta, a TaN film (preferably a film thickness of 40 nm or more) is formed, and then a Ta film is continuously laminated on the TaN film. .

Further, since the Ta film is more likely to store and oxidize hydrogen than the TaN film, in this embodiment, a structure in which the Ta film is sandwiched as shown in FIG. 3A (TaN [101a, 102a, 1
03a, 104a; film thickness 50 nm] / Ta [101b, 102b, 103b, 104b;
Film thickness 250 nm] / TaN [101c, 102c, 103c, 104c; film thickness 50 nm]
) Prevented the increase in resistance. In addition, the TaN film was stacked as the uppermost layer in order to prevent the Ta film from being exposed to cause oxidation and occlusion of hydrogen when forming a contact with other wiring, and to obtain a good ohmic contact. is there. Further, it is preferable to stack a TiN film as the uppermost layer because an insulator is not formed even when the TiN film is oxidized.

Further, instead of tantalum of the wiring material, for example, Mo, Nb, W, Mo—Ta alloy, Nb
It is also possible to use a -Ta alloy, a W-Ta alloy, or the like. It is also possible to use materials containing nitrogen in these materials, or silicide which is a compound of these materials and silicon.

Next, a protective film 105 made of a silicon nitride film is formed so as to cover the gate electrode. Since the tantalum film used for the gate electrode in this example easily oxidizes and occludes hydrogen, the gate electrode was covered with a protective film made of an inorganic film. In addition, when a high temperature treatment (for example, a gettering step) is performed, the protective film can suppress diffusion of impurities from the substrate due to heating, and can maintain a gate insulating film having good insulating properties. In addition, the protective film 105 can prevent the gate electrode and the wiring from laser light or heat. The protective film thickness range here is 10-100.
nm, 20 nm in this example. (Fig. 3 (B))

Next, gate insulating films 106a and 106b were formed to cover the protective film. In this example,
125 nm thick insulating film 106 a made of silicon oxynitride film (SiO _x N _y ), 75 nm
An insulating film 106b having a thickness of 5 mm was formed. The thickness of the region that becomes the gate insulating film of the high voltage circuit is selectively made thicker than the region that becomes the gate insulating film of the high-speed driving circuit, so that a higher voltage is obtained. As a method for forming insulating films having different film thicknesses, a known means may be used.
After forming an insulating film having a thickness of m over the entire surface, a method of selectively stacking an insulating film having a thickness of 50 nm may be used. As the insulating films 106a and 106b, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof can be used with a thickness of 50 to 300 nm.

Then, after forming the gate insulating film, an amorphous semiconductor film is continuously stacked, and this insulating film 106a
, 106b, an active layer is formed. Note that it is preferable that the protective film 105, the insulating film 106, and the amorphous semiconductor film be successively formed in order to reduce impurities and improve throughput. 2 active layers
A crystalline semiconductor film (typically a crystalline silicon film) with a thickness of 0 to 100 nm (preferably 25 to 70 nm) may be used. As a method for forming the crystalline semiconductor film, any known means, for example, laser crystallization, thermal crystallization, etc. may be used. In this embodiment, a catalytic element (which promotes crystallization during crystallization) ( The method of adding nickel) was used. This technique is disclosed in JP-A-7-13.
No. 0652, JP-A-9-312260 and the like.

In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by a low pressure CVD method. Next, a Ni acetic acid solution was applied using a spinner and further dried to form a Ni layer 302. (Fig. 3 (C)
However, the Ni layer is not a complete layer. The Ni concentration of the Ni acetic acid solution is 1-1000 ppm in terms of weight. In this example, it was set to 100 ppm. In this state, Ni is held on the surface of the amorphous silicon film. Next, 550 ° C. in an inert or oxidizing atmosphere,
A crystalline silicon film was obtained by heating for 8 hours. (Fig. 3 (D))

Next, a laser is irradiated in an oxidizing atmosphere to form a thin oxide film 401 together with laser annealing. (FIG. 4 (A)) This thin oxide film is formed by the adhesion between the crystalline silicon film and the resist or the adhesion between the crystalline silicon film and the etching stopper in the subsequent step of forming a resist or etching stopper. It plays the role of improving sex. However,
When laser irradiation is performed in an inert atmosphere, an oxide film is not formed.

Next, a silicon oxide film having a thickness of 120 nm is formed and patterned to form an etching stopper 118. Then, a doping mask 402 made of a resist is formed.
Note that as another material used for the etching stopper 118, an amorphous silicon film, a crystalline silicon film, a silicon nitride film, or a silicon oxynitride film can be used.

The first doping of phosphorus element was performed by a non-self-aligned process using the resist 402 as a mask. In this embodiment (FIG. 4 (B)), the N ⁺ -type region indicated by 403, 1 ×
Phosphorus was added at a concentration of 10 ²⁰ to 8 × 10 ²¹ atoms / cm ³ .

Thereafter, the resist mask 402 was removed, and a second doping of phosphorus element was performed using the etching stopper 118 as a mask. (FIG. 4C) In this example, the phosphorus concentration in the N ⁻ -type region indicated by 406 is adjusted to be 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ . Note that in the N-channel TFT, the N ⁺ type region 407 becomes a source region or a drain region, and the N ⁻ type region becomes a low concentration impurity region 406.

Next, the N-channel TFTs 203 and 204 are covered with a resist 501, and a P-channel TFT
Boron is added to the active layer to form a P-type region 502 in which phosphorus is present at a high concentration and a P-type region 503 in which phosphorus is present at a low concentration. (FIG. 5A) The boron dose is set so that the concentration of boron ions in the P-type region is about 1.3 to 2 times the concentration of phosphorus ions added to the N ⁺ -type region. In addition, the addition method of the phosphorus ion or boron ion in a present Example is
A known method such as an ion implantation method, a plasma doping method, a method of heating after applying a solution containing phosphorus ions or boron ions, a method of heating, a method of heating after forming a film containing phosphorus ions or boron ions, or the like is used.

The P-type regions 502 and 503 are a source region or a drain region of a P-channel TFT. In addition, a region where phosphorus ions and boron ions are not implanted becomes an intrinsic or substantially intrinsic channel formation region that later becomes a carrier movement path.

In this specification, intrinsic refers to a region that does not contain any impurities that can change the Fermi level of silicon, and the substantially intrinsic region is a balance between electrons and holes that offset the conductivity type. Region, that is, a concentration range (1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms in which threshold control is possible)
/ Cm ³ ) indicates a region containing an impurity imparting N-type or P-type, or a region in which the conductivity type is canceled by intentionally adding a reverse conductivity type impurity.

Next, heat treatment was performed in an inert atmosphere or a dry oxygen atmosphere at 450 ° C. or higher for 0.5 to 12 hours, and in this example at 550 ° C. for 2 hours. (Fig. 5 (B))

In the above heating step, Ni intentionally added for crystallization of the amorphous silicon film is changed into FIG.
) As shown schematically by the arrows in the figure, it diffuses from the channel formation region to the respective source and drain regions. This is because these regions contain a high concentration of phosphorus element, and Ni that has reached the source region and the drain region is captured (gettered) there. 40
Ni can be sufficiently gettered by heat treatment at 0 to 600 ° C. for 0.5 to 4 hours.

As a result, the Ni concentration in the channel formation region 110 can be reduced. The Ni concentration in the channel formation regions 107 to 110 is 5 × 10 ¹⁷ atoms / cm which is the SIMS detection lower limit.
Can be ³ or less. On the other hand, the Ni concentration in the source region and drain region used for the gettering sink is higher than that in the channel formation region. (Fig. 5 (C))

In addition to phosphorus, antimony or bismuth can be used as an impurity imparting N-type conductivity. Phosphorus has the highest gettering ability, followed by antimony.

In particular, a region 505 in which both phosphorus and boron are added so that the boron concentration is about 1.3 to 2 times that of phosphorus is a source region and a drain region 504 of an N-channel TFT to which only phosphorus is added.
Experiments have confirmed that the gettering ability is higher than that.

Furthermore, phosphorus and boron added to the source region, the drain region, and the low-concentration impurity region are activated simultaneously with the gettering by this heat treatment. Conventionally, since the heat resistance of the wiring material (aluminum) was low, only heat treatment at about 450 ° C. could be performed. In this embodiment, when the heating temperature is set to 500 ° C. or higher, the dopant can be sufficiently activated, and the resistance of the source region and the drain region can be further reduced only by the heat treatment.

Furthermore, the crystallinity of the region where the crystallinity is destroyed during the ion doping process is improved by this heat treatment.

That is, in the heat treatment in the oxidizing atmosphere of (FIG. 5B),
1) Gettering treatment for reducing the concentration of the catalyst element in the channel formation regions 107 to 110 2) Impurity activation treatment in the source and drain regions 111, 114, 504, and 505 3) Crystal structure damage caused during ion implantation An annealing process for recovering can be performed at the same time.

Moreover, it is good also as a process of performing light annealing by a laser beam, infrared light, or ultraviolet light before or after this heat treatment process.

  Next, the active layer is patterned into a desired shape to obtain the state shown in FIG.

Thereafter, in order to reduce the resistance of the high-concentration impurity region 111, a metal film for selective silicidation is formed on the active layer indicated by 111 and subjected to heat treatment. It is preferable to silicide the formed region. By adding this step, the resistance can be reduced and an operating frequency of several GHz level can be realized. As the metal film for silicidation, a film made of a material mainly containing cobalt, titanium, tantalum, tungsten, molybdenum, or the like can be used. For effective silicidation, it is preferable to remove the thin oxide films 115 to 117 on the high-concentration impurity region before forming the metal film. Further, the etching stopper 118 may be removed.

Then, a first interlayer insulating film 119 is formed on the entire surface of the substrate with a transparent organic resin film (acrylic resin). Here, the first interlayer insulating film 119 having a film thickness of 1 μm is formed by spin coating.
Form. When a transparent organic resin film such as an acrylic resin, polyimide, or BCB (benzocyclobutene) is used, the surface can be flattened as shown.
As another interlayer insulating film material, a silicon oxide film or a silicon oxynitride film can be used.

Then, contact holes are formed, and a metal film (not shown) for forming contact electrodes is formed. Here, as the metal film, a three-layer film of a titanium film, an aluminum film, and a titanium film is formed by a sputtering method. Then, by patterning the metal film (laminated film), electrodes and wirings indicated by 120 to 124 are formed.

Next, an organic resin film is formed as a second interlayer insulating film 125 to a thickness of 1 μm by spin coating. Then, in order to form an auxiliary capacitor, only a predetermined portion is etched and thinned. Then, a 300 nm thick metal film made of Ti was formed. Then, this metal film was patterned to form a black mask 126 and lead wirings 127 and 128.

Then, a third interlayer insulating film 129 is formed with an acrylic resin. Here, a third interlayer insulating film 129 having a thickness of 1 μm is formed by spin coating. When a resin film is used, the surface can be flattened as shown.

Next, contact holes are formed, and pixel electrodes 130 are formed. Here first IT
An O film is formed to a thickness of 100 nm by sputtering, and this is patterned to form a pixel electrode indicated by 130.

Finally, heat treatment is performed for 1 hour in a hydrogen atmosphere at 350 ° C. to reduce defects in the semiconductor layer. In this way, the state shown in FIG.

In this embodiment, the gate electrode of the pixel TFT 203 of the pixel matrix circuit has a double gate structure. However, a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off current. Further, a single gate structure may be used in order to improve the aperture ratio.

The TFT structure shown in this embodiment is an example of a bottom gate type (etching stopper type), and is not particularly limited to the structure of this embodiment. For example, a channel etch type TF is used.
There are T structures and the like. Further, although an example in which a transmissive LCD is manufactured is shown in this embodiment, only an example of a semiconductor device is shown. Note that a reflective LCD can be easily manufactured by configuring the pixel electrode with a highly reflective metal film instead of ITO and appropriately changing the patterning of the pixel electrode by the practitioner. Further, when a reflective LCD is manufactured, if a structure in which an insulating film is stacked on a heat-resistant metal film or a structure in which an insulating film is stacked on an aluminum nitride film is used as a base film, the metal film under the insulating film serves as a heat dissipation layer. Working and effective. The practitioner can change the above process order as appropriate.

In Example 1, patterning was performed in the process shown in FIG. 6A after the laser irradiation process, but in this example, patterning was performed before the laser irradiation process in FIG.
Shown in ~ 9. Since the basic configuration is substantially the same as that of the first embodiment, only the differences will be described.

Since this embodiment is the same up to the step of obtaining the crystalline semiconductor film shown in FIG. After obtaining the state shown in FIG. 3D, after patterning the desired shape,
Laser light is irradiated in an oxidizing atmosphere to obtain the state shown in FIG. As shown in FIG. 7A, the surfaces of the active layers 701 to 703 are covered with thin oxide films 704 to 706.

Subsequent steps are the same as in Example 1, high concentration phosphorus doping step (FIG. 7B), low concentration phosphorus doping step (FIG. 7C), boron doping step (FIG. 8A), getter. Ring process (
The state shown in FIG. 8C is obtained through FIG.

Next, the etching stopper 707 disposed above the channel formation region is removed to obtain the state of FIG. Here, the etching stopper 707 is removed, but it is not necessary to remove it.

Note that the thin oxide films 704 to 706 may be removed before, after, or simultaneously with this step. Further, it is preferable to add a step of silicidation by applying a heat treatment after removing the thin oxide film and selectively forming a metal film for silicidation on the high concentration impurity region. By doing so, it is possible to reduce the resistance of the source region and the drain region and realize an operating frequency of several GHz level. As the metal film for silicidation, a film made of a material mainly containing cobalt, titanium, tantalum, tungsten, molybdenum, or the like can be used.

Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted. In this way, the state of FIG. 9B was obtained. With such a configuration, the active layers 701 to 703 can be protected from diffusion of impurities from the interlayer insulating film by the thin oxide films 704 to 706.

In the first embodiment, the gate insulating film 1 of the CMOS circuit 202 constituting a part of the peripheral drive circuit section.
Although the thickness of the gate insulating film 106a of the pixel matrix circuit 201 is different from that of 06b, FIG. 10 shows an example in which the gate insulating film has the same thickness in this embodiment. Since the basic configuration is substantially the same as that of the first embodiment, only the differences will be described.

Since this embodiment is the same up to the step of forming the protective film shown in FIG. After obtaining the state of FIG. 3B in accordance with Embodiment 1, the gate insulation 1001 is continuously obtained.
An amorphous semiconductor film is formed. Thereafter, the active layer made of the crystalline semiconductor film is patterned through the same steps as in the first embodiment.

Then, remove the thin oxide film and etching stopper provided in contact with the active layer,
A metal film was selectively formed on the high-concentration impurity region, and then heat treatment was performed to form a silicide. In this way, the resistance of the source region and the drain region is reduced, and several GH
A z-level operating frequency can be realized. As the metal film for silicidation, a film made of a material mainly containing cobalt, titanium, tantalum, tungsten, molybdenum, or the like can be used. Thereafter, an interlayer insulating film 1002 made of a silicon oxide film was formed. Thereafter, the configuration shown in FIG. 10 is obtained through the same steps as in the first embodiment.

  This embodiment can be combined with the second embodiment.

This embodiment is an example in which a crystalline semiconductor film is obtained by a method different from that in Embodiment 1. This embodiment relates to a method for obtaining a crystalline semiconductor film by adding a catalytic element using a mask and performing heat treatment. Since the basic configuration is substantially the same as that of the first embodiment, only the differences will be described.

Since this embodiment is the same up to the step of forming the protective film shown in FIG. After obtaining the state of FIG. 3B according to Embodiment 1, an amorphous semiconductor film is formed, and then a mask made of a silicon oxide film is formed. The mask is provided with an opening. Next, the catalytic element (Ni) is held in the region provided with the opening using a nickel acetate salt solution.

Next, the amorphous semiconductor film is crystallized by heating (400 to 700 ° C.). At this time, crystal growth proceeds in a direction parallel to the substrate surface from the region where the opening is provided. This crystal growth is called lateral growth or lateral growth. Thereafter, the mask was removed. Good characteristics can be obtained by using the region crystallized by this lateral growth as a channel formation region of the TFT. By utilizing the present invention, a heat treatment at 400 ° C. or higher can be performed to obtain a crystalline semiconductor film. Thereafter, the same configuration as that of FIG. 1 can be obtained through the same steps as in the first embodiment (after FIG. 4A).

  It should be noted that this embodiment can be combined with other embodiments 2-3.

This embodiment is an example in which a crystalline semiconductor film is obtained by a method different from that in Embodiment 1. In this embodiment, a laser element is formed into a rectangle or a square by using a catalytic element that promotes crystallization of silicon, and uniform laser crystallization in a region of several cm ² to several hundred cm ² by one irradiation. The present invention relates to a method for obtaining a crystalline semiconductor film by treatment. Since the basic configuration is substantially the same as that of the first embodiment, only the differences will be described.

Since this embodiment is the same up to the step of holding the catalytic element on the surface of the amorphous silicon film shown in FIG. The Ni concentration of the Ni acetic acid solution in the step shown in FIG. In this example, it was set to 100 ppm. In this state, Ni is held on the surface of the amorphous silicon film. Next, excimer laser light (wavelength 248 to 308 nm) was irradiated in an inert or oxidizing atmosphere to obtain a crystalline silicon film.

In this embodiment, a laser beam shape with a wavelength of 248 nm is formed into a rectangle or a square,
A crystalline silicon film was obtained using a laser device (SAELC manufactured by Sopra) capable of irradiating a uniform laser beam on a region of several cm ² to several hundred cm ² by one irradiation. Thereafter, the same configuration as that of FIG. 1 can be obtained through the same steps as in the first embodiment (after the step shown in FIG. 4A).

It should be noted that this embodiment can be combined with other embodiments 2 to 4.

In this embodiment, a structure for obtaining a good ohmic contact in connection between wirings will be described with reference to FIG. Since the basic configuration of the pixel matrix circuit is almost the same as that of the first embodiment, only the differences will be described.

First, similarly to Example 1, a substrate having an insulating surface is prepared. Then, a base film (not shown) made of a silicon oxide film is formed. A layer made of a metal material over the layer 1101 containing tantalum as a main component, typically a layer 1102 containing titanium as a main component (thickness 20 nm to 100 nm).
nm) was continuously formed and patterned to provide a multilayer wiring. Thereafter, in the same manner as in Example 1, a gate insulating film was formed, an active layer was formed, an interlayer insulating film was formed, and a contact hole was formed.

This layer containing titanium as a main component prevents oxidation of the layer 1101 containing tantalum as a main component and occlusion of hydrogen when forming a contact hole (opening portion). In addition, the layer mainly composed of titanium is
When forming the opening portion, a part thereof may be removed at the same time as the interlayer insulating film, but a good ohmic contact can be obtained because it does not become an insulator even if it reacts with oxygen. That is, the layer containing titanium as a main component protects the layer containing tantalum as a main component and has a sufficient etching margin, so that it is easy to form an opening. Then, after forming the opening portion, the wiring 1103 was formed and connected to the multilayer wiring indicated by 1101 and 1102. Thereafter, the state of FIG. 11 was obtained in the same manner as in Example 1.

Further, instead of the layer mainly containing titanium, a layer mainly containing one kind of element selected from Cr, Mn, Co, Ni, Cu, Mo, and W can be used.

Unlike the configuration of Example 1, in this example, the etching stopper and the thin oxide film were removed. Moreover, it was set as the structure which does not form a protective film.

  Note that this embodiment can be combined with other embodiments 2 to 5.

AMLC using the TFT substrate (element formation side substrate) including the configuration shown in the above Examples 1 to 6
An example where D is configured will be described. Here, the appearance of the AMLCD of this embodiment is shown in FIG.

In FIG. 12A, reference numeral 1201 denotes a TFT substrate, on which a pixel matrix portion 1202, a source side driver circuit 1203, and a gate side driver circuit 1204 are formed. The pixel matrix portion corresponds to FIG. 2A and FIG. 1, and a part thereof is shown. In addition, the driver circuit is shown in FIG.
) And FIG. 1, and as shown in part, it is preferably constituted by a CMOS circuit in which an N-type TFT and a P-type TFT are combined in a complementary manner. Reference numeral 1205 denotes a counter substrate.

The AMLCD shown in FIG. 12A includes an active matrix substrate 1201 and a counter substrate 120.
5 are bonded together with the end faces aligned. However, only a part of the substrate 1205 is removed, and an FPC (flexible print
Circuit) 1206 is connected. The FPC 1206 transmits an external signal into the circuit.

Further, IC chips 1207 and 1208 are attached using a surface to which the FPC 1206 is attached. These IC chips are configured by forming various circuits on a silicon substrate, such as a video signal processing circuit, a timing pulse generation circuit, a γ correction circuit, a memory circuit, and an arithmetic circuit. Although two pieces are attached in FIG. 12A, one piece or a plurality of pieces may be used.

Further, a configuration as shown in FIG. 12B, the same portions as those in FIG. 12A are denoted by the same reference numerals. Here, an example is shown in which the signal processing performed by the IC chip in FIG. 12A is performed by a logic circuit (logic circuit) 1209 formed with TFTs on the same substrate. In this case, the logic circuit 1209 is also a driving circuit 1203, 1204.
Like the above, it is configured based on a CMOS circuit.

Further, color display may be performed using a color filter, or the liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like, and the color filter may not be used.

The AMLCD shown in Example 7 is used as a display of various electronic devices. Note that the electronic device described in this embodiment is defined as a semiconductor device including a semiconductor circuit.

Examples of such an electronic device include a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, etc.). . An example of them is shown in FIG.

FIG. 13A illustrates a mobile computer (mobile computer).
The camera unit 2002 includes an image receiving unit 2003, an operation switch 2004, and a display device 2005. The present invention can be applied to the image receiving unit 2003, the display device 2005, and the like.

FIG. 13B illustrates a head mounted display, which includes a main body 2101 and a display device 2102.
, And a band unit 2103. The present invention can be applied to the display device 2102.

FIG. 13C illustrates a mobile phone, which includes a main body 2201, an audio output unit 2202, and an audio input unit 22.
03, a display device 2204, an operation switch 2205, and an antenna 2206. The present invention can be applied to the audio output unit 2202, the audio input unit 2203, the display device 2204, and the like.

FIG. 13D illustrates a video camera, which includes a main body 2301, a display device 2302, and an audio input unit 2.
303, an operation switch 2304, a battery 2305, and an image receiving unit 2306. The present invention can be applied to the display device 2302, the audio input unit 2303, and the image receiving unit 2306.

FIG. 13E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.

FIG. 13F illustrates a portable book which includes a main body 2501, display devices 2502 and 2503, a storage medium 2504, operation switches 2505, and an antenna 2506. Storage media (MD,
Data stored on a DVD or the like or data obtained from an antenna (such as a satellite antenna) is displayed. The present invention can be applied to the display devices 2502 and 2503.

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In addition, it can also be used for electric billboards, advertising announcement displays, and the like.

100 Substrate 101, 102 Gate wiring or electrode (pixel matrix circuit)
103 Gate wiring or electrode (N-channel TFT of CMOS circuit)
104 Gate wiring or electrode (P-channel TFT of CMOS circuit)
105 Protective film 106 Gate insulating films 107 to 110 Channel formation region 111 High concentration impurity region 112 Low concentration impurity region 113 High concentration impurity region (N-channel TFT)
114 Low-concentration impurity region (P-channel TFT)
115 to 117 Oxide film 118 Etching stopper 119 First interlayer insulating film 120 to 124 Wiring 125 Second interlayer insulating film 126 Black mask 127 and 128 Lead wiring 129 Third interlayer insulating film 130 Pixel electrode

Claims (3)

On a substrate having an insulating surface,
A gate electrode having a multilayer structure;
A protective film covering the substrate and the upper and side surfaces of the gate electrode;
A gate insulating film formed to cover the protective film;
A source region, a drain region, and a channel formation region formed between the source region and the drain region in contact with the gate insulating film;
A liquid crystal display device comprising a semiconductor circuit made of a semiconductor element having the above.   An electronic apparatus using the liquid crystal display device according to claim 1.   3. The electronic device according to claim 2, wherein the electronic device is a video camera, a still camera, a projector, a head mounted display, a car navigation, a personal computer, a portable information terminal, a mobile computer, a mobile phone, or a portable book. .

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