TW200416990A - Stacked flip-chip package processing - Google Patents

Abstract

A stacked flip-chip package processing is provided. The bump processing is formed on the surface of the wafer, in which first bumps is formed on the first contracts. In addition, a second chip is mounted on the wafer by the means of flip-chip bonding, and the die pads of the second chip are connected to the second contracts through the second bumps. After the wafer is sawed into a plurality of first chips, the first chip stacks with the second chip and mounts on a carrier together to promote the density of the stacked chip package and to reduce the space required. Moreover, the first chip and the second chip shorten transmission lines and work in higher speed and multi-function is provided.

Description

200416990 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a flip chip packaging process, and more particularly to a stacked flip chip packaging process. [Previous technology] The production of 'Integrated Circuits (IC)' in the half-body industry is mainly divided into three stages: wafer (wa fer) manufacturing, integrated circuit (ic) manufacturing, and integrated circuit (IC) Packages, etc. Among them, the “bare wafer (d 1 e)” is completed through the steps of wafer fabrication, circuit design, photomask multiple processes, and wafer dicing, and each bare wafer formed by wafer dicing is passed through the bare wafer. The Bonding Pad is electrically connected to the carrier. The carrier is, for example, a packaging substrate (Substrate) or a printed circuit board (PCB). In order to connect the above chip and the carrier, wires (Wire) and / or bumps (Bump) are usually used as the bonding. Media to form a chip package structure. Among them, the flip chip bonding technology (FI ip Chip Interconnect Technology) is to form bumps on the wafer in an area array arrangement, and then dry the wafer, and then use the bumps on the wafer to separate Corresponding to the contacts connected to the device, the chip can be electrically and mechanically connected to the carrier through the bumps, and then connected through the internal circuit and surface of the carrier = circuit connections, such as motherboards. / 、 With the increase of the degree of accumulation of the wafer, the more diverse the seals of the wafer, the more the use of the above-mentioned flip-chip bonding technology ^ ^ Into the heart and the sun and the moon and the package. Reduced chip package area and shortened signal transmission path

200416990 V. Description of the invention (2) Don't already be widely used in the field of chip packaging, such as Chip Scale Package (CSP), Flip Chip / Ball Grid Array (FC / BGA), and more Multi-Chip Module (MCM) and other types of package modules are all applications of flip-chip bonding technology. Among them, the multi-chip module package refers to the construction of several wafers on the same carrier using flip-chip bonding technology, and the chips are electrically connected to each other through the carrier to form a multi-chip = The flip chip package structure. The memory multichip chip reduces the space to achieve and carry the structure 'accumulation degree. Signal transmission [Invention due to manufacturing process, chip and purpose. For example, dynamic random access memory (dynamic randQm aeeess 'dram) and logic circuit (loglc circuU), multiple DRAM chips and logic circuits can be placed on the same carrier using the MCM package type.' In this way, not only the structure density is increased, the demand is reduced, but also the phenomenon of signal delay between the package modules is reduced. Therefore, it is widely used in communication 1Γ! 0 ^ 7. It should be noted that, for various flip-chip packaging structures, how to make t # 二 ： sexual chip packaging products and shorten the path between the wafer and the wafer is based on The focus of the invention. Content]…: The process of providing flip-chip packaging on the surface of a stacked 2-crystal wafer is described in this article. ^ The signal transmission path between the wafers can be achieved, and multi-chip sealing can be achieved. The above object of the invention The present invention proposes a stacked flip chip

200416990 V. Description of the invention (3) For the packaging process, a wafer is first provided, and the wafer has multiple first wafers, and each first wafer has multiple first contacts and multiple second contacts, and the first The contact is electrically connected to the second contact. A plurality of bumps are then disposed on these first contacts. A plurality of second wafers are provided, each of which has a plurality of solder pads corresponding to the second contacts, and a surface of the solder pads is respectively provided with a first bump, and then a flip-chip step is performed. A bump is connected to each second contact and one of the corresponding solder pads. Finally, re-soldering is performed and the wafer is cut to separate the first wafers independently. According to a preferred embodiment of the present invention, after the wafer is diced, the diced dies are arranged on a carrier, and the carrier has a plurality of bonding pads respectively corresponding to the first contacts, and These first contacts and corresponding bonding pads are respectively connected by a second bump. In addition, an underfill process is performed to fill a primer between the substrate, the wafer and the first wafer, and the primer further covers the bumps and bumps. In the present invention, a bump process is performed on the surface of an uncut wafer, and a cut wafer is arranged on the surface of the wafer to form a stacked flip-chip packaging structure. The wafers are directly stacked on the surface of the wafer and are electrically connected to each other by bumps, so the signal transmission path between the wafer and the wafer can be shortened, and the purpose of multi-chip packaging can be achieved. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Embodiment] The first 1 ~ 1 The figure illustrates a stacked type of the first embodiment of the present invention in sequence.

10551 t.wf. ptd Page 7 200416990 V. Description of the invention (4) Schematic diagram of the flip-chip packaging process. Please refer to FIG. 1A first. First, a wafer 100 is provided. The surface of the wafer 100 can be roughly divided into a plurality of square-shaped first wafers 1 1 0 (refer to FIG. 2), and the wafer 1 〇 〇 After the internal integrated circuit passes multiple semiconductor processes, a plurality of first contacts 1 1 2 and a plurality of second contacts 1 1 4 are finally formed on the first wafer 丨 丨 0, among which the contacts 1 1 2 1 1 4 is the medium for signal input and output. It is worth noting that these contacts 丨 2 and Π 4 are arranged on the first chip 丨 丨 in the form of a surface array, for example, as chip contacts 1 1 2 (ie, the first contacts) of a flip-chip package or The bump contacts 1 1 4 (ie, the second contacts), and the chip contacts 1 1 2 and the bump contacts 1 1 4 are electrically connected to each other. Next, referring to FIG. 1B, a bump process is performed on the surface of the wafer 100, and a plurality of bumps 120 (that is, the first bumps) are separately formed on each surface by screen printing. A bump contact 丨 14, and the material of the bump 120 may be a tin-lead alloy. Among them, the bump bottom metal layer 116 'has been formed on the bump contacts 1 14 respectively, and the bump bottom metal layer 116 is used to position the bumps 120 on the bump contacts 14. In a better case, the bump contacts 114 are distributed on the area around the first wafer Π 0, and a screen plate (not shown) is used to cover the wafer contacts 1 1 2 on the wafer 100 first. Hold and expose only the bump contact 1 1 4, and then apply solder paste (s ο 1 derpaste) to the screen by printing, and on each bump contact 丨 丨 4 respectively Forming a bump 120. Of course, in addition to screen printing, the bumps 120 can also be formed on the bump contacts 1 1 4 in an electroplating manner, which uses a photolithography process such as exposure and development to form a photoresist (not shown). On the surface of the wafer, a pattern is transferred to the photoresist, so that the photoresist forms a plurality of photoresist openings.

200416990 V. Description of the invention (5) The resistance opening only exposes the bump contacts 1 1 4 and then the electric ore tin-lead alloy is used to form the bumps 1 2 0 on each bump contact π 4 and finally Photoresist removal. In addition, the bumps 1 2 0 may be formed by a ball-planting method. Next, please refer to FIGS. 1C and 1D to provide a plurality of second wafers 13o, and the second wafer 130 is formed by cutting another wafer, and the surface of the second wafer 130 has a plurality of pads. (Bonding pad) 132, respectively corresponding to the wafer contacts 1 12 of the wafer 100, and the surface of the solder pad 132 is formed with a bump bottom metal layer 136, for example, and then a bump 134 ( That is, the second bump is on the bump and the metal layer 136. Then, a flip-chip step is performed, and each of the wafer contacts 1 1 2 and one of the corresponding solder pads 32 are connected to each other through the bump 134. Wherein, the bump 1 = 4 is, for example, a solder paste or a tin-lead alloy. In the best case, the first chip! For example, it is a logic circuit chip, which has high-density pads arranged in an area array. When the second wafer 130 is formed on the wafer 100 in a StaCked manner, the second wafer 130 is directly connected to the wafer 100 and the second wafer 130 is connected to the wafer 100. The signal transmission path between the wafers 1 is relatively shortened. In addition, since the second chip ^ \ 30 can be used as a dynamic random access memory (DRAM) chip, and the first chip of the port has a logic operation function, it provides the best work between the two, and uses The stacking method can increase the structure density, reduce the space 2 ′, and reduce the signal delay between the second wafer 130 and the wafer 1000, so that the purpose of high-speed processing is achieved. The vintage " month refers to Figure 1E, reflow (ref 1 〇w), so that the bump idfi t ^ ^ fused into a sphere in the state, and the second wafer 130 and the wafer, the bump 1 34. After reflow, the second wafer is also made.

200416990 V. Description of the invention (6) A good bonding effect is formed between the 30 and the wafer 100. It is worth noting that the main components of the first and second wafers 130 and 100 are silicon, so the thermal expansion coefficients of the two are the same, so the bump 134 will not be affected by the second wafer 13 and the wafer 1. The thermal expansion coefficient is different from 0 to cause fatigue strain of thermal strain. In this way, the distance between the second wafer 130 and the wafer 〇〇 (st and 〇ff) can be reduced, thereby shortening the pad of the second wafer 1300 and the distance between the wafers 2 or the wafer 100 The pitch of the chip contacts 112 is increased to increase the number of contacts of the flip-chip package. On the other hand, after the bumps 120 are melted into a sphere, in order to maintain the height of the bumps 120, a distance (standoff) required for subsequent subsequent wafers to be packaged on the carrier is provided. In a better case, by using the large-area bump contact 1 1 4, the spherical bump 1 2 0 can have a larger outer diameter to maintain the height of the bump 120. The area of the wafer contact 112 is smaller than the area of the bump contact 1 1 4. ^ Referring to Figures 1? And 16, the wafer 100 is cut to separate the crystal wafer 1. The wafer 110 'and the wafer 100 are cut in a wafer and then placed on a carrier in the form of a flip chip (1P ChlP). On the device 200, and the load is 200 ^ = the package substrate (substrate) or 22 contacts on a printed circuit board; 14 ° has a plurality of bonding pads 202, corresponding to each bump connection, respectively, 1 wafer after chip-on-chip 'is connected to the mother-bump contact 114 and the corresponding bonding pad 202 by bump 120, respectively, and the chip sealer is connected to 4, and the fetching i-type cover; cry 2 η Λ refinishes these bumps 120 so that the wafer 100 and the wafer 2 = good bonding effect. If 1 ", the second chip 13. The signal of the and Ba film 110 can be transmitted to the contractor 9ηη through the bump 120, and then transmitted through the contacts and internal circuits of the carrier 2 0 0 ...

200416990 V. Description of Invention (7) To external electronic device. In addition, as shown in the first figure, in order to protect the bump 120 from being damaged by the thermal stress L due to the difference in thermal expansion coefficient between the first wafer 110 and the carrier 2000, it can be finally performed. An underfill process, in which a primer 2 such as epoxy resin is filled between the carrier 200, the second wafer 130 and the first wafer 110. In the space, the primer 20 can completely cover the bump 120 and the bump 134 to buffer the thermal strain between the first wafer Π 0 and the carrier 2000. In the above-mentioned embodiments of the first F, 1 G, and 1 drawings, the wafer 100 is notched J first, and then the independently separated first wafer 1 1 10 is encapsulated in a flip chip package 20 0 Finally, an underfill process is performed to form a stacked flip-chip package structure. However, in another embodiment of the present invention, the carrier 200 may be first packaged on the wafer 100 and re-soldered. The bump 120 is connected to the bonding pad 202 and the wafer of the carrier 200. The bump contact 114 of the circle 100 is cut, and then the wafer 100 and the carrier 200 are cut to separate the carrier 200 and the first wafer 1 of the wafer 100 separately. Finally, a bottom is performed. In a stacked-chip flip chip package. Furthermore, as shown in FIG. 2 / embodiment, a plurality of second wafers 13 are arranged in a single wafer:. The process on the wafer 110 is as described in the first embodiment, so it is no longer necessary to understand from the above description. The process of this process is to electroplate tin-lead alloy or screen printing on the surface of the uncut wafer. . Next, a bump process is performed on the stacked flip-chip package that has been revealed and disclosed in a flip-chip manner, wherein a second wafer formed in each bump contact manner is directly packaged on the wafer.

10551 t.wf, ptd page 11 200416990 V. Description of the invention (8) On the surface of a circle, and the pads of the second chip are connected to the chip contacts by bumps. Among them, the second chip is, for example, a dynamic random access memory (DRAM) chip, and the first chip of the wafer can be used as a logic circuit chip. The signal transmission path between the two is shortened, so the speed of chip operation can be increased. In addition, after the wafer is diced, it is arranged on a carrier in a flip-chip manner to form a stacked flip-chip package structure. Since the first chip and the second chip are packaged on the same carrier, and the two are connected to each other in a stacked manner, the flip chip structure density can be increased, space requirements can be reduced, and the signal delay between the chip and the wafer can be reduced. Phenomenon, it can achieve the purpose of high-speed wafer processing and product multiplexing. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10551 t.wf. ptd Page 12 200416990 Brief description of the drawings 1 A ~ 1 Figure 1 shows a schematic flow chart of a stacked flip-chip packaging process according to the first embodiment of the present invention in sequence. FIG. 2 is a schematic top view of a stacked flip-chip package according to a second embodiment of the present invention. [Schematic symbols do not explain] 100 wafers 110 di wafers 1 12 wafer contacts (first contacts) 114 bump contacts (second contacts) 116 bump bottom metal layer 120 first block 130 two wafers 132 Welding pad 134 Second bump 136 Metal layer of bump bottom 200 Carrier 202 Bonding pad 210 Primer

10551 twf. Pt.d Page 13

Claims (1)

200416990 VI. Scope of patent application 1 · A stacked flip-chip packaging process at least includes: a. Provide a wafer with a plurality of first wafers, and each of these μ slices has a plurality of first contacts and a plurality of The second contact, complex 5 = = 21 contacts are electrically connected to the second contacts; /, τ configures a plurality of first bumps on the first contacts; provides a plurality of chips Each of these wafers has a plurality of bonding pads, eight corresponding to the second contacts, and the surfaces of the bonding pads are divided into two or two bumps; The block is convex second; by one, it is welded and stepped by crystal; the cover of welded one should go back to the advancing and adjoining tabs, then the crystals are connected one by h and the lambda t The number t is filled with some P compound crystals, and the P has an open account with the bottom of the account holder and the account \ points 1, the point 2 will be. The vertical device is connected to the first, and the independent wafer carrier I is produced in accordance with the standard and the standard. The first and some special wafers are provided for the point. The bottom is a crystal. Please refer to the first application. Include \ Even apply some cuts such as the first, the second, the other 2. The more, the more, the block, the film process in the convex Cheng Jing packaged crystal cover / should be divided. , By the pad by the joint to make a packaged crystal-covered stacker view) ^ 1 Cheng should be entered into some Hai = ° Cheng point system U block f M f this t one two the crystal-crystal, coating-coating α Some formulas 4 formulas d helical stacks " v «d _ and _ formulas > blocks > Fang Zhiqiaozhi's ^ # β \ 0 According to the household electrical items, 3 J 1 i Department of enclosing enclosing block Fan Baofan Conley is more profitable. Please ask for some applications, such as 4 and 5 ♦. Continue to 200416990 6. Scope of patent application ___ 6 · As described in item 1 of the scope of patent application, the process is as follows, in which the first line is used to enclose a contact on a daily basis.丨 Other types are formed in these first stacked flip-chip packaging processes, including at least: providing a wafer having a plurality of first wafers having a plurality of first contacts and a plurality of second contact mothers-the Some-= put a plurality of first bumps on the first contacts; provide a plurality of wafers, each of which should correspond to the first-garden film * there are a plurality of recording pads, divided into two Bumps; brother-contacts' and the surfaces of the pads are respectively provided with a first step of flip-chip, each second contact is connected to one of the pads by the second bump; * These two brothers are to be re-welded; provide a carrier with a plurality of bonding pads, go to the first pile, * #, ^ ^ 1 ^ The knife does not correspond to this ", and the first bumps are wrong Connect the first contacts: the corresponding bonding pads respectively. The contacts and the first Π wafer and the carrier to separate the carrier and the 8 independently, as described in item 7 of Shenyan's patent scope The stacked flip-chip package includes: an underfill process, in which a primer is filled in the carrier wafer and the first wafers In between. 9. The stacked flip-chip packaging process described in item 8 of the scope of patent application, wherein the primer further covers the first bumps and the second bump garments. 1 〇 · Stacked flip-chip encapsulation as described in patent application scope item 7 200416990 6. The scope of patent application, wherein the first bumps are formed on the first contacts by electroplating. 1 1 · The stacked flip-chip packaging process described in item 7 of the scope of patent application, wherein the second bumps are formed on the first contacts by screen printing. 10551 t.wf. ptd Page 16