TW587326B - Stacked flip-chip package processing - Google Patents
Stacked flip-chip package processing Download PDFInfo
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- TW587326B TW587326B TW92103360A TW92103360A TW587326B TW 587326 B TW587326 B TW 587326B TW 92103360 A TW92103360 A TW 92103360A TW 92103360 A TW92103360 A TW 92103360A TW 587326 B TW587326 B TW 587326B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
Description
587326587326
【發明所屬之技術領域】 且特別是有關於 本發明是有關於一種覆晶铲萝 一種堆疊式(Stacked)覆晶封裳製程' 【先前技術】 在半導體產業中’積體電路(Integrated circuits, I c )的生產,主要分為三個階段:晶圓(^㊀㈠的製造、積 ,電路(1C)的製作以及積體電路(IC)的封裝(Package) 等。其中’裸晶片(d i e)係經由晶圓製作、電路設計、光 罩夕道製程以及切割晶圓等步驟而完成,而每一顆由晶圓 切割所形成的裸晶片,經由裸晶片上之焊墊(B〇nd Pad)與承載器(Carrier)電性連接。承載器例如為一封裝 基板(Substrate)或一印刷電路板(Printed circuit Board,PCB),為了連接上述之晶片和承載器,通常會使 用導線(Wire)及/或凸塊(Bump)作為接合之媒介,以構成 一晶片封裝(Chip Package)結構。其中,覆晶接合技術 (Flip Chip Interconnect Techno 1 〇gy)即是在晶片之鲜 墊上以面陣列(Area array)排列的方式形成凸塊,接著再 將晶片翻覆之後,利用晶片上之凸塊分別對應連接至承載 器上的接點,使得晶片可經由凸塊而電性以及機械性連接 至承載器,再經由承載器之内部線路及表面之接點而與外 部電路連接,如主機板等。 隨著晶片的積集度的增加,晶片的封裝結構也是越 來越多樣化,利用上述的覆晶接合技術之晶片封裝結構, 其具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點,目[Technical field to which the invention belongs] In particular, the present invention relates to a flip chip shovel and a stacked flip chip process [Previous technology] In the semiconductor industry, "Integrated circuits, The production of I c) is mainly divided into three stages: the manufacture and fabrication of wafers, the fabrication of circuits (1C), and the packaging of integrated circuits (ICs). It is completed through the steps of wafer fabrication, circuit design, photomask process, and wafer dicing. Each bare wafer formed by wafer dicing is passed through a bond pad on the bare wafer. The carrier is electrically connected to the carrier. The carrier is, for example, a substrate or a printed circuit board (PCB). In order to connect the above chip and the carrier, wires and wires are usually used. Bumps are used as a bonding medium to form a chip package structure. Among them, Flip Chip Interconnect Techno 1 0gy is the surface on the fresh pad of the wafer. The bumps are arranged in an area array, and then the wafer is flipped over, and the bumps on the wafer are respectively connected to the contacts on the carrier, so that the wafer can be electrically and mechanically connected to the wafer via the bumps. The carrier is then connected to external circuits, such as the motherboard, via the internal circuit and surface contacts of the carrier. With the increase in the degree of accumulation of the chip, the package structure of the chip is becoming more and more diverse. The chip packaging structure of flip-chip bonding technology has the advantages of reducing the chip packaging area and shortening the signal transmission path.
10551twf.ptd 第5頁 587326 五、發明說明(2) 前已經廣泛應用於晶片封裝領域’例如晶片尺寸封裝 (Chip Scale Package, CSP)、覆晶/球格陣列封裝(Flip Chip/Bal 1 Grid Array, FC/BGA)以及多晶片模組封裝 (Mu 11 i -Ch i p Modu 1 e, MCM )等型態的封裝模組,均是覆晶 接合技術所應用的範疇。其中,多晶片模組封裝係指將數 個晶片以覆晶接合技術構裝在同一承載器上,且這些晶片 之間藉由承載器而彼此電性連接,以構成一具有多工性之 覆晶封裝結構。 以 memory 多晶片 路晶片 減少空 以達到 及攜帶 結構, 積集度 訊號傳 【發明 動態隨機存取記憶體(dynamic rand()m aeeess ,DRAM)以及邏輯電路(1〇gic circuit)為例,利用 模組封裴(MCM)型態可將多個卯錢晶片以及 封裝在同一個承載哭卜,士+ > Η兩東,★降# 如此不僅提南構裝密度、 :;之門ί了封裝模組之間訊號延遲的現象, 目日片之間呵速處理的目的,因 式電子產品中。值彳^立& a μ t极應用在通訊 ^ a ^ 值仔〆主思的是,針對各種覆S封牡 特別是多晶片封裝之瑨曰#壯π j 徑復日日封裝 復日日封衣、、、口構’如何;作屮古 *多:性的晶片封裳產品,並: 遞的路徑,乃為本發明之重點。 一阳片之間 内容】 个货啊的目的就是在 製程,係在一晶圓之表面上 _ 豐式覆晶封裝 曰曰片”日日圓之間訊號傳遞的路縮短 目的。 運到多晶片封裝的 為達本發明之上述目的 本發明提出一 種堆疊式覆晶10551twf.ptd Page 5 587326 V. Description of the Invention (2) It has been widely used in the chip packaging field before, such as Chip Scale Package (CSP), Flip Chip / Bal 1 Grid Array , FC / BGA) and multi-chip module package (Mu 11 i -Ch ip Modu 1 e, MCM) and other types of package modules, are the scope of flip chip bonding technology. Among them, the multi-chip module package refers to the construction of several wafers on the same carrier by flip-chip bonding technology, and the wafers are electrically connected to each other through the carrier to form a multi-layered overlay. Crystal package structure. Take the memory multi-chip circuit chip to reduce the space to achieve and carry the structure, the accumulation degree signal [invention of dynamic random access memory (dynamic rand (meaeeess, DRAM), and logic circuit (10gic circuit) as an example, using Modular sealing (MCM) type can be used to store multiple money-saving chips and packages on the same carrying cry. + +> Η 两 东 , ★ 降 # This not only raises the density of the south structure, the door of the; The phenomenon of signal delay between packaging modules, for the purpose of quick processing between Japanese and Japanese films, is in factor electronic products.彳 ^ 立 & a μ t pole is applied in communication ^ a ^ Value Tsai's main idea is that for a variety of S packages, especially multi-chip packages, # 瑨 π j jday after day packaging day after day How to seal clothes, mouths, mouths, and mouthpieces; make the ancient and many more: sexually sealed wafer products, and: The path of delivery is the focus of this invention. The contents of a single wafer] The purpose of the goods is to tie the surface of a wafer in the manufacturing process. In order to achieve the above object of the present invention, the present invention proposes a stacked flip chip
587326 五、發明說明(3) 封裝製程,首先提供一晶圓,晶圓具有多個第一晶片,而 每一第一晶片具有多個第一接點及多個第二接點,且第一 接點係電性連接於第二接點。接著配置多個凸塊於這些第 一接點上。提供多個第二晶片,每一第二晶片具有多個銲 墊,分別對應於第二接點,且這些銲墊之表面分別配置一 第一凸塊,接著進行一覆晶步驟,藉由第一凸塊連接每一 第二接點及對應之銲墊之一。最後進行迴銲,並切割晶 圓,以獨立分開這些第一晶片。 依照本發明的較佳實施例所述,上述於切割晶圓之 後,又將切割後之晶粒配置於一承載器上,承載器具有多 個接合墊,分別對應於這些第一接點,且藉由第二凸塊分 別連接這些第一接點及對應之這些接合墊。此外,再進行 一底填製程,將一底膠填入於基板、晶片及第一晶片之 間,且底膠更包覆凸塊及凸塊。 本發明係在未切割之晶圓的表面上進行凸塊製程,並 配置一已切割之晶片於晶圓之表面上,以形成一堆疊式覆 晶封裝結構。其中晶片係直接堆疊於晶圓之表面,且藉由 凸塊而彼此電性連接,因此可縮短晶片與晶圓之間的訊號 傳遞路徑,並可達到多晶片封裝的目的。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 【實施方式】 第1 A〜1 Η圖依序繪示本發明第一實施例之一種堆疊式587326 V. Description of the invention (3) In the packaging process, a wafer is first provided, and the wafer has multiple first wafers, and each first wafer has multiple first contacts and multiple second contacts, and the first The contact is electrically connected to the second contact. A plurality of bumps are then disposed on these first contacts. A plurality of second wafers are provided, each of which has a plurality of solder pads corresponding to the second contacts, and a surface of the solder pads is respectively provided with a first bump, and then a flip-chip step is performed. A bump is connected to each second contact and one of the corresponding solder pads. Finally, re-soldering is performed and the wafer is cut to separate the first wafers independently. According to a preferred embodiment of the present invention, after the wafer is diced, the diced dies are arranged on a carrier, and the carrier has a plurality of bonding pads respectively corresponding to the first contacts, and These first contacts and corresponding bonding pads are respectively connected by a second bump. In addition, an underfill process is performed to fill a primer between the substrate, the wafer and the first wafer, and the primer further covers the bumps and bumps. In the present invention, a bump process is performed on the surface of an uncut wafer, and a cut wafer is arranged on the surface of the wafer to form a stacked flip-chip packaging structure. The wafers are directly stacked on the surface of the wafer and are electrically connected to each other by bumps, so the signal transmission path between the wafer and the wafer can be shortened, and the purpose of multi-chip packaging can be achieved. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Embodiment] The first 1 ~ 1 The figure illustrates a stacked type of the first embodiment of the present invention in sequence.
10551twf.prd 第7頁 587326 五、發明說明(4) 覆晶封裝製程的流程示意圖。請先參考第1 A圖,首先提供 一晶圓1 0 0,晶圓1 0 0之表面大致上可區分為多個方格狀之 第一晶片110(請參考第2圖),而晶圓1〇〇内部之積體電路 經由多道半導體製程之後,最後在第一晶片丨丨〇上形成多 個第一接點1 1 2及多個第二接點1 1 4,其中接點}丨2、丨丨4係 作為δίΐ 5虎輸出入之媒介。值得注意的是,這此接點1 1 2、 1 1 4例如以面陣列的方式排列於第一晶片丨丨〇上,以作為覆 晶封裝之晶片接點Π 2 (即第一接點)或凸塊接點丨丨4 (即第 二接點)’且晶片接點1 1 2係與凸塊接點1 1 4彼此電性連 接。 接著凊參考第1B圖’在晶圓1〇〇之表面上進行凸塊製 权’將多個凸塊1 2 0 (即第一凸塊)以網版印刷(s c r e e η print ing)的方式分別形成於每一凸塊接點丨丨4上,而凸塊 1 2 0之材質可為錫鉛合金。其中,凸塊接點丨丨4上已分別形 成一凸塊底金屬層116,藉由凸塊底金屬層116以使凸塊 1 2 0疋位於凸塊接點1丨4上。在較佳情況下凸塊接點工工4 且利用 係刀佈於第一晶片Η 〇周圍的區域上,且利用一網版(禾多會 不)先將晶圓1 〇〇上之晶片接點丨丨2覆蓋住,並僅暴露出凸 塊接點114,之後再將錫膏(s〇lder paste)以印刷的方式 ^佈於^1版中,且在每—凸塊接點114上分別形成凸塊 田然,除了網版印刷之外,凸塊1 2 0亦可以電鍍的方 =二別形成於凸塊接點丨丨4上,其利用曝光、顯影等微影 二桎’先形成一光阻(未繪示)於晶圓丨〇 〇表面上,接著將 一圖案轉印至光阻上,以使光阻形成多個光阻開口 ,而光10551twf.prd Page 7 587326 V. Description of the invention (4) Schematic diagram of the flip-chip packaging process. Please refer to FIG. 1A first. First, a wafer 100 is provided. The surface of the wafer 100 can be roughly divided into a plurality of square-shaped first wafers 110 (refer to FIG. 2). After the internal integrated circuit of 100 has passed through a plurality of semiconductor processes, a plurality of first contacts 1 12 and a plurality of second contacts 1 1 4 are finally formed on the first wafer 丨 丨, among which the contacts} 丨2. 丨 丨 4 is the medium of δίΐ 5 tigers input and output. It is worth noting that these contacts 1 1 2, 1 1 4 are arranged on the first chip 丨 丨 0, for example, in a surface array manner, as chip contacts Π 2 (ie, first contacts) of a flip-chip package. Or bump contacts 丨 4 (ie, second contacts) 'and the chip contacts 1 1 2 and the bump contacts 1 1 4 are electrically connected to each other. Then, referring to FIG. 1B, “performing bumps on the surface of the wafer 100”, a plurality of bumps 120 (that is, the first bumps) are screen-printed (scree η print ing) respectively. It is formed on each bump contact 丨 丨 4, and the material of the bump 120 can be a tin-lead alloy. A bump bottom metal layer 116 has been formed on each of the bump contacts 丨 4. The bump bottom metal layer 116 is used to position the bumps 1 2 0 上 on the bump contacts 1 丨 4. In a better case, the bump contact worker 4 uses a knife cloth on the area around the first wafer 〇 〇, and uses a screen (Hedo will not) to first connect the wafer on the wafer 100 Point 丨 丨 2 covers and exposes only bump contact 114, and then solder paste is printed on the ^ 1 version in a printed manner, and on each bump contact 114 Bumps Tian Ran are formed separately. In addition to screen printing, the bumps 1 2 0 can also be plated. = The two are formed on the bump contacts 丨 丨 4, which uses lithography such as exposure and development. A photoresist (not shown) is formed on the wafer surface, and then a pattern is transferred to the photoresist, so that the photoresist forms a plurality of photoresist openings, and the photoresist
587326 五、發明說明(5) 阻開口僅暴露出凸塊接點丨丨4,之後再利用電鍍錫鉛合金 以形成凸塊1 2 〇於每一凸塊接點1 1 4上,最後再將光阻去 除。另外,亦可以植球方式形成凸塊丨2 〇。 接著請參考第1C及1D圖,提供多個第二晶片130,而 第二晶片1 3 0係由切割另一晶圓所形成的,且第二晶片1 3 〇 之表面具有多個鮮墊(bonding pad)132,分別對應於晶圓 1 〇 〇之晶片接點1 1 2,且銲墊丨3 2之表面例如先形成一凸塊 底金屬層1 3 6,之後再分別配置一凸塊1 34 (即第二凸塊)於 凸塊底金屬層136上。接著進行一覆晶步驟,藉由凸塊134 連接母 曰曰片接點1 1 2及對應之録塾1 3 2之一。其中,凸塊 例如為一錫膏(solder paste)或一錫鉛合金。在較佳 U况下’第一晶片丨丨〇例如為邏輯電路晶片,其具有高密 度且面陣列排列之銲墊1 1 2。當第二晶片1 3 0以覆晶堆疊 (stacked)的方式形成於晶圓1〇〇上時,第二晶片13〇係直 接電性與機械性連接於晶圓1 0 0,因此第二晶片1 3 0與晶圓 1 〇 〇之間的訊號傳遞路徑相對地縮短。此外,由於第二晶 5 U〇係可作為動態隨機存取記憶體(DRAM)晶片之用,且 =圓100之第一晶片具有邏輯運算功能,兩者之間提供不587326 V. Description of the invention (5) The resistance opening only exposes the bump contacts 丨 丨 4 and then the electroplated tin-lead alloy is used to form bumps 1 2 0 on each bump contact 1 1 4 and finally Photoresist removal. In addition, bumps can also be formed in a ball-planting manner. Then please refer to FIGS. 1C and 1D to provide a plurality of second wafers 130. The second wafer 130 is formed by cutting another wafer, and the surface of the second wafer 130 has a plurality of fresh pads ( Bonding pad) 132, respectively corresponding to wafer contacts 1 1 2 of wafer 1000, and the surface of the solder pads 32, for example, first forms a bump bottom metal layer 1 3 6 and then a bump 1 is configured respectively 34 (that is, the second bump) is on the bump bottom metal layer 136. Next, a flip-chip step is performed, and one of the female contact 1 1 2 and the corresponding record 1 2 2 is connected by the bump 134. The bump is, for example, a solder paste or a tin-lead alloy. In a preferred case, the first wafer is, for example, a logic circuit wafer, which has high-density pads 1 2 arranged in an area array. When the second wafer 130 is stacked on the wafer 100 in a flip-chip manner, the second wafer 130 is directly and mechanically connected to the wafer 100, so the second wafer The signal transmission path between 130 and 1000 is relatively shortened. In addition, since the second crystal 5 U〇 series can be used as a dynamic random access memory (DRAM) chip, and the first chip of the circle 100 has a logic operation function, it provides
Joj yJL 六匕 ^ 此’且利用堆疊的方式可提高構裝密度、減少空間 也降低了第二晶片丨3 〇與晶圓丨〇 〇之間訊號延遲的現 故叮達到向速處理的目的。 120接著1清參考第1E圖’進行迴鲜(reflow) ’以使凸塊 1 ο 〇在同溫狀態下熔融為一球體狀,而第二晶片13 〇與晶圓 之間的凸魏1 3 4,在經過迴銲之後,亦使得第二晶片Joj yJL Six Dagger ^ This ’and the use of stacking method can increase the structure density, reduce space and reduce the delay of the signal between the second chip 丨 3 〇 and wafer 丨 〇 〇 to achieve the purpose of speed processing. 120 Next, refer to FIG. 1E 'Reflow' to make the bump 1 ο 〇 melt into a sphere at the same temperature, and the second wafer 13 〇 and the convex between the wafer 1 3 4. After reflow, the second chip is also made
l〇551twf.ptd 587326 五、發明說明(6) 1 3 0與晶圓1 0 0之間形成良好的接合效果。值得注意的是, 第二晶片1 3 0與晶圓1 〇 〇的主要成分均為矽,故兩者之熱膨 脹係數相同,故凸塊134不會受到第二晶片130與晶圓100 之間熱膨脹係數不同而產生熱應變的疲勞(f a t i gu e )破 壞。如此,第二晶片130與晶圓loo之間的距離(stand〇f f) 可縮小,進而縮短第二晶片丨3 〇之銲墊丨3 2的間距或晶圓 1 0 0之晶片接點1 1 2的間距,以提高覆晶封裝的接點數目。 另一方面,由於凸塊1 2 0熔融為球體狀之後,為維持凸塊 1 2 0之高度,以提供後續第一晶片丨丨〇封裝於承載器上所需 之距離(standof f )。在較佳情況下,利用大面積之凸塊接 點1 1 4可使球形之凸塊1 2 0具有較大的外徑,以保持凸塊 I 2 0的高度。其中,晶片接點丨丨2之面積係小於凸塊接點 II 4的面積。 請參考第1 F及1G圖,將晶圓1 〇 〇切割,以獨立分開晶 圓1 〇 〇之第一晶片11 〇,而晶圓丨〇 〇在切割之後,再以覆晶 (F1 ip Chip)的方式配置於一承載器20 0上,而承載器200 例如為一封裝基板(substrate)或一印刷電路板(PCB)。其 中’承載器2 0 0具有多個接合墊2 〇 2,分別對應於每一凸塊 接點1 1 4,且晶圓1 〇 〇於覆晶之後,藉由凸塊1 2 〇分別連接 ^ 一凸塊接點1 1 4及對應之接合墊2 〇 2,以構成一堆疊式覆 曰曰封裝結構,並藉由迴銲這些凸塊丨2 〇,以使晶圓1 〇 〇與承 栽器2 〇 〇之間形成良好的接合效果。如此,第二晶片丨3 〇與 % _ 〜晶片110的訊號可藉由凸塊120而傳導至承載器20 0, 之後再經由承載器2 0 0之接點及内部線路(未繪示)而傳導〇551twf.ptd 587326 V. Description of the invention (6) A good bonding effect is formed between 130 and wafer 100. It is worth noting that the main components of the second wafer 130 and the wafer 1000 are both silicon, so the thermal expansion coefficients of the two are the same, so the bump 134 will not be subjected to the thermal expansion between the second wafer 130 and the wafer 100. Fatigue failure caused by thermal strain due to different coefficients. In this way, the distance (stand0ff) between the second wafer 130 and the wafer loo can be reduced, thereby further shortening the pitch of the second wafer 丨 3 〇 pad 3 ② or wafer contact 1 1 of the wafer 100 2 pitches to increase the number of contacts in a flip-chip package. On the other hand, after the bumps 120 are melted into a sphere, in order to maintain the height of the bumps 120, a distance (standof f) required for packaging the subsequent first wafer 丨 on the carrier is provided. In a better case, by using a large-area bump contact 1 1 4, the spherical bump 1 2 0 can have a larger outer diameter to maintain the height of the bump I 2 0. The area of the wafer contact 2 is smaller than the area of the bump contact II 4. Please refer to the 1F and 1G diagrams, and cut the wafer 100 to separate the first wafer 11 of the wafer 100 separately. After the wafer is cut, the wafer is then flip-chiped (F1 ip Chip ) Is configured on a carrier 200, and the carrier 200 is, for example, a packaging substrate or a printed circuit board (PCB). Among them, the “carrier 200” has a plurality of bonding pads 2 02, corresponding to each bump contact 1 4 respectively, and after the wafer 100 is flip-chiped, the bumps 1 2 0 are connected respectively ^ A bump contact 1 1 4 and a corresponding bonding pad 2 02 are used to form a stacked overlay package structure, and these bumps 2 are re-soldered so that the wafer 1 00 and the carrier A good bonding effect is formed between the devices. In this way, the signal of the second chip 丨 3 〇 and% _ ~ the chip 110 can be transmitted to the carrier 200 through the bump 120, and then through the contacts of the carrier 200 and the internal circuit (not shown). Conduct
587326 五、發明說明(7) 至外部電子裝置。 此外’如第1 Η圖所示,為了保護凸塊1 2 〇不會受到第 一晶片1 1 0與承載器2 〇 〇之間因熱膨脹係數不同而產生熱應 變的破壞,最後還可進行一底填(u n d e r f i 1 1 )製程,將一 底膠2 1 0如環氧樹脂(e p 〇 χ y r e s i η )填入於承载器2 〇 〇、第 二晶片1 3 0及第一晶片1 1 〇之間所構成的空間中,且底膠 2 1 〇係可完全包覆凸塊1 2 0以及凸塊1 34,以緩衝第一晶片 1 1 〇與承載器2 0 0之間的熱應變。 上述第1 F、1 G及1 Η圖之實施例中’係先將晶圓1 〇 〇切 副之後’再將獨立分開之第一晶片1 1 〇進行—覆晶封裝於 一承載器2 0 0上,最後再進行底填製程,以形成一堆疊式 復晶封裝結構。然而,本發明之另一實施例,亦可先將承 載器2 0 〇封裝於晶圓丨〇 〇上,並進行迴銲,藉由凸塊丨2 〇連 接承載器200之接合墊2〇2及晶圓100之凸塊接點114,之後 再切割晶圓1 〇 〇以及承載器2 0 0,以獨立分開承載器2 〇 〇以 及晶圓1 00之第一晶片1 1 0,最後再進行一底填製程,以形 成:堆疊式覆晶封裝結構。再者,如第2圖所示,本發明 之第一實施例,係配置多個第二晶片1 3 〇於晶圓1 〇 〇之單一 第一晶片11 0上,其流糕如第一實施例所述,在此不再贅 述。 制由以上之說明可知,本發明所揭露之堆疊式覆晶封骏 製程係在未切割之晶圓的表面上進行凸塊製程,其中凸$ 係以電鍍錫鉛合金或網版印刷的方式形成於每一凸塊接 上。接著以覆晶的方式將已切割之第二晶片直接封裝於晶587326 V. Description of the invention (7) To external electronic devices. In addition, as shown in the first figure, in order to protect the bump 1 2 0 from being damaged by the thermal strain due to the different thermal expansion coefficient between the first wafer 1 10 and the carrier 2 200, a final In an underfill 1 1 process, a primer 2 1 0 such as epoxy resin (ep 0 × yresi η) is filled in the carrier 2 000, the second wafer 1 30, and the first wafer 1 1 0. In the space formed by the space, the primer 2 10 can completely cover the bumps 120 and the bumps 1 34 to buffer the thermal strain between the first wafer 1 10 and the carrier 200. In the above-mentioned embodiments of the first F, 1 G, and 1 drawings, 'the wafer 100 is cut first, and then the separately separated first wafer 1 1 0 is performed—the flip chip is packaged in a carrier 2 0 0, and finally underfilling process to form a stacked polycrystalline packaging structure. However, in another embodiment of the present invention, the carrier 200 may be first packaged on a wafer 丨 00 and re-soldered, and the bonding pad 002 of the carrier 200 is connected to the carrier 200 by a bump 丨 200. And the bump contact 114 of the wafer 100, and then the wafer 100 and the carrier 2000 are cut to separate the carrier 200 and the first wafer 1 100 of the wafer 100 separately, and finally performed A bottom filling process to form: a stacked flip-chip package structure. Moreover, as shown in FIG. 2, the first embodiment of the present invention is configured by arranging a plurality of second wafers 130 on a single first wafer 110 of wafer 100, and the flow of cake is the same as that of the first embodiment. The examples are not repeated here. It can be known from the above description that the stacked flip-chip sealing process disclosed in the present invention is a bump process on the surface of an uncut wafer, wherein the bumps are formed by electroplating tin-lead alloy or screen printing. Connect to each bump. Then the chipped second wafer is directly packaged on the wafer
1〇551twf.ρια 第11頁 587326 五、發明說明(8) 圓之表面上,且第二晶片之銲墊藉由凸塊而連接於晶片接 點上。其中,第二晶片例如作為動態隨機記憶體(DRAM)之 晶片,而晶圓之第一晶片可作為邏輯電路晶片,兩者之間 的訊號傳遞路徑縮短,故可提高晶片運算之速度。此外, 晶圓於切割之後,再以覆晶的方式配置於一承載器上,以 形成一堆疊式覆晶封裝結構。由於第一晶片與第二晶片係 封裝於同一承載器上,且兩者以堆疊的方式彼此連接,因 此可提高覆晶構裝密度、減少空間需求,也降低了晶片與 晶圓之間訊號延遲的現象,故可達到晶片高速處理以及產 品多工性的目的。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍内,當可作些許之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。1〇551twf.ρια Page 11 587326 V. Description of the invention (8) On the surface of a circle, and the pads of the second chip are connected to the chip contacts by bumps. Among them, the second chip is, for example, a dynamic random access memory (DRAM) chip, and the first chip of the wafer can be used as a logic circuit chip. The signal transmission path between the two is shortened, so the speed of chip operation can be increased. In addition, after the wafer is diced, it is arranged on a carrier in a flip-chip manner to form a stacked flip-chip package structure. Since the first chip and the second chip are packaged on the same carrier, and the two are connected to each other in a stacked manner, the flip chip structure density can be increased, space requirements can be reduced, and the signal delay between the chip and the wafer can be reduced. Phenomenon, it can achieve the purpose of high-speed wafer processing and product multiplexing. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.
10551twf.ptd 第12頁 587326 圖式簡單說明 第1 A〜1 Η圖依序繪示本發明第一實施例之一種堆疊式 覆晶封裝製程的流程不意圖。 第2圖繪示本發明第二實施例之一種堆疊式覆晶封裝 的俯視示意圖。 【圖式標示說明】 100 晶 圓 110 第 一 晶 片 112 晶 片 接 點(第一 ‘接 點) 114 凸 塊 接 點(第二 -接 點) 116 凸 塊 底 金屬層 120 第 一 凸 塊 130 第 二 晶 片 132 銲 墊 134 第 二 凸 塊 136 凸 塊 底 金屬層 200 承 載 器 202 接 合 墊 210 底 膠10551twf.ptd Page 12 587326 Brief description of the drawings 1 A ~ 1 The drawings sequentially show the process of a stacked flip-chip packaging process according to the first embodiment of the present invention. FIG. 2 is a schematic top view of a stacked flip-chip package according to a second embodiment of the present invention. [Illustration of Graphical Symbols] 100 wafers 110 first wafers 112 wafer contacts (first 'contacts) 114 bump contacts (second-contacts) 116 bump bottom metal layer 120 first bump 130 second Wafer 132 Welding pad 134 Second bump 136 Bump metal layer 200 Carrier 202 Bonding pad 210 Primer
10551twf.ptd 第13頁10551twf.ptd Page 13
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