TW587326B - Stacked flip-chip package processing - Google Patents

Abstract

A stacked flip-chip package processing is provided. The bump processing is formed on the surface of the wafer, in which first bumps is formed on the first contracts. In addition, a second chip is mounted on the wafer by the means of flip-chip bonding, and the die pads of the second chip are connected to the second contracts through the second bumps. After the wafer is sawed into a plurality of first chips, the first chip stacks with the second chip and mounts on a carrier together to promote the density of the stacked chip package and to reduce the space required. Moreover, the first chip and the second chip shorten transmission lines and work in higher speed and multi-function is provided.

Description

587326

[Technical field to which the invention belongs] In particular, the present invention relates to a flip chip shovel and a stacked flip chip process [Previous technology] In the semiconductor industry, "Integrated circuits, The production of I c) is mainly divided into three stages: the manufacture and fabrication of wafers, the fabrication of circuits (1C), and the packaging of integrated circuits (ICs). It is completed through the steps of wafer fabrication, circuit design, photomask process, and wafer dicing. Each bare wafer formed by wafer dicing is passed through a bond pad on the bare wafer. The carrier is electrically connected to the carrier. The carrier is, for example, a substrate or a printed circuit board (PCB). In order to connect the above chip and the carrier, wires and wires are usually used. Bumps are used as a bonding medium to form a chip package structure. Among them, Flip Chip Interconnect Techno 1 0gy is the surface on the fresh pad of the wafer. The bumps are arranged in an area array, and then the wafer is flipped over, and the bumps on the wafer are respectively connected to the contacts on the carrier, so that the wafer can be electrically and mechanically connected to the wafer via the bumps. The carrier is then connected to external circuits, such as the motherboard, via the internal circuit and surface contacts of the carrier. With the increase in the degree of accumulation of the chip, the package structure of the chip is becoming more and more diverse. The chip packaging structure of flip-chip bonding technology has the advantages of reducing the chip packaging area and shortening the signal transmission path.

10551twf.ptd Page 5 587326 V. Description of the Invention (2) It has been widely used in the chip packaging field before, such as Chip Scale Package (CSP), Flip Chip / Bal 1 Grid Array , FC / BGA) and multi-chip module package (Mu 11 i -Ch ip Modu 1 e, MCM) and other types of package modules, are the scope of flip chip bonding technology. Among them, the multi-chip module package refers to the construction of several wafers on the same carrier by flip-chip bonding technology, and the wafers are electrically connected to each other through the carrier to form a multi-layered overlay. Crystal package structure. Take the memory multi-chip circuit chip to reduce the space to achieve and carry the structure, the accumulation degree signal [invention of dynamic random access memory (dynamic rand (meaeeess, DRAM), and logic circuit (10gic circuit) as an example, using Modular sealing (MCM) type can be used to store multiple money-saving chips and packages on the same carrying cry. + +> Η 两 东 ， ★ 降 # This not only raises the density of the south structure, the door of the; The phenomenon of signal delay between packaging modules, for the purpose of quick processing between Japanese and Japanese films, is in factor electronic products.彳 ^ 立 & a μ t pole is applied in communication ^ a ^ Value Tsai's main idea is that for a variety of S packages, especially multi-chip packages, # 瑨 π j jday after day packaging day after day How to seal clothes, mouths, mouths, and mouthpieces; make the ancient and many more: sexually sealed wafer products, and: The path of delivery is the focus of this invention. The contents of a single wafer] The purpose of the goods is to tie the surface of a wafer in the manufacturing process. In order to achieve the above object of the present invention, the present invention proposes a stacked flip chip

587326 V. Description of the invention (3) In the packaging process, a wafer is first provided, and the wafer has multiple first wafers, and each first wafer has multiple first contacts and multiple second contacts, and the first The contact is electrically connected to the second contact. A plurality of bumps are then disposed on these first contacts. A plurality of second wafers are provided, each of which has a plurality of solder pads corresponding to the second contacts, and a surface of the solder pads is respectively provided with a first bump, and then a flip-chip step is performed. A bump is connected to each second contact and one of the corresponding solder pads. Finally, re-soldering is performed and the wafer is cut to separate the first wafers independently. According to a preferred embodiment of the present invention, after the wafer is diced, the diced dies are arranged on a carrier, and the carrier has a plurality of bonding pads respectively corresponding to the first contacts, and These first contacts and corresponding bonding pads are respectively connected by a second bump. In addition, an underfill process is performed to fill a primer between the substrate, the wafer and the first wafer, and the primer further covers the bumps and bumps. In the present invention, a bump process is performed on the surface of an uncut wafer, and a cut wafer is arranged on the surface of the wafer to form a stacked flip-chip packaging structure. The wafers are directly stacked on the surface of the wafer and are electrically connected to each other by bumps, so the signal transmission path between the wafer and the wafer can be shortened, and the purpose of multi-chip packaging can be achieved. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Embodiment] The first 1 ~ 1 The figure illustrates a stacked type of the first embodiment of the present invention in sequence.

10551twf.prd Page 7 587326 V. Description of the invention (4) Schematic diagram of the flip-chip packaging process. Please refer to FIG. 1A first. First, a wafer 100 is provided. The surface of the wafer 100 can be roughly divided into a plurality of square-shaped first wafers 110 (refer to FIG. 2). After the internal integrated circuit of 100 has passed through a plurality of semiconductor processes, a plurality of first contacts 1 12 and a plurality of second contacts 1 1 4 are finally formed on the first wafer 丨 丨, among which the contacts} 丨2. 丨 丨 4 is the medium of δίΐ 5 tigers input and output. It is worth noting that these contacts 1 1 2, 1 1 4 are arranged on the first chip 丨 丨 0, for example, in a surface array manner, as chip contacts Π 2 (ie, first contacts) of a flip-chip package. Or bump contacts 丨 4 (ie, second contacts) 'and the chip contacts 1 1 2 and the bump contacts 1 1 4 are electrically connected to each other. Then, referring to FIG. 1B, “performing bumps on the surface of the wafer 100”, a plurality of bumps 120 (that is, the first bumps) are screen-printed (scree η print ing) respectively. It is formed on each bump contact 丨 丨 4, and the material of the bump 120 can be a tin-lead alloy. A bump bottom metal layer 116 has been formed on each of the bump contacts 丨 4. The bump bottom metal layer 116 is used to position the bumps 1 2 0 上 on the bump contacts 1 丨 4. In a better case, the bump contact worker 4 uses a knife cloth on the area around the first wafer 〇 〇, and uses a screen (Hedo will not) to first connect the wafer on the wafer 100 Point 丨 丨 2 covers and exposes only bump contact 114, and then solder paste is printed on the ^ 1 version in a printed manner, and on each bump contact 114 Bumps Tian Ran are formed separately. In addition to screen printing, the bumps 1 2 0 can also be plated. = The two are formed on the bump contacts 丨 丨 4, which uses lithography such as exposure and development. A photoresist (not shown) is formed on the wafer surface, and then a pattern is transferred to the photoresist, so that the photoresist forms a plurality of photoresist openings, and the photoresist

587326 V. Description of the invention (5) The resistance opening only exposes the bump contacts 丨 丨 4 and then the electroplated tin-lead alloy is used to form bumps 1 2 0 on each bump contact 1 1 4 and finally Photoresist removal. In addition, bumps can also be formed in a ball-planting manner. Then please refer to FIGS. 1C and 1D to provide a plurality of second wafers 130. The second wafer 130 is formed by cutting another wafer, and the surface of the second wafer 130 has a plurality of fresh pads ( Bonding pad) 132, respectively corresponding to wafer contacts 1 1 2 of wafer 1000, and the surface of the solder pads 32, for example, first forms a bump bottom metal layer 1 3 6 and then a bump 1 is configured respectively 34 (that is, the second bump) is on the bump bottom metal layer 136. Next, a flip-chip step is performed, and one of the female contact 1 1 2 and the corresponding record 1 2 2 is connected by the bump 134. The bump is, for example, a solder paste or a tin-lead alloy. In a preferred case, the first wafer is, for example, a logic circuit wafer, which has high-density pads 1 2 arranged in an area array. When the second wafer 130 is stacked on the wafer 100 in a flip-chip manner, the second wafer 130 is directly and mechanically connected to the wafer 100, so the second wafer The signal transmission path between 130 and 1000 is relatively shortened. In addition, since the second crystal 5 U〇 series can be used as a dynamic random access memory (DRAM) chip, and the first chip of the circle 100 has a logic operation function, it provides

Joj yJL Six Dagger ^ This ’and the use of stacking method can increase the structure density, reduce space and reduce the delay of the signal between the second chip 丨 3 〇 and wafer 丨 〇 〇 to achieve the purpose of speed processing. 120 Next, refer to FIG. 1E 'Reflow' to make the bump 1 ο 〇 melt into a sphere at the same temperature, and the second wafer 13 〇 and the convex between the wafer 1 3 4. After reflow, the second chip is also made

〇551twf.ptd 587326 V. Description of the invention (6) A good bonding effect is formed between 130 and wafer 100. It is worth noting that the main components of the second wafer 130 and the wafer 1000 are both silicon, so the thermal expansion coefficients of the two are the same, so the bump 134 will not be subjected to the thermal expansion between the second wafer 130 and the wafer 100. Fatigue failure caused by thermal strain due to different coefficients. In this way, the distance (stand0ff) between the second wafer 130 and the wafer loo can be reduced, thereby further shortening the pitch of the second wafer 丨 3 〇 pad 3 ② or wafer contact 1 1 of the wafer 100 2 pitches to increase the number of contacts in a flip-chip package. On the other hand, after the bumps 120 are melted into a sphere, in order to maintain the height of the bumps 120, a distance (standof f) required for packaging the subsequent first wafer 丨 on the carrier is provided. In a better case, by using a large-area bump contact 1 1 4, the spherical bump 1 2 0 can have a larger outer diameter to maintain the height of the bump I 2 0. The area of the wafer contact 2 is smaller than the area of the bump contact II 4. Please refer to the 1F and 1G diagrams, and cut the wafer 100 to separate the first wafer 11 of the wafer 100 separately. After the wafer is cut, the wafer is then flip-chiped (F1 ip Chip ) Is configured on a carrier 200, and the carrier 200 is, for example, a packaging substrate or a printed circuit board (PCB). Among them, the “carrier 200” has a plurality of bonding pads 2 02, corresponding to each bump contact 1 4 respectively, and after the wafer 100 is flip-chiped, the bumps 1 2 0 are connected respectively ^ A bump contact 1 1 4 and a corresponding bonding pad 2 02 are used to form a stacked overlay package structure, and these bumps 2 are re-soldered so that the wafer 1 00 and the carrier A good bonding effect is formed between the devices. In this way, the signal of the second chip 丨 3 〇 and% _ ~ the chip 110 can be transmitted to the carrier 200 through the bump 120, and then through the contacts of the carrier 200 and the internal circuit (not shown). Conduct

587326 V. Description of the invention (7) To external electronic devices. In addition, as shown in the first figure, in order to protect the bump 1 2 0 from being damaged by the thermal strain due to the different thermal expansion coefficient between the first wafer 1 10 and the carrier 2 200, a final In an underfill 1 1 process, a primer 2 1 0 such as epoxy resin (ep 0 × yresi η) is filled in the carrier 2 000, the second wafer 1 30, and the first wafer 1 1 0. In the space formed by the space, the primer 2 10 can completely cover the bumps 120 and the bumps 1 34 to buffer the thermal strain between the first wafer 1 10 and the carrier 200. In the above-mentioned embodiments of the first F, 1 G, and 1 drawings, 'the wafer 100 is cut first, and then the separately separated first wafer 1 1 0 is performed—the flip chip is packaged in a carrier 2 0 0, and finally underfilling process to form a stacked polycrystalline packaging structure. However, in another embodiment of the present invention, the carrier 200 may be first packaged on a wafer 丨 00 and re-soldered, and the bonding pad 002 of the carrier 200 is connected to the carrier 200 by a bump 丨 200. And the bump contact 114 of the wafer 100, and then the wafer 100 and the carrier 2000 are cut to separate the carrier 200 and the first wafer 1 100 of the wafer 100 separately, and finally performed A bottom filling process to form: a stacked flip-chip package structure. Moreover, as shown in FIG. 2, the first embodiment of the present invention is configured by arranging a plurality of second wafers 130 on a single first wafer 110 of wafer 100, and the flow of cake is the same as that of the first embodiment. The examples are not repeated here. It can be known from the above description that the stacked flip-chip sealing process disclosed in the present invention is a bump process on the surface of an uncut wafer, wherein the bumps are formed by electroplating tin-lead alloy or screen printing. Connect to each bump. Then the chipped second wafer is directly packaged on the wafer

1〇551twf.ρια Page 11 587326 V. Description of the invention (8) On the surface of a circle, and the pads of the second chip are connected to the chip contacts by bumps. Among them, the second chip is, for example, a dynamic random access memory (DRAM) chip, and the first chip of the wafer can be used as a logic circuit chip. The signal transmission path between the two is shortened, so the speed of chip operation can be increased. In addition, after the wafer is diced, it is arranged on a carrier in a flip-chip manner to form a stacked flip-chip package structure. Since the first chip and the second chip are packaged on the same carrier, and the two are connected to each other in a stacked manner, the flip chip structure density can be increased, space requirements can be reduced, and the signal delay between the chip and the wafer can be reduced. Phenomenon, it can achieve the purpose of high-speed wafer processing and product multiplexing. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10551twf.ptd Page 12 587326 Brief description of the drawings 1 A ~ 1 The drawings sequentially show the process of a stacked flip-chip packaging process according to the first embodiment of the present invention. FIG. 2 is a schematic top view of a stacked flip-chip package according to a second embodiment of the present invention. [Illustration of Graphical Symbols] 100 wafers 110 first wafers 112 wafer contacts (first 'contacts) 114 bump contacts (second-contacts) 116 bump bottom metal layer 120 first bump 130 second Wafer 132 Welding pad 134 Second bump 136 Bump metal layer 200 Carrier 202 Bonding pad 210 Primer

10551twf.ptd Page 13

Claims (1)

587326 6. Scope of patent application 1 · A stacked flip-chip packaging process at least includes: providing a wafer with a plurality of first wafers, and each of the first wafers has a plurality of first contacts and a plurality of first wafers; Two contacts, wherein the first contacts are electrically connected to the second contacts; a plurality of first bumps are arranged on the first contacts; a plurality of wafers are provided, and each of the wafers has a plurality of contacts Pads corresponding to the second contacts, and a second bump is respectively arranged on the surfaces of the pads; a flip-chip step is performed to connect each of the second contacts by the second bump Point and one of the corresponding pads; reflow; and cut the wafer to separate the first wafers independently. 2. The stacked flip-chip packaging process described in item 1 of the patent application scope further includes providing a carrier with a plurality of bonding pads respectively corresponding to the first contacts, and the wafer is flip-chip Way, the first bumps and the corresponding bonding pads are respectively connected by the first bumps. 3. The stacked flip-chip packaging process described in item 2 of the patent application scope further includes an underfill process in which a primer is filled between the carrier, the wafers and the first wafers. 4. The stacked flip-chip packaging process as described in item 3 of the patent application scope, wherein the primer further covers the first bumps and the second bumps. 5. The stacked flip-chip packaging process according to item 1 of the scope of patent application, wherein the first bumps are formed on the first contacts by electroplating. 10551twf.ptd Page 14 587326 6. Scope of patent application 6 · The stacked flip-chip packaging process described in item 1 of the scope of patent application, wherein the first bumps are formed on the first through screen printing. One point. 7. A stacked flip-chip packaging process, at least comprising: providing a wafer having a plurality of first wafers, and each of the first wafers having a plurality of first contacts and a plurality of second contacts; A plurality of first bumps on the first contacts; a plurality of wafers are provided, each of which has a plurality of solder pads corresponding to the second contacts, and the surfaces of the solder pads are respectively arranged A first-first bump, performing a flip-chip step, connecting each of the second contacts and one of the corresponding pads by the second bump; and the points are connected to a pair of first and second ones It should be divided into several pieces. The number of convex pieces is more than one, and the number of convex pieces is one, and Hai = 0; the bearing is borrowed and welded back to one, and the supply point is picked up and picked up. Separated by device. The pad and the round connection crystal should be cut as described in the packaged crystal overlay stack. Item 7 Fan Li specially invites the middle piece such as crystal 8. Some of the devices should be filled with the Xuan mouth. The rubber-base packaged crystal-covered stack is described in the first item of the film 8 and the film of the second step is filled with the crystal bottom of the film. Please include some applications such as more and 9. The block and convex seal of the two crystals are covered by the first type of the stack and the block. The first item is covered with a more rubberized bottom. 10551iwf.ptd Page 15 587326 10551twf.ptd Page 16