CN216980539U - Fan-out packaging structure and chip packaging body - Google Patents
Fan-out packaging structure and chip packaging body Download PDFInfo
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- CN216980539U CN216980539U CN202220550872.5U CN202220550872U CN216980539U CN 216980539 U CN216980539 U CN 216980539U CN 202220550872 U CN202220550872 U CN 202220550872U CN 216980539 U CN216980539 U CN 216980539U
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Abstract
The utility model provides a fan-out packaging structure, comprising: the device comprises a rewiring layer, a plurality of chips welded on the rewiring layer and a plurality of silicon dummy wafers fixed on the rewiring layer, wherein the projection of the chips on the rewiring layer is not overlapped with the projection of the silicon dummy wafers on the rewiring layer. Through the fan-out packaging structure and the chip packaging body, the silicon dummy wafer is arranged in the fan-out packaging structure so as to improve the volume ratio of the silicon material in the whole fan-out packaging structure, the warping degree depends on the volume ratio of the silicon material on the whole fan-out packaging structure, and the higher the volume ratio is, the smaller the warping degree is, so that the warping degree of the fan-out packaging structure is reduced; in addition, the reduction of the warping degree can also greatly improve the internal stress distribution of the fan-out packaging structure, and the phenomenon of local stress concentration is avoided; finally, the yield of the fan-out packaging structure and the failure risk of the follow-up product in the service process are guaranteed.
Description
Technical Field
The utility model relates to the technical field of chip packaging, in particular to a fan-out packaging structure and a chip packaging body.
Background
In the high-density fan-out package structure, a plurality of chips are usually used as a chip unit to realize rearrangement of I/O pins of the chips through a plurality of high-density redistribution layers prepared on a carrier plate, and are plastically packaged by a high-modulus EMC (Epoxy Molding Compound) Molding Compound. The chip is connected in a conductive manner by welding the conductive columns prepared on the pins of the chip and the bonding pads of the redistribution layer, and the chip-level micro conductive columns generally adopt photoetching and electroplating processes with high manufacturing cost; after the conductive connection between the chip and the rewiring layer is completed, the chip needs to be subjected to bottom filling, and EMC plastic package is performed on the chip units, so that the built plastic package layer can realize the reliability protection of the chip.
However, CTE (Coefficient of Thermal Expansion) mismatch exists among the EMC molding compound, the underfill, the conductive posts of the chip, and the silicon base material of the chip, so that warpage caused by CTE mismatch and local stress concentration caused by warpage are introduced into the fan-out package structure, yield of the fan-out package structure is greatly reduced, and failure risk in the subsequent product service process is improved.
SUMMERY OF THE UTILITY MODEL
Aiming at the defects in the prior art, the utility model provides a fan-out packaging structure and a chip packaging body.
In a first aspect, in one embodiment, the present invention provides a fan-out package structure, comprising:
the device comprises a rewiring layer, a plurality of chips welded on the rewiring layer and a plurality of silicon dummy pieces fixed on the rewiring layer, wherein the projection of the chips on the rewiring layer is not overlapped with the projection of the silicon dummy pieces on the rewiring layer.
In one embodiment, the plurality of chips soldered on the redistribution layer are formed into a plurality of chip units, each chip unit including a plurality of chips.
In one embodiment, the conductive posts on the pins of the chip and the bonding pads of the redistribution layer form tin-based solder balls through a reflow soldering process, so that the chip and the redistribution layer are soldered.
In one embodiment, the fan-out package structure further includes:
and the underfill is filled between the chip and the redistribution layer and wraps the conductive columns, the tin-based solder balls and the bonding pads.
In one embodiment, the fan-out package structure further includes:
and the DAF film, the silicon dummy sheet and the rewiring layer are pasted through the DAF film.
In one embodiment, the fan-out package structure further includes:
and carrying out plastic package on the chip and the silicon dummy chip to obtain a plastic package layer.
In one embodiment, the fan-out package structure further includes:
and the scribing film is adhered to one side of the plastic packaging layer, which is far away from the rewiring layer.
In one embodiment, the fan-out package structure further includes:
preparing a ball-planting solder ball on one side of the redistribution layer away from the chip;
the ball-planting solder ball is used for being connected with the packaging substrate or the PCB.
In one embodiment, the fan-out package structure further includes:
preparing a scribing way on one side of the rewiring layer away from the chip;
the scribing lanes are used for providing position indication for the subsequent scribing process.
In a second aspect, in an embodiment, the present invention provides a chip package, which is obtained by dicing the fan-out package structure in the above one embodiment along dicing streets.
Through the fan-out packaging structure and the chip packaging body, the silicon dummy wafer is arranged in the fan-out packaging structure so as to improve the volume ratio of the silicon material in the whole fan-out packaging structure, the warping degree depends on the volume ratio of the silicon material on the whole fan-out packaging structure, and the higher the volume ratio is, the smaller the warping degree is, so that the warping degree of the fan-out packaging structure is reduced; in addition, the reduction of the warping degree can also greatly improve the internal stress distribution of the fan-out packaging structure, and the phenomenon of local stress concentration is avoided; finally, the yield of the fan-out packaging structure and the failure risk of the follow-up product in the service process are guaranteed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
FIG. 1 is a schematic structural diagram of a fan-out package structure in one embodiment of the utility model;
FIG. 2 is a schematic diagram showing the distribution of chip units and dummy silicon wafers on a dicing film according to an embodiment of the present invention;
fig. 3 is an enlarged view of the area a in fig. 2.
In the above drawings: 1. scribing the film; 2. a silicon dummy wafer; 3. scribing a street; 4. a DAF film; 5. a rewiring layer; 5a, rewiring the first layer; 5b, rewiring the second layer; 6. a conductive post; 7. tin-based solder balls; 8. a pad; 9. bottom filling; 10. a plastic packaging layer; 11. planting ball solder; 100. a chip unit; 100a, a chip; 100b, a chip; 100c, a chip; 100d, chip.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.
In a first aspect, in one embodiment, the present invention provides a fan-out package structure, comprising:
the device comprises a rewiring layer, a plurality of chips welded on the rewiring layer and a plurality of silicon dummy wafers fixed on the rewiring layer, wherein the projection of the chips on the rewiring layer is not overlapped with the projection of the silicon dummy wafers on the rewiring layer.
Wherein, the silicon dummy wafer is a small silicon wafer with a certain thickness.
Through the fan-out packaging structure and the chip packaging body, the silicon dummy wafer is arranged in the fan-out packaging structure so as to improve the volume ratio of the silicon material in the whole fan-out packaging structure, the warping degree depends on the volume ratio of the silicon material on the whole fan-out packaging structure, and the higher the volume ratio is, the smaller the warping degree is, so that the warping degree of the fan-out packaging structure is reduced; in addition, the reduction of the warping degree can also greatly improve the internal stress distribution of the fan-out packaging structure, and the phenomenon of local stress concentration is avoided; finally, the yield of the fan-out packaging structure and the failure risk of the follow-up product in the service process are guaranteed.
As shown in fig. 1, 2 and 3, in one embodiment, there are a plurality of chips, such as the chip 100a, the chip 100b, the chip 100c and the chip 100d in fig. 1, soldered on the redistribution layer 5, the plurality of chips form a plurality of chip units 100, each chip unit 100 includes a plurality of chips, such as the chip 100a and the chip 100b form a chip unit 100, and the chip 100c and the chip 100d form a chip unit 100.
In this embodiment, the fan-out package structure is a wafer level package structure and includes a plurality of chip units 100, a plurality of corresponding individual chip packages may be obtained through a subsequent dicing process, and each chip package includes a corresponding chip unit 100. Of course, in other embodiments, the fan-out package structure may only include one chip unit 100, and then dicing is not required subsequently.
Wherein the rewiring layer 5 includes a rewiring first layer 5a and a rewiring second layer 5 b; of course, in other embodiments, the redistribution layer 5 may include a greater or lesser number of layers.
The volume ratio of silicon materials in the whole fan-out packaging structure is improved by arranging the silicon dummy wafer 2 in the fan-out packaging structure comprising a plurality of chip units 100; and the scribing cutter can cut the higher EMC plastic-sealed material of modulus (namely plastic-sealed layer 10, utilize EMC plastic-sealed material to construct plastic-sealed layer 10, can completely cut off the influence that external complex environment produced the chip), cause local crackle very easily, and this kind of local crackle can be along with going on of cutting progress and constantly aggravate, especially when fan-out packaging structure's angularity is higher, this kind can further aggravate because of the crackle that the cutting triggered, consequently lay silicon dummy wafer 2 and can alleviate the condition that the scribing cutter takes place local crackle when carrying out the scribing to fan-out packaging structure, improve the scribing yield.
As shown in fig. 1, 2 and 3, the dummy silicon wafer 2 is arranged at an edge portion of the rewiring layer 5.
Wherein, the fan-out package process is to re-arrange the pins of the chip by re-wiring, and convert the dense pins on the chip into the wider ball-planting solder balls 11 on the side of the redistribution layer 5 away from the chip, so as to facilitate the conductive connection with the external package substrate or PCB, and the pins of the chip and the ball-planting solder balls 11 of the redistribution layer 5 are conductively connected through the connection circuit in the redistribution layer 5, therefore, the area of the redistribution layer 5 is usually larger than the area of the chip unit 100, the chip unit 100 is usually distributed in the middle of the redistribution layer 5 in a concentrated manner, so that the edge of the redistribution layer 5 has a certain margin, while the traditional package process can directly carry out plastic package on the margin in the subsequent process, so that the occupation ratio of the silicon material in the finally obtained fan-out package structure is low, and in this embodiment, the silicon dummy wafer 2 is distributed at the edge of the redistribution layer 5, the silicon material can be provided. Of course, in other embodiments, the dummy silicon wafer 2 may be disposed at a non-edge portion of the redistribution layer 5 (i.e., a portion between adjacent chip units 100).
As shown in fig. 1, in one embodiment, the conductive posts 6 on the leads of the chip itself and the pads 8 of the redistribution layer 5 are formed into solder balls 7 by a reflow process, thereby achieving the bonding of the chip and the redistribution layer 5.
As shown in fig. 1, in an embodiment, the fan-out package structure further includes:
and an underfill 9 filled between the chip and the redistribution layer 5 and wrapping the conductive posts 6, the tin-based solder balls 7 and the pads 8.
The underfill 9 can redistribute the mechanical load of the chip to the entire surface area of the chip, so as to reduce the stress and strain on the conductive posts 6, the tin-based solder balls 7 and the pads 8, and especially plays a very important role in reducing the thermal stress and strain on the conductive posts 6, the tin-based solder balls 7 and the pads 8.
As shown in fig. 1, in an embodiment, the fan-out package structure further includes:
the DAF film 4, the dummy silicon wafer 2 is stuck to the rewiring layer 5 through the DAF film 4.
Among them, the daf (die Attach film) film can stably Attach the dummy silicon wafer 2 to the rewiring layer 5 by its adhesive action.
As shown in fig. 1, in an embodiment, the fan-out package structure further includes:
and the scribing film 1 is adhered to one side of the plastic sealing layer 10 far away from the rewiring layer 5.
The scribing film 1 can be made of the same material as the DAF film, and the scribing film 1 can ensure that weak connection is kept between chip packaging bodies after scribing is finished, so that disorder of positions is avoided.
As shown in fig. 1, in an embodiment, the fan-out package structure further includes:
preparing a dicing street 3 on a side of the redistribution layer 5 away from the chip;
the scribe lanes 3 are used to provide a position indication for the subsequent scribing process.
In fig. 1, the dicing process has been completed, and cutting is started from the dicing streets 3 until the cutting depth completely penetrates to the dicing film 1.
In a second aspect, as shown in fig. 1, in one embodiment, the utility model provides a chip package obtained by dicing the fan-out package structure in the above one embodiment along the dicing streets 3.
In fig. 1, a plurality of chip packages, such as the chip package including the chip 100a and the chip 100b and the chip package including the chip 100c and the chip 100d in fig. 1, have been obtained through a dicing process, and the plurality of chip packages are only weakly connected by the dicing film 1, and then only the chip packages need to be peeled off from the dicing film 1.
The chip packaging body obtained by the embodiment is obtained by scribing based on the fan-out packaging structure distributed with the silicon dummy pieces 2, so that the yield can be ensured during scribing, the quality of the obtained chip packaging body is ensured, and the failure condition is not easy to occur in the subsequent service process of the chip packaging body due to the existence of the silicon dummy pieces 2.
As shown in fig. 1, in one embodiment, the present invention provides a method for manufacturing a chip package, including:
s1: preparing a plurality of heavy wiring layers 5 with high-density wiring structures on a 12-inch circular carrier plate according to the requirements of a chip;
s2: connecting the conductive columns 6 on the chip pins to the bonding pads 8 of the redistribution layer 5 through a reflow soldering process to realize conductive interconnection between the chip and the redistribution layer 5;
s3: filling the bottom of the chip to obtain an underfill 9, and distributing the silicon dummy wafer 2 with the DAF film 4 to the edge area of the redistribution layer 5;
s4: carrying out plastic package on the chip and the dummy silicon chip 2, and concretely carrying out plastic package by adopting an EMC plastic package material to obtain a plastic package layer 10;
s5: removing the carrier plate through de-bonding, preparing a ball-planting solder ball 11 through a ball-planting process, thinning to obtain a fan-out packaging structure, and preparing a scribing way 3 on the fan-out packaging structure;
s6: and scribing the fan-out packaging structure along the scribing lanes 3 by a scribing process to obtain a plurality of chip packaging bodies which are kept in weak connection through the scribing films 1.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the utility model. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the utility model, and these changes and modifications are all within the scope of the utility model. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. A fan-out package structure, comprising:
the device comprises a rewiring layer, a plurality of chips welded on the rewiring layer and a plurality of silicon dummy pieces fixed on the rewiring layer, wherein the projection of the chips on the rewiring layer is not overlapped with the projection of the silicon dummy pieces on the rewiring layer.
2. The fan-out package structure of claim 1, wherein a plurality of the chips soldered on the redistribution layer form a plurality of chip units, each chip unit including a plurality of the chips.
3. The fan-out package structure of claim 2, wherein the conductive posts on the pins of the chip and the pads of the redistribution layer form solder balls on the chip by a reflow process, thereby achieving soldering of the chip and the redistribution layer.
4. The fan-out package structure of claim 3, further comprising:
and the underfill is filled between the chip and the redistribution layer and wraps the conductive columns, the tin-based solder balls and the bonding pads.
5. The fan out package structure of claim 2, further comprising:
and the silicon dummy wafer is pasted on the heavy wiring layer through the DAF film.
6. The fan-out package structure of claim 2, further comprising:
and carrying out plastic packaging on the chip and the silicon dummy chip to obtain a plastic packaging layer.
7. The fan-out package structure of claim 6, further comprising:
and the scribing film is adhered to one side of the plastic packaging layer, which is far away from the rewiring layer.
8. The fan-out package structure of claim 7, further comprising:
preparing a ball-planting solder ball on one side of the redistribution layer away from the chip;
the ball-planting solder ball is used for being connected with the packaging substrate or the PCB.
9. The fan-out package structure of claim 8, further comprising:
preparing a scribing way on one side of the rewiring layer away from the chip;
the scribing channels are used for providing position indication for the subsequent scribing process.
10. A chip package obtained by dicing the fan-out package structure of claim 9 along the dicing streets.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220550872.5U CN216980539U (en) | 2022-03-14 | 2022-03-14 | Fan-out packaging structure and chip packaging body |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220550872.5U CN216980539U (en) | 2022-03-14 | 2022-03-14 | Fan-out packaging structure and chip packaging body |
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| CN216980539U true CN216980539U (en) | 2022-07-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117390936A (en) * | 2023-12-12 | 2024-01-12 | 武创芯研科技(武汉)有限公司 | Method and system for solving warpage of chip packaging reliability model |
| CN117894797A (en) * | 2024-03-13 | 2024-04-16 | 江苏中科智芯集成科技有限公司 | Fan-out type wafer |
-
2022
- 2022-03-14 CN CN202220550872.5U patent/CN216980539U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117390936A (en) * | 2023-12-12 | 2024-01-12 | 武创芯研科技(武汉)有限公司 | Method and system for solving warpage of chip packaging reliability model |
| CN117390936B (en) * | 2023-12-12 | 2024-03-15 | 武创芯研科技(武汉)有限公司 | Method and system for solving warpage of chip packaging reliability model |
| CN117894797A (en) * | 2024-03-13 | 2024-04-16 | 江苏中科智芯集成科技有限公司 | Fan-out type wafer |
| CN117894797B (en) * | 2024-03-13 | 2024-05-28 | 江苏中科智芯集成科技有限公司 | Fan-out type wafer |
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