TW200407995A - Mark and method for multiple alignment - Google Patents

Mark and method for multiple alignment Download PDF

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Publication number
TW200407995A
TW200407995A TW091132929A TW91132929A TW200407995A TW 200407995 A TW200407995 A TW 200407995A TW 091132929 A TW091132929 A TW 091132929A TW 91132929 A TW91132929 A TW 91132929A TW 200407995 A TW200407995 A TW 200407995A
Authority
TW
Taiwan
Prior art keywords
stack
alignment
alignment mark
marks
mark
Prior art date
Application number
TW091132929A
Other languages
English (en)
Chinese (zh)
Other versions
TWI302348B (https=
Inventor
Feng-Yi Chen
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to TW091132929A priority Critical patent/TW200407995A/zh
Priority to US10/684,108 priority patent/US6962854B2/en
Publication of TW200407995A publication Critical patent/TW200407995A/zh
Priority to US11/067,958 priority patent/US20050156335A1/en
Application granted granted Critical
Publication of TWI302348B publication Critical patent/TWI302348B/zh

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
TW091132929A 2002-11-08 2002-11-08 Mark and method for multiple alignment TW200407995A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW091132929A TW200407995A (en) 2002-11-08 2002-11-08 Mark and method for multiple alignment
US10/684,108 US6962854B2 (en) 2002-11-08 2003-10-10 Marks and method for multi-layer alignment
US11/067,958 US20050156335A1 (en) 2002-11-08 2005-02-28 Marks and method for multi-layer alignment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091132929A TW200407995A (en) 2002-11-08 2002-11-08 Mark and method for multiple alignment

Publications (2)

Publication Number Publication Date
TW200407995A true TW200407995A (en) 2004-05-16
TWI302348B TWI302348B (https=) 2008-10-21

Family

ID=32228173

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091132929A TW200407995A (en) 2002-11-08 2002-11-08 Mark and method for multiple alignment

Country Status (2)

Country Link
US (2) US6962854B2 (https=)
TW (1) TW200407995A (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003257828A (ja) * 2002-03-01 2003-09-12 Nec Electronics Corp 半導体装置の製造方法
US6617175B1 (en) * 2002-05-08 2003-09-09 Advanced Technology Materials, Inc. Infrared thermopile detector system for semiconductor process monitoring and control
DE10258420B4 (de) * 2002-12-13 2007-03-01 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterspeichereinrichtung mit Charge-trapping-Speicherzellen und vergrabenen Bitleitungen
US6914337B2 (en) * 2003-11-04 2005-07-05 Taiwan Semiconductor Manufacturing Co., Ltd Calibration wafer and kit
US7289868B2 (en) * 2005-08-22 2007-10-30 Hewlett-Packard Development Company, L.P. System and method for calculating a shift value between pattern instances
KR20090128337A (ko) * 2008-06-10 2009-12-15 어플라이드 머티리얼즈 이스라엘 리미티드 반복 패턴을 갖는 물체를 평가하는 방법 및 시스템
US11342184B2 (en) * 2019-11-25 2022-05-24 Xia Tai Xin Semiconductor (Qing Dao) Ltd. Method of forming multiple patterned layers on wafer and exposure apparatus thereof
TWI833185B (zh) * 2022-01-04 2024-02-21 南亞科技股份有限公司 疊置誤差的校正方法及半導體元件的製備方法
US12002765B2 (en) 2022-01-04 2024-06-04 Nanya Technology Corporation Marks for overlay measurement and overlay error correction
US11796924B2 (en) 2022-01-04 2023-10-24 Nanya Technology Corporation Method for overlay error correction and method for manufacturing a semiconductor device structure with overlay marks
US12117735B2 (en) * 2022-02-16 2024-10-15 Nanya Technology Corporation Method of determining overlay error during semiconductor fabrication

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2841124C2 (de) * 1978-09-21 1984-09-13 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von elektronischen Halbleiterbauelementen durch Röntgen-Lithographie
JPS57112021A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of semiconductor device
US6118137A (en) * 1997-09-08 2000-09-12 Advanced Micro Devices, Inc. Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias
US5916715A (en) * 1997-09-08 1999-06-29 Advanced Micro Devices, Inc. Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements
US5952132A (en) * 1997-09-12 1999-09-14 Taiwan Semiconductor Mfg. Co. Method for forming a stepper focus pattern through determination of overlay error
US6465322B2 (en) * 1998-01-15 2002-10-15 Koninklijke Philips Electronics N.V. Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing
US6228743B1 (en) * 1998-05-04 2001-05-08 Motorola, Inc. Alignment method for semiconductor device
US6350548B1 (en) * 2000-03-15 2002-02-26 International Business Machines Corporation Nested overlay measurement target
US6484060B1 (en) * 2000-03-24 2002-11-19 Micron Technology, Inc. Layout for measurement of overlay error
JP3588582B2 (ja) * 2000-10-20 2004-11-10 松下電器産業株式会社 半導体装置の製造方法
US6440816B1 (en) * 2001-01-30 2002-08-27 Agere Systems Guardian Corp. Alignment mark fabrication process to limit accumulation of errors in level to level overlay
JP3914451B2 (ja) * 2001-02-26 2007-05-16 エーエスエムエル ネザーランズ ビー．ブイ． 測定された位置合わせマークの修正位置を決定するためのコンピュータプログラムと、デバイス製造方法と、該製造方法により製造されるデバイス
US7190823B2 (en) * 2002-03-17 2007-03-13 United Microelectronics Corp. Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same
US6782525B2 (en) * 2002-09-05 2004-08-24 Lsi Logic Corporation Wafer process critical dimension, alignment, and registration analysis simulation tool
US6925411B1 (en) * 2003-04-02 2005-08-02 Sun Microsystems, Inc. Method and apparatus for aligning semiconductor chips using an actively driven vernier

Also Published As

Publication number Publication date
US20050156335A1 (en) 2005-07-21
US20040092080A1 (en) 2004-05-13
US6962854B2 (en) 2005-11-08
TWI302348B (https=) 2008-10-21

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