TW200405481A - Structure comprising an interlayer of palladium and/or platinum and method for fabrication thereof - Google Patents

Structure comprising an interlayer of palladium and/or platinum and method for fabrication thereof Download PDF

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TW200405481A
TW200405481A TW092120508A TW92120508A TW200405481A TW 200405481 A TW200405481 A TW 200405481A TW 092120508 A TW092120508 A TW 092120508A TW 92120508 A TW92120508 A TW 92120508A TW 200405481 A TW200405481 A TW 200405481A
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copper
inner layer
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TW092120508A
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Panayotis C Andricacos
Steven H Boettcher
Fenton Read Mcfeely
Milan Pounovic
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Ibm
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • H—ELECTRICITY
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322—Composite web or sheet
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    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
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Description

200405481 五、發明說明（1) 發明所屬之技術領域 本發明係關於在電子裝署μ μ &、志 置上的内連線路，例如在積體 電路晶片上，及更具體的關於將人枘沾〜土 ^ ^ Α 剛ι將3銅的内連線放在積體電 路内。 二、【先前技術】 過去’ n銅合金和其相關合金是較佳的合金來在電子 衣置上形成内連線，例如積體電路晶片。銅在銘—銅合全 所含的數量一般上在0· 3%至4%的範圍之間。 晶片的内連線材料由銅或銅合金取代紹 士:寻到良好性能。性能改善是因為銅和某些銅合金之 率低於鋁-銅合金之電阻率；因此細 尾I且 高的線路密度能被實現。 I 線路能被利用且更 體工業所確認。事實 料的選擇迅速的检棄 率和改善的可靠度。 鋁 銅金屬金屬化的優點早被半導 上’半導體工業在晶片的内連線材 而選擇銅，其原因在於鋼的高導電 製造内連線包含很多相關聯的步驟。 制 連線所用的方法稱作、、雙道金屬鑲嵌法,，衣w鋼内
Damascene )’這方法在單一步驟同 、生Ual 路。但有一個整合性的問題，豆問衣化"層洞和一線 ^ 』畸是阻障層雪糾益> 晶層（s e e d 1 a y e r )薄膜和銅内連崎 、在種 ，而以雙道金屬鑲嵌
200405481
法製造銅内連線能成功地克服此問題。此外，國際半導體 技術&圖（I T R S )’ 1 9 9 9年版，預測未來内連金屬化製程 需要較小介層洞的直徑和更好的深寬比（aspect 、 ratios )。 在許多先前的技術，用電沉積法將銅沉積在一銅種晶 層上，而銅種晶層再依次沉積在一層擴散層上。擴散阻g 層和銅種晶層的沉積都是用物理氣相沉積法（pvD)，離子物 理氣相沉積法（I PCD ),或化學氣相沉積法（c VD )(胡· 等人於Mat· Chem.phts·，52 ( 1 998 ) 5 )，再者，此擴散層通 常包含有兩層（例如··鈦/氮化鈦雙層阻障層）。 因此，先前技術對於改善種晶層或銅層的附著性具 改善的空間。 三、【發明内容】 本發明，使放在積體電路的含銅的内連線製造成為可 能，此結構利用某些内層在鋼層或種晶層，或直下方阻障 層之間。本發明係利用一鈀及/或鉑的内層。’
n二二，日月係關於一電子結構，此結構包含基材， 八=有3;丨層洞開口（via opening)的介電層，此介層洞 2:土及底部表面；而且阻障層在表面介層洞開口側号 氐。之上，含有鈀及/或鉑的内層；銅或銅合金層位於
200405481
内層上。 另一方面，本發明係關於製造一電子結構的 包基材上形成絕緣物質，將絕緣物質微：月二' 絕緣物質上形成後及/表介馬、μ &義及在 j凹處；在該凹處沉積阻障層；沉積含有鈀及/或鉑=貝 a ，以及沉積銅或銅合金在内層之上以填滿凹處。、· 盡的和被熟此技藝者經由下列詳 由簡單的圖式戈明以本—=I#田述本發明較佳實施例，經 ,^ H式明只订本發明的最好模式。五人可7加 本奄明有其他不同的實施例， 口可了解 面能修正，且不脫雜太& 且數個細即在多種明顯的方
所L、 不脫離本發明的精神。因此，下诚於、+、产I 貝上視為說明，而不是限制。 ’、以在本 四、【實施方式】 參考圖式可幫助了解本發夂 L^ ^ 發明可f >見圖1，此紇構依據本 料2而： （例如半導體晶圓基材）提供-絕缘材 枓2而得，例如二氧化矽。 促1/、、、巴、、彖材 已習知5 2: τ ’線及/或介層洞開口 3被微影化定義和利用 積在圖3結構之上。此二斤示’㈣層4沉 積法，# 9戌… 陣層，儿積一般上疋使用化學氣相沉 、3疋使用濺鍍法，例如物理氣相沉積法或離子物理
五、發明說明（4) 氣相》儿積法。 依據本發明，如圖4所示， 障層4上。此内層的沉積可使用化或'的内層5沉積於阻 沉積法或離子物理氣相沉積法。内層5: ς:二译物理氣相 至約50 0埃，而且更並型的 ，、1之厚度為約50埃 U的厚度為約5〇埃至約！ 00埃。 :層5強化阻障層4及其後續沉積銅 舉例來…層5沉積可使用賤鍍法沉積 ：者二 沉積。如圖5所示，若有需®u ”相/儿積法 ,,,^甘 右有而要可遥擇性的形成一種晶層6 , =銅，其沉積在内層5之上。依據本發明種晶層6是非必 t的。此鋼層6是使用無電解或電鍍法所沉積的電化學 物。 、 、 此種晶層6 一般厚度為約50nm至約20〇nm，更適用厚度 為約60nm至約1 OOnm。 一般的然電解銅電鍍合成物是水溶液合成物，其水溶 液合成物包含銅離子水溶液、還原劑（recjucing agent) 和錯合劑（complexing agent)。其合成物也包含安定劑 (stabilizer)、表面活性劑（surfactants)、平整劑 (levelers)and 光澤劑（brighteners)。 一般銅離子源自硫酸銅（CuS04 )。典型的還原劑是曱
第8頁 200405481 五、發明說明（5) 酸（formaldehyde )。典型的錯合劑是乙二胺四乙酸 (EDTA )和其鹽類。 一般的安定劑是氰胺鈉（sodium cyanamide)和 2，2 ’ 一聯此唆（2，2 ’ 一 d i p y r i d i 1 )。一般的表面活性 Triton X-114 (聚氧伸乙基異辛苯鱗）（polyoxyethylene isooctyl phenyl ether ) 〇 此組成一般的PH值是約1 〇 · 8至約1 3，可加入PH調整劑 調整PH值，例如氫氧化鈉（NaOH )或氫氧化鉀（Κ0Η )。其鲁 無電解沉積一般地在約2 0 °C到約3 5 °C之間以每分鐘2 5 nm的 >儿積速度 >儿積。另外，銅晶種層6是在酸性銅水溶液中電沉 積0 銅或銅合金7沉積在内層5上，或在有銅種晶層6時，沉 積在銅種晶層6上。銅用電化學沉積法不需要任何種晶層就 可以直接沉積在内層5，例如電鍍或無電解電鍍。適當的電 鍍成份的例子已揭露在美國申請第〇9/348,632號，其於此 作為參考。電鍍銅以用來填滿此線路及/或介層洞開口 '。
、5和6在結構的最頂端表面 機械研磨（CMP )能提供平坦 ’其能對個別的線路及/或介 如圖6所示，目前任一層4 都要被去除，舉例來說，化學 化結構，使銅結構與基材齊平 層洞達到電絕緣。
200405481 五、發明說明（6) -- 如果有需要，化學機械研磨是要沉積無電解沉積銅之 前完成磨光。 本發明用的技術是可用於單道或雙道金屬鑲嵌法結 對整體的電子結構測試電鍍的效果，所有鈀和鉑沉積 的完成可藉由簡單的濺鍍沉積在鎢基材上，此基材是六羰 基化鎢（tungsten hexacarbonyl )，可用化學氣相積 (CVD) 電鏡貫驗沒有特殊敏感的細節需注意。 為了有更好的成果，其鎢/鉑和鎢/鈀結構可以藉由沉 積一些前驅物（precursors)於鎢層頂端。其下列^步驟 可被利用。首先起始沉積_。其可以利用此基材，盆被 完成放置在低壓化學氣相沉積反應室（CVD react〇r)裡 (壓力低於1〇-6陶爾（t〇rr))，並且加熱此基材在37〇〇c~ =C的範圍。灌入惰性氣體（Ar)，帶動六羰化鎢（w (C〇)6 )蒸氣流過基材’直到薄膜厚度到達所厚度，薄膜厚 ，二般地來說5nm-30⑽。之後六幾化鶴蒸氣將停止，而將 if，内排而將基材溫度調整到所要求的溫度。視沉 所”的前驅物…其可能使用和鶴相同的沉 積 >皿度。在此日可’翻或如箭肖瓦从从 A紀刖|&物的流動，為（W ( C0 ) 6 )的 200405481 五、發明說明（7) 氣體或其他適合的載體（例如C0 )，進入一反應室而且流 過加熱的基材，直到有充分的沉積物。 於此時，當一基材被覆蓋一層連續鎢層，對鉑或鈀前 驅物的選擇有相當多自由。例如鉑，前驅物包含其羰基氯 化物（carbonyl chloride)、二乙醯二酸鉑（Pt(acac)2 (acac = ace tacetonate ) ) 、4 (三氟石彝）化顧(Pt (PF3 )
4)，和多種有機金屬包含環辛二烯 (cyclooctadienly ) 、cycloentadienly、烧基 (alky 1 )、丙烯基配位體（ai iy 1 1 igands )。對鈀來 說’前驅物適當的化合物在數量來說是較少的，然而多種 雙丙烯基混合物（bis(allyl) compounds)、環戊二烯丙 烯鈀（cyclopentadienely allyl palladdium)、和2(六 氟乙驢醋酸）|巴（（Pd(hfac)2) (hfac = hexafluoroacetoacetonatc))都是適合的。 下列非用以限定的範例可以更進一步說明本發明。 範例1 無電解銅種晶層沉積於結構上，其結構為5 〇 濺鍍 鈀，用LeaRonal Electroless Coppermerse20 溶液 1〇_的 PVD叙（Ta ) / _氧化發（Si〇2 ) /⑨⑻），此溶液pH值為 13· 00，在市面上可以買到。用此溶液的沉積速率為在25它 每分鐘沉積2 5nm。25nm銅沉積物為黏著的塗布層且適合本
第11頁
200405481 五、發明說明（8) 發明。 範例二 重複範例一步驟，其電鍍時間延長以產生5 〇 nm厚度的 銅沉積物；其為一黏著的塗布層。 範例三 銅種晶層是用電沉積法沉積在結構之上，此結構為5 〇 nm滅鑛I巴，用Sel-Rex酸銅溶液pvDIOnm的妲/二氧化石夕/ 矽，此溶液在市面上可以買到。電沉積速率在每平方公分 通10mA的速率下進行。銅沉積物於表面上的沉積厚度為 22 1 nm，是一種黏著的塗布層。 範例四 重複範例三步驟，除了其電鍍時間延長以產生6 6 3 nm 厚度的銅沉積物之外。此沉積物為一黏著的塗布層。 範例五 銅種晶層電沉積沉積在結構之上，此結構含5 ηιη的 !巴， 在驗性銅溶液沉積1 〇 nm的Ta /S i 〇2 / S i，此驗性銅溶液包 含：
五水合硫酸銅（CuS04 · 5H20 ) ............0·0 3-0.08M EDTA完整的溶液，乙二胺四乙酸（ethylene diamine
第12頁 200405481 五、發明說明（9) tetraacetic acid)或鈉，EDTA 的單、二、三 四鈉鹽（m ο η 〇、- d i、t r i、〇 r t e t r a - s 〇 d i u m salt ) ............0· 〇· 2〇M， 氫氧化鈉PH值為10.8-13。
2，2，-聯口比口定............1 O'"8 -1 0-2 M / L
Triton X-114 (聚氧伸乙基（8)異辛苯醚 (polyoxyethylene(8) i sooctylphenyl
ether ) ) ............0. 10 -0· 30mL/L
水............至1 L
溫度............2 0 - 3 5 °C 電沉積以每平方公分通7 · 8 m A進行 銅/儿積物厚度為8 7 n m，係一黏著的沉積物。 範例六 無電解鋼種晶層沉積於結構上，此結構含1 · 5 nm的銳 和CVD组/二氧化矽/矽其係由範例五相同的溶液，在5〇〜 % 65 °C，加甲酸（CHj，37%溶液）充當Cu2+離子的還原劑所 形成。此洛液沉積速率每分鐘約5 — 6 〇 n m。銅沉積厚度為 25nm之黏著塗布層且適用於本發明。 上述是舉例描述本發明。此外，上述所揭露僅為一本 發明之較佳貫施例，但是如前所述，須知本發明能應用於 其他不同的組合、變化、和環境上，且不超脫本發明的範
第13頁 200405481 五、發明說明（ίο) 疇。本文所述之實例會做進一步解釋本發明於實作上之最 佳模式，並使熟此技藝者都可利用本發明之實施例，或依 本發明於各種特別的應用或用途做各種變化。因此，本說 明並非意圖使這個發明局限於本文所揭露的形式。同樣地， 申請專利範圍係包括各種具體實施例。
第14頁 200405481 圖式簡單說明 依據本發明在不同階段的製造，圖卜6是概要圖示結 構0 絕緣材料 阻障層 種晶層 圖示元件符號說明 1、基材 3、線及/或介層洞開 5、纪及/或翻的内層 % nil 第15頁

Claims (1)

  1. 200405481 六、申請專利範圍 1. 一種電子結構包含： 一基材，該基材具有一介層洞開口（ v i a 〇 p e n i n g)的一 介電層，該介層洞開口有側壁及底部表面； 一内層，由把（palladium)、翻（platinum)和其混合物 所組成之群組中選出；以及 銅或銅合金，位於該内層之上。 2. 如申請專利範圍第1項所述之電子結構，其中該内層為 !巴。 3. 如申請專利範圍第1項所述之電子結構，其中該内層為 翻。 4. 如申請專利範圍第1項所述之電子結構，其中該内層之厚 度為約5 0埃至約5 0 0埃。 5. 如申請專利範圍第1項所述之電子結構，其中該内層之厚 度為約5 0埃至約1 0 0埃。 6. 如申請專利範圍第1項所述之電子結構，其中該介電層包 含二氧化矽。 7. 如申請專利範圍第1項所述之電子結構，其中該介層洞之 厚度為約lOOnm至約500nm。 第16頁 200405481 六、申請專利範圍 8 ·如申請專利範圍第1項所述之電子結構，其中該阻障層之 厚度為約5 n m至約2 0 0 n m。 9 ·如申請專利範圍第1項所述之電子結構，其中該阻障層由 鎢（tungsten)、鈦（titanium)、鎢合金、氮化鈦（titanium nitride)、钽（tantalum)、氮化組（tantalum nitride)、 石夕化組（tantalum si 1 icon)所組成之群組中選出。 1 0 ·如申請專利範圍第1項所述之電子結構，更進一步包含 一銅種晶層（copper seed layer)在該内層中間或在銅或 銅合金之上。 1 1 · 一種製造一電子結構的方法，包含： 在基材上形成一絕緣物質； 微影化定義和形成線及/或介層洞的凹處於絕緣材料， 内連導體物質在凹處被沉積； 在該凹處沉積一阻障層； >儿積一内層’該内層由把、鉑和其混合物所組成之群 組中選出；以及 沉積銅或銅合金在内層之上以填滿該凹處。 1 2 ·如申請專利範圍第11項所述之方法，其中該銅或銅合金 的沉積為電化學沉積物。
    第17頁 200405481 六、申請專利範圍 1 3.如申請專利範圍第11項所述之方法，更進一步包含平坦 化該結構。 1 4.如申請專利範圍第11項所述之方法，其t使該内層沉積 的方法為濺鍍法或化學氣相沉積法（C VD)。 1 5.如申請專利範圍第11項所述之方法，其中該内層為鈀。 1 6.如申請專利範圍第11項所述之方法，其中該内層為鉑。 1 7.如申請專利範圍第11項所述之方法，其中該内層之厚度 為約5 0埃至約5 0 0埃。 1 8.如申請專利範圍第11項所述之方法，其中該内層之厚度 為約5 0埃至約1 0 0埃。 1 9.如申請專利範圍第11項所述之方法，其中該介電層包含 二氧化矽。 2 0.如申請專利範圍第11項所述之方法，其中該介層洞之厚 度為約lOOnm至約500nm。 2 1.如申請專利範圍第1 1項所述之方法，其中該阻絕層之厚 III m 1»
    Μ 第18頁 200405481 六、申請專利範圍 度為約5 n m至約2 0 0 n m。 2 2.如申請專利範圍第11項所述之方法，其中該阻絕層由 鎢、鎢合金、鈦、鈦合金、氮化鈦、钽、氮化钽、氮化矽 組（tantalum silicon nitride)組成之君_組中選出。 2 3.如申請專利範圍第11項所述之方法，更進一步包含沉積 一層銅種晶層在該内層之上，該内層在銅或銅合金的中 間。 2 4.如申請專利範圍第11項所述之方法，其中使該内層沉積 的方法為濺鍍法或化學氣相沉積法。 2 5.如申請專利範圍第2 3項所述之方法，其中該晶種層的沉 積是在一無電鍍槽所形成。 2 6.如申請專利範圍第23項所述之方法，其中該晶種層的電 沉積是在一酸性銅水溶液槽所形成。 2 7. —種如申請專利範圍第1 1項所述之方法所得到的結構。 1 ΙΙ1_ί 第19頁
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