CN101981663B - 用于在底材上形成沉积金属的底层的方法和向待涂敷有金属层的底材施用的液体预处理剂 - Google Patents
用于在底材上形成沉积金属的底层的方法和向待涂敷有金属层的底材施用的液体预处理剂 Download PDFInfo
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 35
- 239000010949 copper Substances 0.000 claims abstract description 32
- 229910052802 copper Inorganic materials 0.000 claims abstract description 31
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明涉及一种用于在底材(5)上形成底层的方法，所述底层能够使金属层随后沉积，所述方法包括在包含来自乙氧基硅烷类或硅氧烷类和铜脒化物或镍脒化物的材料的浴液(7)中浸入底材。
Description
技术领域
本发明通常涉及一种底材金属化方法，并且更具体地，涉及一种用于形成能够使金属随后沉积的种子层的方法。
背景技术
形成在集成电路中的器件通常利用在底材的表面处形成的、诸如由铜构成的金属导线来互接。
对于形成这样的导线，有很多方法。一种方法是在底材上进行铜的无电镀沉积。“无电镀”沉积是一种在不使用电极的情况下进行的自催化沉积。
在进行无电镀沉积之前，必需在待金属化的底材上形成种子层，这个种子层允许底材上的良好接合并形成用于自催化反应的种子。用于形成这种类型的种子层的已知方法需要执行昂贵的操作，例如，诸如物理气相沉积(PVD)的物理沉积和诸如等离子蚀刻的蚀刻操作等系列操作。此外，通常必需几个步骤来一方面形成确保对底材的粘着的材料层，另一方面形成使金属能够自催化沉积的材料的种子。通常，确保与底材接合的材料是基于氮化钽(TaN)或者氮化钛(TiN)的材料，而使金属能够自催化反应的材料地基于钯(Pd)、锡(Sn)和/或钌(Ru)的材料。还应该注意物理沉积方法的缺点在于它们中很多需要一个底材一个底材的处理。
发明内容
因此，需要一种在底材上形成用于无电镀沉积的、对底材具有良好粘着的种子层的方法。还需要提供一种能够一起处理几个底材的方法。
此外，需要一种能够在具有强形状变化的底材上，例如在孔中共形沉积的方法。
本发明提供了一种通过在一种浴液中浸入一种或多种底材而形成催化粘着层的方法，所述浴液包括铜化合物或镍化合物与能够与底材粘着的化合物的混合物。
因此，实施方案提供了一种用于在底材上形成种子层的方法，所述种子层能够使金属层随后沉积，所述方法包括在包含来自乙氧基硅烷类或硅氧烷类和铜脒化物或镍脒化物的材料的浴液中浸入底材的步骤。
根据所述实施方案，所述随后沉积是无电镀沉积。
根据所述实施方案，所述浴液保持在范围在80℃和130℃之间的温度，优选地110℃，并且在所述浴液上方保持氢环境，以便具有范围在2000百帕和4000百帕之间的总压强，优选地3000百帕的总压强，所述底材被浸入几个小时，优选地大约8小时。
根据所述实施方案，所述材料是四乙氧基硅烷(TEOS)。
根据所述实施方案，所述TEOS中铜脒化物或者镍脒化物浓度范围在15克/升和TEOS中脒化物的饱和浓度之间。
根据所述实施方案，所述底材(5)由来自包括以下物质的组的材料制成或者涂敷：二氧化硅、硅、玻璃、苯并环丁烯(BCB)和传导材料。
根据所述实施方案，所述浸入步骤之后是通风，接着是退火步骤，所述退火步骤在氢和氩气流下，在范围在250℃和350℃之间的温度优选地大约300℃，持续几小时，优选地大约3小时。
根据所述实施方案，所述底材包括沟槽和/或孔。
根据所述实施方案，所述浴液还包括感光化合物。
另一实施方案提供了一种向待覆盖有金属层的底材施用预处理剂，所述预处理剂由来自乙氧基硅烷类或硅氧烷类和铜脒化物或镍脒化物的作用剂构成。
在下面的具体实施方案的非限制性描述中，将结合附图对本发明的前述目的、特征和优点进行详细讨论。
附图说明
图1图示了用于根据本发明的实施方案的无电镀沉积的种子层的形成步骤；
图2示出了根据本发明的实施方案的方法的流程图；
图3A到3C是图示应用所述方法以在集成电路上形成金属导线的例子的截面图；以及
图4A到4D是图示应用所述方法的实施方案以在集成电路的互连堆叠中形成传导线和孔的例子的截面图。
具体实施方式
像正常在集成电路的图形中一样，图示制造步骤的各个附图，尤其是截面图不是按照比例的。
图1图示了用于根据实施方案的无电镀沉积的种子层的形成步骤。舟皿3浸在容器1中，具有待金属化的表面或者表面部分的几个底材5布置在舟皿3中。容器1填充有浴液(bath)7，该浴液包括铜化合物和能够与底材粘着的化合物的混合物。
粘着化合物是一种乙氧基硅烷类或者硅氧烷类的化合物，例如，具有下面的半结构式的四乙氧基硅烷(TEOS)。
其中，Et表示乙基。
用作溶剂的TEOS形成与底材粘着的粗作用剂。
铜化合物是铜脒化物(copper amidinate)。例如，该铜脒化物可以是分子式[Cu(iPr-amd)]2并具有下面的半结构式的铜(N，N’-二异丙基-乙脒化物(acetamidinate))：
其中，Me表示甲基，iPr表示异丙基。应该注意，所使用的脒化物可以是任何已知类型的铜脒化物。
这个反应导致在一个底材(或多个底材)5上形成由铜和二氧化硅的紧密混合物构成的种子层。该层然后被通风，优选地，接着被退火。
图2示出了用于形成根据本发明的实施方案的无电镀种子层的方法的流程图。
在第一步骤11中，制备包含铜脒化物和TEOS的混合物的浴液。优选地，TEOS中的铜脒化物浓度将在15克/升和150克/升(高达该溶剂中的脒化物的饱和浓度)之间变化。
在步骤13，制备底材以处理底材(等离子净化……)。
在步骤15，将底材布置在舟皿中。
在步骤17，将舟皿浸在浴液中几个小时，例如2到15小时，优选地8小时。如图1中利用箭头9所示，在容器上方，保持压强范围在1000百帕和3000百帕之间(总压强范围在2000百帕和4000百帕之间)，并且优选地2000百帕(总压强3000百帕)的氢环境。在浸入期间，浴液保持在范围在80℃和130℃之间的温度，并且优选地在大约110℃的温度，以获得在底材上形成的种子层的良好粘着。
在步骤19，将舟皿取出容器并通风。
在步骤21，将保持或者没有保持在船皿中的底材退火，以使所获得的层致密化。在氢和/或氩气流下，在范围在200℃和350℃之间的温度优选地300℃，进行2小时到4小时，例如3小时退火。该步骤是可选的，因为在浸入期间形成的种子层如果暴露给空气会发生致密化。但是，退火具有加速这个现象的优点。
通过选择下面的条件：
在TEOS中的铜脒化物为25克/升；
在TEOS和铜脒化物浴液中浸入15小时；
浸入期间浴液保持110℃；
在容器上方，氢环境保持在2000百帕(总压强3000百帕)；
退火之前，将种子层暴露在空气中；以及
浸入之后，在300℃退火3小时，
发明人在底材上获得了具有大约0.3μm厚度的种子层。
图3A到3C是图示应用实施方案的种子层沉积方法以在集成电路上形成金属导线的例子的截面图。
图3A图示了涂敷有根据图1和2描述的方法形成种子层23的底材5。
在图3B图示的步骤，已经对种子层23进行了光刻，以便在该层中形成开口25并在需要导线的位置处留下种子层23的部分27。光刻可以按照常规利用掩模和/或合适的树脂进行，以获得期望尺寸的导线和/或部分27。蚀刻可以是利用氟化铁FeCl3的液体蚀刻。作为变型，可以将感光化合物加入到浴液7，以便使种子层23感光并去除光刻的某些步骤。
一旦完成了光刻，就可以进行无电镀沉积。在这里，以无电镀铜沉积为例。为了这个目的，将底材浸入到常规上包括下列成分的浴液中：
铜源，例如硫酸盐CuSO4，5H2O；
还原剂，例如甲醛(HCOH)；
PH稳定剂(例如氢氧化物)；
用于避免浴液中的任何自发铜沉积的复合剂，例如EDTA(乙二胺四乙酸，C10H16N2O8)；以及
能够提高沉积质量的添加剂，例如表面作用剂、稳定剂、湿润剂、促进剂和/或慢化剂。
在该步骤期间包含的反应将不会被进一步详细描述，这样的反应对于所属领域技术人员而言是众所周知的。
图3C图示了在图3B的结构上进行无电镀铜沉积之后获得的结果。在每个部分27上，形成了铜部分29。该铜部分29沿着与底材5的表面垂直的方向形成。铜部分29可以具有范围高达5μm的厚度。
因此，传导线可以按照光刻所预定的图案形成在底材上。在图3A到图3C的情况下，底材可以是例如由硅制成的半导体晶片，但是本发明还可以适用于在任何其他类型的底材，例如诸如玻璃板、二氧化硅(SiO2)或苯并环丁烯(BCB)层的绝缘底材上，或者在传导底材上形成铜部分。
图4A到4D是图示应用根据实施方案的方法以在集成电路的互连堆叠中形成导线和孔的例子的截面图。
在图4A中，由形成有互连层N的互连堆叠开始，该平面包括例如由BCB或者SiO2制成的绝缘层33，传导线35形成在绝缘层33上，在这里示出了沿着该结构长度方向截取的截面。
一层绝缘材料37形成在互连层N上(互连层N+1)，该绝缘材料具有被蚀刻的表面(开口39)以限定上互连层的传导材料的位置(平面N+1的导线和孔)。
在图4B图示的步骤，已经将所述结构浸在诸如图1的浴液中，接着进行上述相关的操作模式。于是，在绝缘材料的表面上和在开口39的壁和底上获得种子层41。
在图4C图示的步骤，已经从层41的位置开始进行了诸如铜的无电镀沉积。该沉积在开口39和层41上形成铜层43。
在图4D图示的步骤，已经对图4C的结构进行了化学-机械抛光(CMP)，以便暴露绝缘层37的上表面。于是获得互连层N+1。
应该理解，这种方法还适用于具有任何其他形状的底材，例如包括孔和/或沟槽的底材的金属化。根据实施方案的方法还可以在底材的表面上进行具有更复杂形状的金属化。
已经描述了本发明的具体实施方案。所属领域技术人员将会想到不同的变型和修改。具体地，这里所述的与在底材上形成铜基种子层有关的方法可以推广到其他金属，尤其是镍基种子层。用于形成原始层的浴液会包括镍脒化物以随后替换铜脒化物。
还应该注意，在铜基或镍基种子层上进行的无电镀沉积可以是有可能沉积在这种种子层上的任何已知金属的沉积。作为非限制性例子，尤其可以将铜、镍或者铂沉积在利用铜脒化物形成的种子层上。可以将铜、镍、铂或者金沉积在利用镍脒化物形成的种子层上。
此外，可以将铜基或者镍基种子层形成在具有任何一种较强或较弱形状变化的、任何其他已知的底材类型上。
根据实施方案形成的种子层还可以用作电镀沉积的种子层。
这样的变型、修改和改进旨在作为本公开的一部分，并且旨在落于本发明的精神和范围内。因此，前述描述仅仅作为例子，并不旨在限制。本发明仅受限于下面的权利要求及其等效物。
Claims (15)
1.一种用于在底材(5)上形成种子层(23)的方法，所述种子层能够使金属层随后沉积，所述方法包括在包含来自乙氧基硅烷类或硅氧烷类中的一种材料并且还包含铜脒化物或镍脒化物的浴液(7)中浸入底材的步骤。
2.根据权利要求1所述的方法，其中所述随后沉积是无电镀沉积。
3.根据权利要求1或2所述的方法，其中所述浴液(7)保持在80℃和130℃之间范围的温度，并且在所述浴液上方保持氢环境，以便具有范围在2000百帕和4000百帕之间的总压强，所述底材被浸入2到15小时。
4.根据权利要求3所述的方法，其中所述温度为110℃。
5.根据权利要求3所述的方法，其中所述总压强为3000百帕。
6.根据权利要求3所述的方法，其中所述底材被浸入8小时。
7.根据权利要求1所述的方法，其中所述材料包含四乙氧基硅烷(TEOS)。
8.根据权利要求7所述的方法，其中所述四乙氧基硅烷(TEOS)中铜脒化物或者镍脒化物浓度范围在15克/升和所述四乙氧基硅烷(TEOS)中脒化物的饱和浓度之间。
9.根据权利要求1所述的方法，其中所述底材(5)由来自包括以下物质的组的材料制成或者涂敷：二氧化硅、硅、玻璃、苯并环丁烯(BCB)和传导材料。
10.根据权利要求1所述的方法，其中所述浸入步骤之后是通风，接着是退火步骤，所述退火步骤在氢和氩气流下，在范围在250℃和350℃之间的温度，持续几小时。
11.根据权利要求10所述的方法，其中所述温度为300℃。
12.根据权利要求10所述的方法，其中所述退火步骤持续3小时。
13.根据权利要求1所述的方法，其中所述底材(5)包括沟槽和/或孔。
14.根据权利要求1所述的方法，其中所述浴液(7)还包括感光化合物。
15.一种向待涂敷有金属层的底材(5)施用的液体预处理剂，所述液体预处理剂包含来自乙氧基硅烷类或硅氧烷类中的一种材料并且还包含铜脒化物或镍脒化物。
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| PCT/FR2009/050524 WO2009125143A2 (fr) | 2008-03-28 | 2009-03-30 | Procede de formation d'une couche d'amorcage de depot d'un metal sur un substrat |
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| WO2017130373A1 (ja) * | 2016-01-29 | 2017-08-03 | 株式会社Ｊｃｕ | 基板上への回路形成方法 |
| US10410883B2 (en) | 2016-06-01 | 2019-09-10 | Corning Incorporated | Articles and methods of forming vias in substrates |
| US10794679B2 (en) | 2016-06-29 | 2020-10-06 | Corning Incorporated | Method and system for measuring geometric parameters of through holes |
| US10134657B2 (en) | 2016-06-29 | 2018-11-20 | Corning Incorporated | Inorganic wafer having through-holes attached to semiconductor wafer |
| US11078112B2 (en) | 2017-05-25 | 2021-08-03 | Corning Incorporated | Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same |
| US10580725B2 (en) | 2017-05-25 | 2020-03-03 | Corning Incorporated | Articles having vias with geometry attributes and methods for fabricating the same |
| US11554984B2 (en) | 2018-02-22 | 2023-01-17 | Corning Incorporated | Alkali-free borosilicate glasses with low post-HF etch roughness |
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| KR20210127188A (ko) | 2019-02-21 | 2021-10-21 | 코닝 인코포레이티드 | 구리-금속화된 쓰루 홀을 갖는 유리 또는 유리 세라믹 물품 및 이를 제조하기 위한 공정 |
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