TW200305293A - Method to manufacture a semiconductor-components - Google Patents

Method to manufacture a semiconductor-components Download PDF

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Publication number
TW200305293A
TW200305293A TW092101972A TW92101972A TW200305293A TW 200305293 A TW200305293 A TW 200305293A TW 092101972 A TW092101972 A TW 092101972A TW 92101972 A TW92101972 A TW 92101972A TW 200305293 A TW200305293 A TW 200305293A
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TW
Taiwan
Prior art keywords
semiconductor layer
manufacturing
substrate
carrier
laser beam
Prior art date
Application number
TW092101972A
Other languages
Chinese (zh)
Other versions
TWI226139B (en
Inventor
Volker Haerle
Berthold Hahn
Michael Fehrer
Stephan Kaiser
Frank Otte
Otte Franz
Original Assignee
Osram Opto Semiconductors Gmbh
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Filing date
Publication date
Priority claimed from DE10203795.7A external-priority patent/DE10203795B4/en
Priority claimed from DE10243757A external-priority patent/DE10243757A1/en
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of TW200305293A publication Critical patent/TW200305293A/en
Application granted granted Critical
Publication of TWI226139B publication Critical patent/TWI226139B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36Removing material
    • B23K26/40Removing material taking account of the properties of the material involved
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50Working by transmitting the laser beam through or within the workpiece
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    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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    • C30B29/403AIII-nitrides
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Abstract

This invention describes a method to manufacture a semiconductor-component, especially a thin-layer-component, where a semiconductor-layer is separated from a substrate through the irradiation with a laser-beam, which has a plateau-shaped spatial radiation-profile. In addition, the semiconductor-layer is before the separation applied on a carrier with an adapted thermal expansion-coefficient. This invention is especially suitable for semiconductor layers, which contain a nitride-compound-semiconductor.

Description

200305293 玖、發明說明 (#明_日月應救日月:發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明) 技術領尨 # # Μ #及一種半導體組件之製造方法,其中半導體層 _ ώ胃ΐί光束之照射而與基板相隔開。 先前技術 此種方、法例如已用在GaN爲主之無基板之發光二極體之 _ ίί Φ ° lit種組件包含半導體本體,半導體本體固定在載 體± ° 製成半導體本體,首先須在適當之基板上製成 半導體層’然後與載體相連接以及再由基板拆開。藉由載 體與其上所配置之半導體層之切開(例如,切鋸)而形成許 多半導體本體,其分別固定在相對應之載體上。此處重要 的是:製造半導體層所用之基板須由半導體層分開且同時 不能用作此組件中之載體。 上述製造方法之優點是:基板及載體可使用不同之材料 。各別之材料因此可在半導體層製造(一方面)及不同之操 作條件(另一方面)時針對不同之需求作各自獨立之調整。 於是可依據載體之機械性、熱性及光學特性來選取載體而 與製造半導體層用之基板所需之需求無關。 特別是以嘉晶方式製造半導體層時對嘉晶基板有許多特 殊之需求。例如,基板-及其上所施加之半導體層之晶格常 數須互相對應。此外,基板須可承受各種磊晶條件,特別 是溫度大於1 〇 〇 〇 °c時’且基板須適合用來嘉晶生長該相關 半導體材料之儘可能均勻之層。 200305293 就半導體本體之進一步加工及操作而言,載體之其它特 性(例如,導電性及導熱性)以及光電組件中之輻射穿透性 都很重要。適用於嘉晶基板之材料因此通常只能有限地作 爲該組件中之載體。最後,特別是在較貴之磊晶基板(例如 ,碳化矽基板)中値得多次地使用該基板。 就上述之製法而言,"使半導體層由基板分開”是重要的 。此種分開以雷射光來照射半導體層-基板-界面而達成。 雷射光在界面附近中被吸收而在該處使半導體材料分解。 半導體層由基板中分開例如可藉由雷射分離法(如文件 WO 98/14986中所述者)來達成。就GaN層及Gal nN層由 藍寶石基板中分開而言,可使用Q開關N d : Y A G雷射之 三倍頻率之輻射。藍寶石基板對此種波長之輻射而言是透 明的。該輻射能量在藍寶石基板及GaN半導體層之間之接 面(junction)上由大約l〇〇nm厚之界面層所吸收。大於 200mJ/cm2之脈波能量可使界面上之溫度大於850 °C。GaN 界面層在此種溫度時會分解而釋出氮,半導體層及基板之 間之連接會分開。 上述方法存在以下之危險性:在半導體層分開時由於材 料未完全分解而使基板殘留物黏附在半導體層上。例如’ 在以上述方式而與藍寶石基板相分開之GaN層上通常會存 在微小藍寶石晶粒,所謂A b p 1 a t z e r (剝落物)’’。 藍寶石殘留物之直徑是在5μπι及ΙΟΟμπι之之間。藍寶石 殘留物使半導體層之進一步加工更困難且由於藍寶石較大 之機械阻力及化學阻力而需要較高之耗費以將其去除。這 -7- 200305293 樣會使已分開之半導體層中只有一部份可繼續使用或甚至 整個層都不可使用。 即將分開之半導體層之機械穩定性通常是需要的,否則 層厚度很小時會有,,損傷"之危險性發生,特別是該層可能 會斷開或裂開。爲了達成機械上之穩定性,則適當之方式 是使半導體層(其可以是一部份已加工者)與載體形成一種 材料鎖定式之接合。此種接合至少須在一段溫度中是穩定 的’使其可承受隨後之各步驟中所產生之溫度而不會受損 。此外,在溫度變換之各種負載(其特別是發生在該組件操 作時)中此種接合亦須保持穩定。 爲了使半導體層固定在載體上,通常使用黏合材料。^ 較大之電功率時由於黏合材料之有限之導熱性及導奮 电丨生而 會發生一些問題。黏合材料之有限之耐熱性另外會使相對 應之組件之可允許之溫度範圍受限,因此亦使可能士 <最大 損耗功率受限。 發明內容 本發明之目的是提供一種半導體組件用之較佳之製造方 法,其中半導體層可藉由雷射照射而與基板相分開。 上述目的以申請專利範圍第1、2及1 3項之方法來 、 運成 。本發明其它有利之形式描述在申請專利範圍各附屬項中 本發明之設計方式是:藉由雷射束之照射使半導體磨由 基板分開,其中雷射束具有一種高台形式(特別是矩 一 t戥梯 形)之輻射外形(profile)。藉由此種輻射外形,則半 上之基板殘留物可較傳統之分離方法中者大大地減少。 200305293 所謂高台形式之輻射外形是指雷射束之一種橫向之強度 分佈’其中央區有一種定値之強度分佈,其側面之強度則 下降。中央區中之輻射強度之相對波動小於5 %。 爲了進一步改良該輻射外形,則可在雷射之後配置一種 輻射均勻器。又,亦可在半導體層上使用一適當之光學系 統’例如,透鏡系統(其可包含各種修正透鏡、減薄劑、鏡 面、遮罩結構及/或投影器),來映射該雷射束。以此種方 式可調整該材料分解時所需之能量密度而不會使雷射輻射 外形劣化。 反之’傳統之雷射分割法中所使用之雷射通常具有一高 斯(Gauss)形式之輻射外形。這會在半導體·基板-界面上造 成空間上變化較大之不均勻之場分佈,結果會造成不同程 度之材料分解度。在隨後之半導體層之分開過程中會產生 以下之危險性:在輕微(或不完全)之材料分解之位置上基 板殘留物會黏合在半導體層上。 本發明中雷射束較佳是由準分子(Excimer)雷射所產生 。準分子雷射通常具有一種高台形式(通常是梯形或長方形) 之輻射外形。此外,特別是在準分子雷射(其以稀有氣體― 鹵素化合物作爲雷射介質)中該輻射波長是在紫外光譜區 域中,其特別適合使氮化物化合物半導體被分開。此外, 準分子雷射中尖峰脈衝功率(其通常在lkW及100MW之間) 須夠大’使得在雷射束進行遮罩映射時及穿過多個透鏡之 後能量密度仍足以進行材料分解。 爲了在材料分解時達成所需之輻射強度,則脈波操作對 200305293 雷射而Η是適當的。相對於連續式操作之雷射而言亦可使 待分離之半導體層發生過熱之危險性減小。由雷射照射所 產生之熱之發散在脈波式雷射中可藉由適當地選取脈波期 間及脈波間距來作最佳化之調整。 在橫向尺寸較大之半導體層中,依序對該半導體層之相 鄰配置之各區進行照射時是有利的,使照射面之範圍不會 太大。在雷射脈衝之輻射功率已給定時,則其強度隨著照 射面之增大而變小,在輻射範圍太大時,則未超過分解門 限(t h r e s h ο 1 d )値(g|],材料分解所需之能量密度)而使半導 體層之完整地分離受到影響。 特別有利的是完成該雷射束及/或基板(其上存在著該半 導體層),使已照射之各區形成一種全平面之總配置。在時 間上相對應地(即,在該照射之時間區間中)對該照射面之 主要部份積分出一種在空間中幾乎是定値之強度分佈。由 於此種在空間中幾乎是定値之強度分佈,則已分離之半導 體層所具有之基板殘留物較少或甚至沒有該殘留物。就已 照射之各區之全平面之總配置而百,筒台形式(特別是矩形 )之空間輻射外形特別有利。 在本發明較佳之其它形式中,雷射束在半導體層或半導 體-基板-界面之位置上具有一種照射面,其縱向尺寸較橫 向尺寸大很大。較佳是縱向尺寸較橫向尺寸大5至1〇倍, 因此可形成一種線形或條形之照射面。 在平行於橫向尺寸之方向輻射時該半導體層會移動,因 此在輻射期間該線形或條形之照射面會分佈在該待分開之 -10- 200305293 整個半導體層上。在該輻射之 半導體層獲得一種定値之強度 層單純地相對於雷射束作線形 導體層及雷射束之間之相對移 定時使半導體層移動或半導體 當之移動來達成。 本發明中有利的是使雷射束. 之間之界面區上,使轄射能量 該處造成材料分解。這以下述 射束且半導體層是經由基板而: 束在半導體層中之被吸收量較: 束幾乎無損耗地穿過基板且由; 而在半導體層中被吸收。 須注意:輻射吸收未必在材; 分解亦可以下述方式達成:輻] 且隨後使所吸收之輻射能量傳; 況需要時此輻射亦可在基板中: 傳送至半導體層。 在本發明之另一外觀中,藉丨 中分開以製造半導體組件,其! 其遠離基板之此側施加(較佳是 區相對於傳統式黏合材料連接: 性及導電性。 分開過程本身較佳是依據上 間中因此亦可使受照射之 佈,另一優點是:半導體 動即已足夠。此處是指半 ,其可藉由雷射束位置固 位置固定時使雷射束作適 接照射在半導體層及基板 乎在整面上都被吸收且在 式達成:基板可透過該雷 照射。在此種配置中雷射 基板中者大很多,使雷射 靠近界面中較大之吸收率 +分解之位置上進行。材料 ί首先在另一位置上被吸收 !至材料分解之位置上。情 φ 5吸收且隨後使該輻射能量 3雷射束使半導體層由基板 ^在分開之前使半導體層以 焊接)在載體上。焊接連接 所顯現之特徵是高的導熱 ί方法之一來進行。在上述 200305293 之分開方法中焊接連接法是有利的,但本發明之範圍亦包 含一種在載體及半導體層之間所達成之黏合連接法。 較佳是使用~種含金之焊劑,例如金錫焊劑。此處特別 有利的是金成份較高之金錫焊劑,其中金成份在65λνί·%及 8 5 w t. % 之間。 此種焊劑之熔化溫度是2 7 8 t,因此較焊接電機組件時 所需之溫度還高。在電路板上焊接時之焊接溫度通常小於 2 60 °C。因此在焊接該組件時可使半導體本體不會由載體分 開。 · 又’ IG -銦焊劑適合用作焊劑,其成份在較低之起始溫度 (大約2 0 0 °C )時會相混合且混合後具有一種較高之熔化溫 度(大於6 6 0 °C )。 此種化合物例如可以下述方式製成:在半導體層上施加 一種銦層且在載體上施加一種鈀層,然後使載體及半導體 層在較大之壓力及溫度大約200 °C或更大時相接合。 當然亦可在半導體層上施加鈀層且在載體上施加銦層。鲁 此外’在半導體層及金屬層之間施加其它層時是有利的, 這些層可保護半導體層或達成一種良好之黏合作用。一種 層序列(半導體表面上之鈦層,鈦層上之鈀層及鈀層上之銦 層)在與載體上之鈀層相連接時特別有利。 就較小之接觸電阻及有利之焊接特性而言,適當之方式 是在載體上進行焊接之前在面向載體之此側上使半導體層 設有一接觸金屬層。這例如可使用鉑-金-金屬層。 在本發明之另一外觀中,須依據半導體層之熱膨脹係數 -12- 200305293 aHL及/或基板之熱膨脹係數as來選取載體之熱膨脹係數aT 且情況需要時須選取該雷射脈波之輻射外形及脈波長度。 在各熱膨脹係數進行調整時通常是使其間之差異很小,因 此在製程中所形成-或操作時所預設之溫度範圍中不會對 該半導體層及載體造成損害。特別是在製程中基板、半導 體層及載體之間之應力可大大地減小。載體中及半導體層 中形成裂痕之危險性即可大大地下降。 本發明之範圍中因此須注意:半導體層分開時所用之雷 射脈波之強度外形(pro file)通常可在雷射照射在半導體表 面之後辨認出來。在GaN半導體層分開時,在GaN解離之 後金屬鎵仍保留在表面上。本發明又顯示:在雷射光點之 各邊緣上會在GaN材料中形成裂痕,其在此材料進一步加 工時會使半導體層由其下方之載體中剝落。 目前已發現:此種剝落主要與熱效應有關。爲了在GaN 半導體層中使GaN解離,則半導體層中之局部溫度須達到 8 0 0 °C至1 〇 0 0 °C °若雷射光點之邊緣上之能量密度大大地 下降,則雷射光點內部中可達成該”分開過程”所需之溫度 ,雷射光點之直接之周圍中該半導體材料仍保持較冷。200305293 发明 Description of the invention (# 明 _ 日月 应 救 日月: Brief description of the technical field to which the invention belongs, prior technology, contents, embodiments and drawings) Technical collar ## Μ # and a method for manufacturing a semiconductor component, The semiconductor layer is separated from the substrate by the light beam. In the prior art, such methods and methods have been used in GaN-based substrateless light-emitting diodes. Ί Φ ° lit components include a semiconductor body. The semiconductor body is fixed to a carrier ± ° to make a semiconductor body. A semiconductor layer is formed on the substrate, and then it is connected to the carrier and detached from the substrate. Many semiconductor bodies are formed by cutting (for example, a saw) of a carrier and a semiconductor layer disposed thereon, which are respectively fixed on corresponding carriers. It is important here that the substrate used to make the semiconductor layer must be separated by the semiconductor layer and cannot be used as a carrier in this component at the same time. The above manufacturing method has the advantage that different materials can be used for the substrate and the carrier. Individual materials can therefore be adjusted independently for different needs during semiconductor layer manufacturing (on the one hand) and different operating conditions (on the other hand). Therefore, the carrier can be selected according to the mechanical, thermal, and optical characteristics of the carrier regardless of the requirements required for manufacturing the substrate for the semiconductor layer. In particular, there are many special requirements for Jiajing substrates when manufacturing semiconductor layers by the Jiajing method. For example, the lattice constants of the substrate and the semiconductor layer applied thereon must correspond to each other. In addition, the substrate must be able to withstand a variety of epitaxial conditions, especially at temperatures greater than 1000 ° C 'and the substrate must be suitable for the growth of the relevant semiconductor material as uniformly as possible. 200305293 For further processing and operation of the semiconductor body, other characteristics of the carrier (for example, electrical and thermal conductivity) and radiation penetration in the optoelectronic components are important. Materials suitable for Jiajing substrates can therefore only be used as a carrier in this component to a limited extent. Finally, the substrate can be used multiple times, especially in more expensive epitaxial substrates (eg, silicon carbide substrates). As for the above-mentioned production method, " separating the semiconductor layer from the substrate " is important. Such separation is achieved by irradiating the semiconductor layer-substrate-interface with laser light. The laser light is absorbed near the interface and is used there. Decomposition of semiconductor materials. The separation of the semiconductor layer from the substrate can be achieved, for example, by laser separation (as described in document WO 98/14986). For the separation of the GaN layer and the Gal nN layer from the sapphire substrate, it can be used Q-switched N d: radiation at three times the frequency of the YAG laser. The sapphire substrate is transparent to radiation of this wavelength. The radiant energy is approximately equal to the junction between the sapphire substrate and the GaN semiconductor layer. Absorbed by a 100nm thick interface layer. Pulse energy greater than 200mJ / cm2 can cause the temperature at the interface to be greater than 850 ° C. At this temperature, the GaN interface layer will decompose and release nitrogen. The semiconductor layer and the substrate The connection between them will be separated. The above method has the following dangers: when the semiconductor layer is separated, the residue of the substrate is adhered to the semiconductor layer because the material is not completely decomposed. For example, There are usually tiny sapphire grains on the separated GaN layer of the sapphire substrate, so-called A bp 1 atzer (stripping). The diameter of the sapphire residue is between 5 μm and 100 μm. The sapphire residue makes the semiconductor layer further Processing is more difficult and due to the greater mechanical and chemical resistance of sapphire, it requires a higher cost to remove it. This will result in only a part of the separated semiconductor layer that can be used continuously or even the entire layer. Do not use. The mechanical stability of the semiconductor layer to be separated is usually required, otherwise the thickness of the layer will be very small, and the risk of damage " occurs, especially the layer may be broken or cracked. In order to achieve the mechanical Stability, the appropriate way is to make the semiconductor layer (which can be part of the processed) and the carrier form a material-locked joint. This joint must be stable at least for a period of temperature Withstands the temperatures generated in subsequent steps without damage. In addition, various loads that change in temperature (which especially occur in This kind of bonding must also be stable during the operation of the module. In order to fix the semiconductor layer on the carrier, an adhesive material is usually used. ^ At higher electrical power, it will occur due to the limited thermal conductivity of the adhesive material and the induced electrical generation. Some problems. The limited heat resistance of the bonding material additionally limits the allowable temperature range of the corresponding component, and therefore limits the possible maximum power loss. SUMMARY OF THE INVENTION The object of the present invention is to provide a semiconductor device The preferred manufacturing method is used, in which the semiconductor layer can be separated from the substrate by laser irradiation. The above purpose is achieved by the methods of the patent application scope items 1, 2 and 13. Other advantageous forms of the invention are described The design method of the present invention in each subsidiary item of the scope of the patent application is: the semiconductor mill is separated from the substrate by the irradiation of a laser beam, wherein the laser beam has a radiation profile of a high platform form (especially a moment t trapezoid) profile). With this radiation profile, more than half of the substrate residue can be greatly reduced compared to the conventional separation method. 200305293 The so-called high-profile radiation profile refers to a transverse intensity distribution of the laser beam '. The central region has a fixed intensity distribution, while the intensity on its side decreases. The relative fluctuation of the radiation intensity in the central zone is less than 5%. To further improve the radiation profile, a radiation homogenizer can be provided after the laser. Also, an appropriate optical system ', such as a lens system (which may include various correction lenses, thinners, mirrors, mask structures, and / or projectors), may be used on the semiconductor layer to map the laser beam. In this way, the energy density required when the material is decomposed can be adjusted without deteriorating the shape of the laser radiation. Conversely, the laser used in the traditional laser segmentation method usually has a radiation profile in the form of a Gauss. This will cause a non-uniform field distribution with a large spatial variation on the semiconductor-substrate-interface, resulting in different degrees of material decomposition. During the subsequent separation of the semiconductor layers, the following hazards arise: substrate residues will adhere to the semiconductor layers at the location of slight (or incomplete) material decomposition. The laser beam in the present invention is preferably generated by an excimer laser. Excimer lasers usually have a radiation profile in the form of a plateau (usually trapezoidal or rectangular). In addition, especially in excimer lasers, which use a rare gas, a halogen compound, as the laser medium, the radiation wavelength is in the ultraviolet spectral region, which is particularly suitable for separating nitride compound semiconductors. In addition, the peak pulse power (usually between lkW and 100MW) in excimer lasers must be large enough so that the energy density is still sufficient for material decomposition when the laser beam is masked and after passing through multiple lenses. In order to achieve the required radiation intensity when the material is decomposed, pulse wave operation is appropriate for the 200305293 laser. Compared to continuous operation lasers, the risk of overheating of the semiconductor layer to be separated can also be reduced. The radiation of the heat generated by the laser irradiation in the pulse wave laser can be optimized by selecting the pulse wave period and the pulse wave interval appropriately. In a semiconductor layer having a large lateral size, it is advantageous to sequentially irradiate the adjacently arranged regions of the semiconductor layer, so that the range of the irradiation surface is not too large. When the radiation power of the laser pulse has been given, its intensity will decrease with the increase of the irradiation surface. When the radiation range is too large, it does not exceed the decomposition threshold (thresh ο 1 d) g (g |), material The energy density required for decomposition) affects the complete separation of the semiconductor layer. It is particularly advantageous to complete the laser beam and / or substrate (where the semiconductor layer is present), so that the irradiated areas form a total planar configuration. Correspondingly in time (that is, in the time interval of the irradiation), the main part of the irradiation surface is integrated with an intensity distribution that is almost constant in space. Due to this almost constant intensity distribution in space, the separated semiconductor layer has less or even no substrate residue. In terms of the total configuration of the entire plane of each area that has been irradiated, the shape of the space radiation (especially rectangular) in the form of a tube platform is particularly advantageous. In another preferred form of the present invention, the laser beam has an irradiation surface at the position of the semiconductor layer or the semiconductor-substrate-interface, and its longitudinal dimension is much larger than its lateral dimension. It is preferable that the longitudinal dimension is 5 to 10 times larger than the lateral dimension, so that a linear or strip-shaped irradiation surface can be formed. The semiconductor layer moves when radiating in a direction parallel to the lateral dimension, so the linear or strip-shaped irradiation surface is distributed over the entire semiconductor layer to be separated during the irradiation. A fixed intensity is obtained in the radiating semiconductor layer. The layer is simply linear relative to the laser beam. The relative shift between the conductor layer and the laser beam is accomplished by moving the semiconductor layer or the semiconductor as it is. In the present invention, it is advantageous to make the laser beam on the interface area between the laser beams and cause the radiation energy to cause material decomposition there. This is based on the following beam and the semiconductor layer passing through the substrate: the amount of the beam absorbed in the semiconductor layer is relatively small: the beam passes through the substrate with little loss; and is absorbed in the semiconductor layer. It should be noted that radiation absorption may not be in the material; decomposition can also be achieved in the following way: and then the absorbed radiant energy is transmitted; when necessary, this radiation can also be in the substrate: transmitted to the semiconductor layer. In another aspect of the present invention, a semiconductor device is manufactured by using a separate part, which! It is applied away from the side of the substrate (preferably, the area is connected to the traditional adhesive material: electrical and electrical conductivity. The separation process itself is preferably based on the upper space so it can also make the cloth irradiated. Another advantage is: semiconductor It is enough to move. Here it refers to half, which can make the laser beam properly irradiate the semiconductor layer and the substrate on the entire surface when the laser beam is fixed and fixed. It can be irradiated through the laser. In this configuration, the laser substrate is much larger, so that the laser is conducted near the interface with a larger absorption rate + decomposition position. The material is first absorbed in another position! To the material At the decomposition position, the φ 5 absorbs and then causes the radiant energy 3 laser beam to make the semiconductor layer from the substrate ^ before the semiconductor layer is soldered to the carrier). Welded connections are characterized by high thermal conductivity. In the above-mentioned 200305293 separation method, the solder connection method is advantageous, but the scope of the present invention also includes an adhesive connection method achieved between the carrier and the semiconductor layer. It is preferred to use a gold-containing flux, such as a gold-tin solder. Particularly advantageous here is a gold-tin solder with a higher gold content, in which the gold content is between 65λνί ·% and 8 5 w t.%. The melting temperature of this flux is 2 7 8 t, which is higher than the temperature required when welding motor components. The soldering temperature when soldering on circuit boards is usually less than 2 60 ° C. Therefore, the semiconductor body is not separated from the carrier when the component is soldered. · Also IG-Indium flux is suitable for use as a flux. Its components will be mixed at a lower initial temperature (about 200 ° C) and have a higher melting temperature (greater than 6 6 0 ° C) after mixing. ). Such a compound can be prepared, for example, by applying an indium layer on a semiconductor layer and a palladium layer on a carrier, and then subjecting the carrier and the semiconductor layer to a high pressure and a temperature of about 200 ° C or greater Join. Of course, it is also possible to apply a palladium layer on the semiconductor layer and an indium layer on the carrier. In addition, it is advantageous when other layers are applied between the semiconductor layer and the metal layer. These layers can protect the semiconductor layer or achieve a good adhesion. A layer sequence (a titanium layer on a semiconductor surface, a palladium layer on a titanium layer, and an indium layer on a palladium layer) is particularly advantageous when connected to a palladium layer on a carrier. In terms of small contact resistance and favorable soldering characteristics, it is appropriate to provide the semiconductor layer with a contact metal layer on the side facing the carrier before soldering on the carrier. This can use, for example, a platinum-gold-metal layer. In another aspect of the present invention, the thermal expansion coefficient aT of the carrier must be selected according to the thermal expansion coefficient of the semiconductor layer -12-200305293 aHL and / or the thermal expansion coefficient as of the substrate, and the radiation profile of the laser pulse must be selected when the situation requires And pulse length. When adjusting the coefficients of thermal expansion, the differences between them are usually small, so the semiconductor layer and the carrier will not be damaged in the temperature range formed during the process or preset in the operation. Especially in the process, the stress between the substrate, the semiconductor layer and the carrier can be greatly reduced. The risk of crack formation in the carrier and semiconductor layer can be greatly reduced. It is therefore important to note in the scope of the present invention that the intensity profile of the laser pulses used when the semiconductor layers are separated can usually be identified after the laser is irradiated onto the semiconductor surface. When the GaN semiconductor layer is separated, the metal gallium remains on the surface after the GaN is dissociated. The invention also shows that cracks will be formed in the GaN material on the edges of the laser light spot, which will cause the semiconductor layer to peel off from the carrier below it when the material is further processed. It has been found that such spalling is mainly related to thermal effects. In order to dissociate GaN in the GaN semiconductor layer, the local temperature in the semiconductor layer must reach 800 ° C to 1000 ° C ° If the energy density on the edge of the laser light point is greatly reduced, the laser light point The temperature required for the "separation process" can be achieved internally, and the semiconductor material remains relatively cold in the immediate vicinity of the laser light spot.

GaN表面上已達成之溫度在半導體層之厚度中若大大地 下降’則半導體層之載體側上在雷射光點之區域中該溫度 仍可達到4 0 0 °C。因此,由於雷射光點中及雷射光點外部 之不同之局部溫度而會在半導體層中及載體中由於半導體 材料及載體材料之不同之熱膨脹係數而形成各別之拉應力 ,其會在雷射光點邊緣上之半導體材料中造成裂痕。 -1 3- 200305293 在此種有裂痕之半導體層進一步加工時,例如會形成以 下之問題:酸會沿著裂痕爬行至半導體層下方且在該處破 壞一種鍵結金屬層。 本發明中較佳是使用熱性可調整之特殊之載體材料。在 選取該載體之熱膨脹係數aT時特別須考慮二個步驟,即, 鍵結過程及雷射照射。 在鍵結過程中’基板及其上之磊晶半導體層以及載體以 整面之方式加熱至大約4 0 0 °C之溫度且隨後又逐漸地冷卻 至室溫。本步驟中該層封包(基板/半導體層/載體)之應力預 估値是由基板及載體所決定。若基板及載體之熱膨脹係數 a s及a τ差異很大,則該層封包在冷卻時會彎曲。載體中亦 會形成裂痕,使所形成之晶片不再具有足夠之穩定性。 上述問題例如顯示在第7圖中。在該處所示之層封包2〇 中一種GaN半導體層21生長在藍寶石基板22上。半導體 層21之遠離基板22之此側設有一接觸金屬層23。接觸金 屬層2 3上在溫度4 0 0 °C時焊接一種鍵結晶圓作爲載體2 4。 現在右載體之熱膨脹係數aT較藍寶石基板之熱膨脹係 數a s小很多,則在此種鍵結步驟中會在載體2 4中形成裂 痕0 熱輻導及應 加射半層之 地雷使體中 性對射導包 部其輻半封 局於射則層 料由雷 ,了 材料由除定 體材藉消決 導板。而即 半基態離異 之,狀解差 內度冷由之 點溫持藉aT 光解保結及 射分仍鍵HL 雷之而之 a , 料多間數 時材很之係 射體小板脹 照導性基膨 射半收及熱 雷於吸料之 在大之材體 至射體載 -14- 200305293 为算;彳直。在aHL及之間有很大之差異時會形成拉應力 ,其會在雷射光點邊緣之位置上在半導體材料中形成裂痕。 第8圖說明GaN層21由藍寶石基板22分離時所形成之 問題。在層封包2 0以準分子雷射之短之雷射脈波2 6照身寸 時,雷射輻射會在GaN層21之靠近邊界之區域27中被吸 收且在該處產生800 °C至1000 °C之溫度。在半導體層21 之遠離基板之此側上及相鄰之區域2 8中仍可達到4 0 0 °C之 溫度。雷射光點外部該GaN層21及接觸金屬層23保持著 較冷之狀態。橫向中直接與雷射光點相^ &區域2 9及3 0 中之溫度較3 0 0 °C小很多。在G aN層2 1及載體2 4 (或鍵結 晶圓)之材料之間存在差異很大之熱膨脹係數時’晶晶之 GaN層21中會形成裂痕31。 爲了在載體及磊晶之半導體層中防止裂痕之形成,須選 取一種載體材料’其熱膨脹係數aT是與基板之熱膨脹係數 as及半導體層之熱膨脹係數aHL均不會相差很大。在選取 適當之熱膨脹係數aT時(以下仍將詳述)’須考慮雷射輻射 之輻射外形及脈波長度。 在本方法之較佳之形式中,載體之熱膨脹係數aT與半導 體層之熱膨脹係數aHL之差較aT與基板之熱膨脹係數as 之差還小。這樣可有效地降低或完全防止半導體層中裂痕 之形成。 適當之方式是使aT較as相差45 %或更少,較佳是相差 4 0%或更少。 對熱膨脹係數是 -1 5 - 200305293 a(Al203) = 7.5 *l〇-6K·1 之藍寶石基板而言一種熱膨脹係數aT小於a(Al2 〇3)之載體 材料特別適當,但aT須大於4.125410^1^1,特別是須大於 4 · 5 * 1 (Γ 6 K -1。 就半導體層之熱性而言,當aT與aHL之差是35%或更少 時是有利的,較佳是相差2 5 %或更少。特別是在氮化物化 合物半導體層(例如,G aN爲主之半導體層,其熱膨脹係數 韙&(0&1^) = 4.3*1〇-61<:-1)分開時,一種熱膨脹係數&丁較 MGaN)還大但小於S.SMO·6!^·1(特別是小於5.6^10-6]^1)之 載體材料較佳。 就氮化物化合物半導體層(例如,GaN層或Gal nN層)由 藍寶石基板分開而言,熱膨脹係數介於4. 125*1 (Γ6Κβ1及 5 · 8 * 1 〇 _ 6 Κ ·1,特別是介於 4 · 5 * 1 0 ·6 Κ ·1 及 5 . 6 * 1 0 ·6 Κ ·1 之間 之載體特別適合。 在選取aT時,就半導體層由基板分開而言,可選取脈波 長度較大之雷射脈波,特別是脈波長度大於1 5 n s者,此時 半導體層中不會形成裂痕。 在本發明特別有利之形式中,載體含有鉬。鉬之熱膨脹 係數是 a ( Μ 〇 ) = 5.2 1 * 1 (Γ 6 Κ ·1 其與a(GaN)之差較其與a(GaAs) = 6.4*l〇-6K-1之差小很 多。在鉬-鍵結晶圓/ G a N -半導體層/藍寶石·基板所形成之 封包中,在雷射照射時形成裂痕之問題可大大地降低。此 外,鉬足夠穩定,因此在鍵結(Β ο n d i n g )時或在鍵結溫度冷 -16- 200305293 卻至室溫時不會形成裂痕。 在本方法另一較有利之形式中,載體含有鐵-鎳-鈷-合金 ,其同樣具有一種有利之熱膨脹係數 a(Fe-Ni-Co) = 5 . 1 * 1 O^K'1 熱膨脹係數a( Wo ) = 4.7 * 1 之鎢亦已證實是載體之 一種有利材料。金屬性之載體材料由於其在鍵結過程中及 冷卻至室溫時具有韌性而對撕裂幾乎不敏感。 本發明中在選取載體之熱膨脹係數時對該半導體層之熱 膨脹係數允許一種較大之容許度(tolerance),若使用較短 之雷射脈波時。本發明中當半導體層由基板分開而選取一 種短的雷射脈波長度(特別是小於15ns)時,則載體之熱膨 脹係數aT與半導體層之熱膨脹係數aHL之差可爲35%或更 多。這特別允許使用aaaAshG.PliT6!^1之GaAs鍵結晶 圓,當使用短的雷射脈波長度時。 在本方法有利之其它形式中,在以雷射束(其具有高台形 式之輻射外形)來進行上述之分離方法時使用一種熱膨脹 係數可調整之載體。這特別是亦可包含上述有利之各種形 式,例如,使用準分子雷射(其以XeF、XeBr、XeCl、KrCl 或KrF作爲雷射活性劑),形成空間中矩形或梯形之輻射外 形,選取一種介於2 00nm及400nm之間之發射波長,另外 配置適當之光學系統及/或輻射均勻器,或在半導體層之多 個子區中依序照射該基板。 此外,如上所述,半導體層在分開之前藉由金-錫焊劑 (其中金成份較高且佔有65wt.%至85wt.%)或以鈀-銦焊劑 -17- 200305293 焊接在載體上,其中可選擇地事先在半導體層之遠離基板 之此側上施加一種金屬層’其例如含有金及/或鉑。 本方法之其它優點是:藉由使用熱性可調整之載體,則 半導體層及載體之間黏合力不足之問題即可解決,此種問 題過去在磊晶之GaN層中是以GaAs鍵結晶圓作爲載體有 關。本發明中在整個層封包中應力預估値之控制亦包含該 鍵結金屬層且就上述黏合問題而言可提供一種有效之補救。 本發明特別適用於含有氮化物化合物半導體之半導體層 。氮化物化合物半導體包含化學元素之周期表之第三及/ 或第五族之各元素之氮化物化合物,例如,GaN、A1 GaN 、:[nGaN、AlInGaN、InN或A1N。半導體層可包含不同之 氮化物化合物半導體之許多各別之層。半導體層例如可具 有傳統之接面、雙異質(hetero)結構,單一量子井結構(SQW 結構)或多重量子井結構(M Q W結構)。這些結構已爲此行 之專家所知,此處因此不必詳述。這些結構較佳是用在光 電組件(例如,發光二極體或雷射二極體中)。 須注意:本發明中含有砷化鎵、鍺、鉬、矽或以鐵、鎳 及/或鈷爲主之合金之此種載體特別適用於氮化物化合物 半導體。較佳是使用以上述材料鉬、鎢或鐵-鎳-鈷合金爲 主之載體。 例如,矽基板、碳化矽基板或氧化鋁基板、藍寶石基板 適合用作以嘉晶法製造氮化物化合物半導體層用之基板, 其中藍寶石基板對該半導體層分離時所用之雷射輻射(特 別是在紫外線光譜區中)而言是可透過的。這在半導體層分 200305293 離時可經由基板使半導體層受到照射。 本發明之方法可有利地用在薄層晶片中,其半導體層之 厚度小於5 0 μιη。該薄層晶片可以是光電晶片,特別是輻射 產生用之晶片,例如,發光二極體晶片。 本發明之其它特徵,優點將依據第丨至8圖中之實施例 來描述。 實施方式 第1圖中所示方法之第一步驟第la圖中,在基板1上施 加半導體層2,其可以是氮化物化合物半導體層,例如, I n GaN層,其以磊晶方式生長在藍寶石基板上。半導體層 2亦可包含許多各別層,其含有GaN、AIN、AlGaN、InGaN 、InN或AlInGaN且依序生長在基板1上。 下一步驟(即,第lb圖)中,半導體層2在遠離基板之此 側上設有一接觸金屬層3,藉此可在半導體層2及稍後所 施加之電性終端(例如,終端接線)之間達成一種較小之接 觸電阻。此外,該接觸金屬層3可改良該半導體層2之焊 接特性。 該接觸金屬層3例如以含金-及/或鉑之薄層形式蒸鍍或 濺鍍而成。 然後在接觸金屬層3上焊接一載體4,如第1 c圖所示。 較佳是使用一含金之焊劑作爲焊劑5,例如,使用金成份 在65wt·%及85wt.%(較佳是75wt·%)之間之金-錫-焊劑。 此種焊接連接法之特徵是高的熱導電性及在溫度交變下負 載時具有高的穩定性。 -19- 200305293 焊接連接區在接合溫度3 7 5 °C時形成,其中 之接合壓力(其小於1 · 0巴)。此種小之接合壓 半導體層時亦可與載體4達成一種連接而不會 2受到機械上之損傷。 例如,可使用GaAs晶圓作爲載體4 ’其熱膨 於藍寶石。 較佳是設有一由鉬所構成之鍵結晶圓形式之 結晶圓之熱膨脹係數a(Mo) = 5.21*1(r0Kd很接 板之熱膨脹係數a(Al2 03) = 7.5^0-6]^1,則半導 熱所感應之應力可保持很小。又’鉬是足夠堅 在鍵結時及在由鍵結溫度冷卻至室溫時在鉬-翁 不會形成裂痕。 本發明中亦可使用Ge晶圓以取代GaAs晶圍 膨脹係數近似於GaAs而幾乎無差異。但Ge晶 GaAs晶圓所具有之優點是:其較易被切鋸,特 含砷之有毒切鋸物掉下。此外,G e晶圓在機柄 例如,以200μιη厚之Ge晶圓已可達成一種足 ,反之,GaAs晶圓之厚度大於6 0 0 μπι。此處因 由硏磨而在另一步驟中使Ge晶圓變薄。最後 成本上通常較GaAs晶圓小很多。 在使用Ge晶圓時較佳是使用含金之焊劑或1 作爲焊劑。這樣可與半導體層形成一特別穩固 別有利的是使用一以金蒸鍍之Ge晶圓,其可; 有AuSb表面層。 需要一較小 力在很薄之 使半導體層 i脹係數近似 載體4。鍵 近藍寶石基 體層2中由 韌的,因此 I結晶圓中 3。Ge之熱 ^圓相對於 別是不會有 ξ上較穩定。 夠之穩定性 此亦不必藉 ,Ge晶圓在 丨吏用金本身 之連接。特 選擇性地設 -20- 200305293 在下一步驟(第1d圖)中,經由基板1以雷射束6(其具有 筒台形式之輪射外形7)照射該半導體層2。轄射能量主要 是在半導體層2中被吸收且在半導體層2及基板1之間之 界面上使材料分解’因此該基板1隨後即可取下。 本發明中重要的是:須測定該輻射外形及已耦合而入之 輻射功率,使基板1及半導體層2之間之界面上產生一足 夠使材料分解之局部性高溫,其經由半導體層之厚度而下 降,使載體4及半導體層之間之連接區5不受影響(例如, 不會熔化)。 由於材料分解所產生之大的機械性負載較佳是由焊劑層 所吸納,使半導體層(其厚度是數個μπι)可由基板分開而不 會受損。 雷射束6之橫向之輻射外形7同樣顯示在第1 d圖中。圖 中示出沿著線A - A之輻射強度分佈。輻射外形7具有一中 央區17,其中該強度是定値的。橫向中緊接該中央區17 者是側面區1 8,其強度急速下降。依據下降之形式,該輻 射外形成爲梯形(線形下降)或下降很急速時成爲矩形。 特別是X e F準分子雷射適合用作輻射源。由於準分子雷 射之高的放大率及典型之共振器幾何形式,則空間中之輻 射外形是高台形式且因此特別適合本發明。又’準分子雷 射之高的脈衝尖峰強度是在IkW至100MW之範圍中且發 射波長在紫外線光譜區中對本發明是有利的。 雷射輻射藉由適當之光學系統經由基板而集中在半導體 層2上且該處之典型之輻射面是lmmx2mm或更大。輻射 •21· 200305293 面內之強度分佈很均勻,其中能量密度可達2 0 0m J/cm2及 8 0 0 m J / c m 2之間。此種能量密度及均句之強度分佈可使半 導體層由基板分開時不會有殘渣留存。 這在實驗上例如可在藍寶石基板上之InGaN層獲得證實 。該InGaN半導體層以xeF準分子雷射(其波長是351nm 且脈波期間是2 5 n s )之脈波式雷射來照射。藍寶石基板對 此種波長之雷射而言可透過,該雷射輻射大部份在1 n G aN 半導體層中被吸收。至基板之接面上之薄界面層藉由溫度 8 0 0 °C至100(TC時之能量載入而被加熱。在此種溫度時半 導體材料在雷射光點中被分解而釋出氮且使半導體層14 及基板1 2之間之鍵結分開。 另一方式是以KrF準分子雷射來進行一種無殘渣之分割 過程。發射波長24 8nm亦在紫外光譜範圍中。在較大之輻 射橫切面30mmxl0mm時,能量密度150mJ/cm2至600mJ/ cm2之間(較佳是在150mJ/cm2及450mJ/cm2之間)即足以使 半導體層由基板無殘渣地分開。此外,發射波長大約是 2 8 2 nm、3 0 8 nm 或 2 2 2nm 之 XeBr-、XeCl-及 KrCl-準分子 雷射已證實適用於本發明。 以雷射束照射之後,基板1可取下’如第1 e圖所示,其 中半導體層2可保持在載體4上而不會有基板殘渣存在且 可繼續加工。 第2a圖是本發明之方法之第二實施例。與第1圖不同之 處是此處該半導體層2之各子區8依序受到雷射之照射。 接近長方形之各子區8以全平面方式且容易重疊地配置者 •22- 200305293 。此種重疊用來補償該輻射外形7之邊緣區18中之強度下 降。各子區以矩陣形式配置著,其中各矩陣列相對於一儘 可能均勻之強度分佈而偏移時是有利的。各子區8之另一 配置方式顯示在第2b圖中。 各子區8內之雷射束之輻射外形顯示在第3a、3b圖中。 第3a圖中該強度沿著第2a或2b圖中所示之十字軸9之X 軸而分佈。第3 b圖是強度沿著Y軸之分佈圖。此二種分 佈圖都是高台形式且分別·具有中央區1 7a、1 7b,其旁之側 面18a、18b在強度上急速地下降。 第2a圖中所示半導體層之各子區之照射所造成之強度 分佈顯示在第4圖中。其中顯示沿著此線B - B在整個輻射 時間中積分所得之強度,其在半導體層2之整面上形成一 種幾乎是定値之均勻之強度分佈,其可使半導體層2由基 板1分開而無殘渣留下。 第6圖是先前技藝中與該輻射外形相對應之方法。此處 所用之雷射(例如,頻率已變3倍之Nd : YAG雷射)具有一 幾乎是圓形之輻射面及高斯形式之輻射外形1 5。 半導體層之依序照射之區域14之與第2a或2b圖相對應 之網目形式之配置顯示在第6a圖中。 沿著十字軸9之X軸或Y軸之強度分佈(g|3,輻射外形 15)顯示在第6b圖中。由於旋轉對稱之強度分佈(由此亦可得 知圓形之輻射面),則沿著上述二軸之強度分佈幾乎相等。 強度分佈對應於高斯曲線,其最大強度在十字軸9之原點。 爲了以上述之雷射束達成該分解門限(threshold)値,則 -23- 200305293 須使雷射束聚焦。該分解門限値在輻射中心未被超越,而 在邊緣區中該能量密度對材料分解而言太小。第6a圖所示 之半導體層之網目形式之幅射中’幾乎是定値之強度分佈( 如第4圖所不者)是不能達成的。整個輻射外形上之強度變 化以及特別是輻射中心處明顯之強度最大値會在半導體層 上造成很多之強度最大値及最小値。 沿著第6 a圖中所示之線C - C對整個輻射時間積分所得 之強度曲線1 3顯示在第6 c圖中。強度曲線1 3之變化會使 材料分解發生不均勻,特別是在強度分佈之最小値處該分 ® 解門限値未被超越。 . 在材料分解時所需之能量密度未達到之這些位置上該半 導體材料保持不變。由於在這些位置之周圍發生材料分解 且在使用氮化物化合物半導體時可能發出氣體(例如’氮) ,則會形成局部性之高壓,藉此可使粒子由基板中排出。 這些粒子可黏附在未分解之半導體材料之位置上,最後仍 使基板殘留物保留在已分開之半導體層上。 · 爲了使輻射外形向前彎,在傳統之外形中可使輻射強度 進一步提高。但須承受強度最大値之位置上由於過熱使半 導體層受損之危險。 第5圖是本發明之第三實施例。其與第1、2圖不同之處 是雷射束映射在半導體層2上,以形成一種條形之輻射面 19,其具有縱向尺寸a及橫向尺寸b,其中a較b大很多 。一種相對應之輻射面在準分子雷射1 1中例如可藉由適當 之遮罩透鏡1 2來形成。縱向尺寸a較佳是較半導體層2 -24- 200305293 之相對應之尺寸還大,使半導體層2在該方向中完全被照 -射。輻射外形之側面區1 8中之強度下降因此不會顯現在該 ’’分離方法’’中,此乃因該側面區1 8位於半導體層2外部。 該半導體層2在橫縱向尺寸b之方向中照射時須移動, 使整個半導體層2均勻地被照射。在脈波寬度足夠短(典型 値是在奈秒之範圍中)之脈波式雷射中,可依序照射半導體 層2上條形之各別之面積,此乃因半導體層2繼續在各雷 射脈衝之間移動且瞬間針對此種移動而進行照射。 本發明依據各實施例所作之描述當然不是對本發明之限 制。反之,本發明中各實施例之各別外觀可廣泛地自由組 合。 圖式簡單說明 第1 a至1 e圖本發明之方法之第一實施例之圖解,其 包含5個中間步驟。 第2a、2b圖本發明之方法之第一實施例之二種形式之 圖解。 < 第3 a、3 b圖第2 a圖所示之方法中該雷射束之輻射外 形。 第4圖第2 a圖所示之方法中該強度之分佈圖。 第5圖本發明第三實施例之圖解。 第6 a〜6 c圖使用高斯形式之強度分佈時一種製法之圖 解。 第7圖載體中形成裂痕之圖解。 第8圖半導體層中形成裂痕之圖解。 -25- 200305293 相同之元件 在這些圖中以相同之參考符號來表示 主要部分之代 表符號說明 1,12 基板 2,1 4 半導體層 3 接觸金屬層 4 載體 5 焊劑 6 雷射束 7 輻射外形 8 子區 9 十字軸 13 強度曲線 1 7,1 7a,1 7b 中央區 1 8,18a,18b 側面區 19 輻射面 -26If the temperature reached on the surface of the GaN greatly decreases in the thickness of the semiconductor layer ', the temperature on the carrier side of the semiconductor layer in the region of the laser light point can still reach 400 ° C. Therefore, due to different local temperatures in the laser light spot and outside the laser light spot, separate tensile stresses will be formed in the semiconductor layer and in the carrier due to the different thermal expansion coefficients of the semiconductor material and the carrier material, which will be in the laser light. Cracks in the semiconductor material on the edge of the dot. -1 3- 200305293 During the further processing of such a cracked semiconductor layer, for example, the following problems can be formed: acid will creep along the crack to the bottom of the semiconductor layer and break a bonding metal layer there. In the present invention, it is preferable to use a special carrier material with adjustable thermal properties. When selecting the thermal expansion coefficient aT of the carrier, two steps must be taken into consideration, namely, the bonding process and laser irradiation. During the bonding process, the substrate and the epitaxial semiconductor layer and the carrier thereon are heated to a temperature of about 400 ° C in an entire surface and then gradually cooled to room temperature. In this step, the stress prediction of the layer package (substrate / semiconductor layer / carrier) is determined by the substrate and the carrier. If the thermal expansion coefficients a s and a τ of the substrate and the carrier differ greatly, the layer of the package will bend when cooled. Cracks may also form in the carrier, making the formed wafer no longer sufficiently stable. The above problem is shown in FIG. 7, for example. A GaN semiconductor layer 21 is grown on the sapphire substrate 22 in the layer package 20 shown there. A contact metal layer 23 is provided on the side of the semiconductor layer 21 remote from the substrate 22. On the contact metal layer 2 3, a bond crystal circle is welded as a carrier 2 4 at a temperature of 400 ° C. Now the thermal expansion coefficient aT of the right carrier is much smaller than the thermal expansion coefficient as of the sapphire substrate. In this bonding step, cracks will be formed in the carrier 2 4 thermal radiation and half-layer mines should be added to make the body neutral. The radiating part of the radiating guide is semi-sealed in the radiating layer, and the layer is made of lightning, and the material is deducted by the deducting body. That is to say, the half ground state is divorced, the temperature difference is low, and the temperature is maintained by the aT photolysis and the injection point is still a key to the HL thunder. When the number of materials is large, the material is very small. The semi-conducting expansion of the light-conducting base and the thermal lightning on the suction material from the large material body to the body load -14-200305293 are counted; straight. When there is a large difference between aHL and a tensile stress, it will form a crack in the semiconductor material at the edge of the laser light spot. Fig. 8 illustrates a problem that occurs when the GaN layer 21 is separated from the sapphire substrate 22. When the layer packet 20 is exposed to the short laser pulse wave 26 of the excimer laser, the laser radiation will be absorbed in the region 27 of the GaN layer 21 near the boundary and generate 800 ° C to 1000 ° C. A temperature of 400 ° C can still be reached on this side of the semiconductor layer 21 remote from the substrate and in the adjacent regions 28. Outside the laser light spot, the GaN layer 21 and the contact metal layer 23 are kept cold. In the horizontal direction, it is directly related to the laser light spot. The temperatures in the regions 29 and 30 are much lower than 300 ° C. When there is a large difference in thermal expansion coefficient between the materials of the GaN layer 21 and the carrier 2 4 (or the bonded wafer), cracks 31 are formed in the crystalline GaN layer 21. In order to prevent the formation of cracks in the carrier and the epitaxial semiconductor layer, a carrier material must be selected whose thermal expansion coefficient aT is not significantly different from the thermal expansion coefficient as of the substrate and the thermal expansion coefficient aHL of the semiconductor layer. When selecting an appropriate thermal expansion coefficient aT (which will be described in detail below) ', the radiation profile and pulse length of the laser radiation must be considered. In a preferred form of this method, the difference between the thermal expansion coefficient aT of the carrier and the thermal expansion coefficient aHL of the semiconductor layer is smaller than the difference between aT and the thermal expansion coefficient as of the substrate. This can effectively reduce or completely prevent the formation of cracks in the semiconductor layer. A suitable way is to make aT 45% or less from as, preferably 40% or less. For sapphire substrates with a thermal expansion coefficient of -1 5-200305293 a (Al203) = 7.5 * l0-6K · 1, a carrier material with a thermal expansion coefficient aT less than a (Al2 〇3) is particularly suitable, but aT must be greater than 4.125410 ^ 1 ^ 1, especially must be greater than 4 · 5 * 1 (Γ 6 K -1. In terms of the thermal properties of the semiconductor layer, it is advantageous when the difference between aT and aHL is 35% or less, preferably a difference of 2 5% or less. Especially in nitride compound semiconductor layers (for example, G aN-based semiconductor layers, the thermal expansion coefficient 韪 & (0 & 1 ^) = 4.3 * 1〇-61 <:-1) separates At the time, a carrier material with a larger thermal expansion coefficient & D than MGaN) but less than S.SMO · 6! ^ · 1 (especially less than 5.6 ^ 10-6] ^ 1) is preferred. As far as the nitride compound semiconductor layer (for example, a GaN layer or a Gal nN layer) is separated by a sapphire substrate, the thermal expansion coefficient is between 4. 125 * 1 (Γ6Κβ1 and 5 · 8 * 1 〇_ 6 κ · 1, especially Carriers between 4 · 5 * 1 0 · 6 κ · 1 and 5. 6 * 1 0 · 6 κ · 1 are particularly suitable. When selecting aT, the pulse length can be selected in terms of the separation of the semiconductor layer from the substrate. Larger laser pulses, especially those with a pulse length greater than 15 ns, will not form cracks in the semiconductor layer at this time. In a particularly advantageous form of the invention, the carrier contains molybdenum. The thermal expansion coefficient of molybdenum is a (Μ 〇) = 5.2 1 * 1 (Γ 6 κ · 1 The difference between it and a (GaN) is much smaller than the difference between it and a (GaAs) = 6.4 * l0-6K-1. In the molybdenum-bond crystal circle / G a N-semiconductor layer / sapphire · substrate package, the problem of crack formation during laser irradiation can be greatly reduced. In addition, molybdenum is sufficiently stable, so at the time of bonding (B ο nding) or at the bonding temperature Leng-16- 200305293, but no cracks will be formed at room temperature. In another advantageous form of the method, the carrier contains iron-nickel-cobalt-combination , Which also has a favorable thermal expansion coefficient a (Fe-Ni-Co) = 5. 1 * 1 O ^ K'1 thermal expansion coefficient a (Wo) = 4.7 * 1 tungsten has also proven to be a favorable material for the carrier. The metallic carrier material is hardly sensitive to tearing because of its toughness during the bonding process and when cooled to room temperature. In the present invention, when the thermal expansion coefficient of the carrier is selected, a larger thermal expansion coefficient of the semiconductor layer is allowed. Tolerance, if a shorter laser pulse is used. In the present invention, when the semiconductor layer is separated by the substrate and a short laser pulse length (especially less than 15ns) is selected, the thermal expansion coefficient aT of the carrier The difference from the thermal expansion coefficient aHL of the semiconductor layer can be 35% or more. This allows the use of a GaA bond crystalline circle of aaaAshG.PliT6! ^ 1, when using short laser pulse lengths. Other advantages of this method In the form, a laser beam (which has a radiation profile in the form of a plateau) is used to perform the above-mentioned separation method using a carrier whose coefficient of thermal expansion can be adjusted. This can especially include the above-mentioned advantageous forms, for example, Use an excimer laser (which uses XeF, XeBr, XeCl, KrCl, or KrF as the laser active agent) to form a rectangular or trapezoidal radiation profile in space. Select an emission wavelength between 200nm and 400nm, and configure it separately An appropriate optical system and / or radiation homogenizer, or sequentially irradiate the substrate in a plurality of sub-regions of the semiconductor layer. In addition, as described above, the semiconductor layer is separated by a gold-tin solder (wherein the gold component is higher and Occupies 65wt.% To 85wt.%) Or is soldered on a carrier with a palladium-indium flux-17- 200305293, wherein optionally a metal layer is applied in advance on this side of the semiconductor layer away from the substrate, which contains, for example, gold and / Or platinum. Another advantage of this method is that by using a thermally adjustable carrier, the problem of insufficient adhesion between the semiconductor layer and the carrier can be solved. In the past, this problem used GaAs bond crystal circles as the epitaxial GaN layer. Carrier-related. In the present invention, the control of the stress estimation 値 in the entire layer package also includes the bonding metal layer and can provide an effective remedy for the above-mentioned adhesion problem. The present invention is particularly applicable to a semiconductor layer containing a nitride compound semiconductor. The nitride compound semiconductor contains a nitride compound of each element of the third and / or fifth group of the periodic table of the chemical element, for example, GaN, A1 GaN, [nGaN, AlInGaN, InN, or A1N. The semiconductor layer may include many individual layers of different nitride compound semiconductors. The semiconductor layer may have, for example, a conventional junction, a double hetero structure, a single quantum well structure (SQW structure), or a multiple quantum well structure (MQ W structure). These structures are known to experts in this field and need not be detailed here. These structures are preferably used in photovoltaic components (e.g., light emitting diodes or laser diodes). It should be noted that such a carrier containing gallium arsenide, germanium, molybdenum, silicon or an alloy mainly composed of iron, nickel, and / or cobalt in the present invention is particularly suitable for a nitride compound semiconductor. It is preferable to use a carrier mainly composed of the above-mentioned materials molybdenum, tungsten or iron-nickel-cobalt alloy. For example, a silicon substrate, a silicon carbide substrate or an alumina substrate, and a sapphire substrate are suitable for use as a substrate for manufacturing a nitride compound semiconductor layer by the Jiajing method. The sapphire substrate is used for laser radiation (especially in In the ultraviolet spectrum region). This allows the semiconductor layer to be irradiated via the substrate when the semiconductor layer 200305293 is separated. The method of the present invention can be advantageously used in thin-layer wafers with a semiconductor layer having a thickness of less than 50 μm. The thin-layer wafer may be a photovoltaic wafer, particularly a wafer for radiation generation, such as a light-emitting diode wafer. Other features and advantages of the present invention will be described based on the embodiments in Figs. In the first step of the method shown in FIG. 1 in the first embodiment, in FIG. 1a, a semiconductor layer 2 is applied on a substrate 1, which may be a nitride compound semiconductor layer, for example, an I n GaN layer, which is epitaxially grown on On a sapphire substrate. The semiconductor layer 2 may also include many individual layers, which contain GaN, AIN, AlGaN, InGaN, InN, or AlInGaN and are sequentially grown on the substrate 1. In the next step (that is, FIG. 1b), the semiconductor layer 2 is provided with a contact metal layer 3 on the side far from the substrate, so that the semiconductor layer 2 and an electrical terminal (for example, terminal wiring) applied later ) To achieve a smaller contact resistance. In addition, the contact metal layer 3 can improve the soldering characteristics of the semiconductor layer 2. The contact metal layer 3 is formed by, for example, vapor deposition or sputtering in the form of a thin layer containing gold and / or platinum. A carrier 4 is then welded on the contact metal layer 3, as shown in Fig. 1c. It is preferable to use a gold-containing flux as the flux 5, for example, a gold-tin-flux having a gold content between 65 wt.% And 85 wt.% (Preferably 75 wt.%). This solder connection method is characterized by high thermal conductivity and high stability under load under temperature change. -19- 200305293 Welded connection zone is formed at a joining temperature of 3 7 5 ° C, where the joining pressure (which is less than 1.0 bar). When such a small bonding pressure is applied to the semiconductor layer, a connection with the carrier 4 can also be achieved without being mechanically damaged. For example, a GaAs wafer can be used as the carrier 4 'which is thermally expanded to sapphire. The thermal expansion coefficient a (Mo) = 5.21 * 1 (r0Kd is very close to the thermal expansion coefficient a (Al2 03) = 7.5 ^ 0-6] ^ 1 , The stress induced by semi-thermal conduction can be kept small. Also, molybdenum is strong enough to prevent cracks from forming in molybdenum-ontide during bonding and cooling from the bonding temperature to room temperature. Ge can also be used in the present invention. Instead of GaAs, the wafer has a coefficient of expansion similar to that of GaAs with almost no difference. However, the advantages of Ge crystal GaAs wafers are that they are easier to be sawed, and toxic arsenic that specifically contains arsenic falls off. In addition, G The e-wafer is in the handle. For example, a 200 μm thick Ge wafer can already reach a sufficient level. On the contrary, the GaAs wafer has a thickness greater than 600 μm. Here, the Ge wafer is changed in another step due to honing. Thin. Finally, the cost is usually much smaller than GaAs wafers. When using Ge wafers, it is better to use gold-containing flux or 1 as the flux. This can form a particularly stable with the semiconductor layer. It is advantageous to use a gold vaporization. A plated Ge wafer, which can have an AuSb surface layer. A small force is needed to make the semiconductor layer very thin The expansion coefficient of i is similar to that of carrier 4. The bond near the sapphire substrate layer 2 is tough, so the I crystal circle is 3. The thermal circle of Ge is relatively stable compared to others. It is not necessary to borrow this. The Ge wafer is connected with gold itself. It is specifically set to -20-200305293. In the next step (Figure 1d), the laser beam 6 (which has a round shape in the form of a cylinder table) is passed through the substrate 1 7) Irradiate the semiconductor layer 2. The radiation energy is mainly absorbed in the semiconductor layer 2 and decomposes the material at the interface between the semiconductor layer 2 and the substrate 1. Therefore, the substrate 1 can be subsequently removed. Important in the present invention It is necessary to determine the radiation profile and the radiated power that has been coupled in, so that the interface between the substrate 1 and the semiconductor layer 2 generates a localized high temperature sufficient to decompose the material, which decreases through the thickness of the semiconductor layer, so that The connection area 5 between the carrier 4 and the semiconductor layer is not affected (for example, it will not melt). The large mechanical load due to material decomposition is preferably absorbed by the flux layer, so that the semiconductor layer (the thickness of which is several digits) Μπι) by the substrate Separate without damage. The lateral radiation profile 7 of the laser beam 6 is also shown in Figure 1d. The figure shows the radiation intensity distribution along the line A-A. The radiation profile 7 has a central region 17, The intensity is fixed. The one next to the central area 17 in the horizontal direction is the side area 18, whose intensity decreases rapidly. Depending on the form of the decline, the radiation profile becomes trapezoidal (linear decline) or rectangular when the decline is rapid. Special X e F excimer laser is suitable for use as a radiation source. Due to the high magnification of the excimer laser and the typical resonator geometry, the shape of the radiation in space is a plateau and is therefore particularly suitable for the present invention. The high pulse spike intensity of the excimer laser is in the range of 1 kW to 100 MW and the emission wavelength is in the ultraviolet spectrum region, which is advantageous to the present invention. Laser radiation is concentrated on the semiconductor layer 2 through a substrate by a suitable optical system and a typical radiation surface there is 1 mm × 2 mm or more. Radiation • 21 · 200305293 The intensity distribution in the plane is very uniform, among which the energy density can reach between 200 m J / cm2 and 800 m J / c m 2. This kind of energy density and uniform intensity distribution allows no residue to remain when the semiconductor layer is separated from the substrate. This can be experimentally confirmed, for example, on an InGaN layer on a sapphire substrate. The InGaN semiconductor layer is irradiated with a pulsed laser of xeF excimer laser (whose wavelength is 351 nm and the pulse period is 2 5 n s). The sapphire substrate is transparent to lasers of this wavelength, and most of the laser radiation is absorbed in the 1 n G aN semiconductor layer. The thin interface layer on the interface to the substrate is heated by the energy loading at a temperature of 80 ° C to 100 ° C. At this temperature, the semiconductor material is decomposed in the laser light spot to release nitrogen and Separate the bond between the semiconductor layer 14 and the substrate 12. Another method is to use a KrF excimer laser to perform a residue-free segmentation process. The emission wavelength of 24 8nm is also in the ultraviolet spectral range. In larger radiation When the cross section is 30mmx10mm, the energy density between 150mJ / cm2 and 600mJ / cm2 (preferably between 150mJ / cm2 and 450mJ / cm2) is enough to separate the semiconductor layer from the substrate without residue. In addition, the emission wavelength is about 2 XeBr-, XeCl- and KrCl- excimer lasers of 8 2 nm, 308 nm or 22 nm have proven to be suitable for the present invention. After irradiation with a laser beam, the substrate 1 can be removed 'as shown in Figure 1e The semiconductor layer 2 can be held on the carrier 4 without the presence of substrate residues and can be processed further. Figure 2a is a second embodiment of the method of the present invention. The difference from Figure 1 is that the semiconductor is here The sub-areas 8 of layer 2 are sequentially illuminated by the laser. Sub-region 8 is arranged in a full-plane manner and is easily overlapped • 22-200305293. This overlap is used to compensate for the decrease in intensity in the edge region 18 of the radiation profile 7. Each sub-region is arranged in a matrix form, with each matrix column It is advantageous when shifting relative to an intensity distribution that is as uniform as possible. Another arrangement of each sub-region 8 is shown in Figure 2b. The radiation profile of the laser beam in each sub-region 8 is shown in Sections 3a, Figure 3b. The intensity in Figure 3a is distributed along the X axis of the cross axis 9 shown in Figure 2a or 2b. Figure 3b is the distribution of intensity along the Y axis. Both types of distribution diagrams are It is in the form of a platform and has a central area 17a, 17b, respectively, and the side surfaces 18a, 18b rapidly decrease in intensity. The intensity distribution caused by the irradiation of each sub-region of the semiconductor layer shown in Fig. 2a is shown in Figure 4. It shows the intensity integrated along this line B-B over the entire radiation time, which forms a nearly constant uniform intensity distribution on the entire surface of the semiconductor layer 2, which enables the semiconductor layer 2 It is separated by the substrate 1 without residue. Figure 6 is a prior art The method corresponding to this radiation profile. The laser used here (for example, Nd: YAG laser whose frequency has been tripled) has a nearly circular radiation surface and a radiation profile in Gaussian form 15. Semiconductors The arrangement of the mesh form corresponding to Figure 2a or 2b of the sequentially illuminated area 14 of the layer is shown in Figure 6a. The intensity distribution (g | 3, radiation profile along the X or Y axis of the cross axis 9) 15) It is shown in Fig. 6b. Due to the rotationally symmetrical intensity distribution (the circular radiation surface can also be obtained), the intensity distributions along the above two axes are almost equal. The intensity distribution corresponds to a Gaussian curve, the maximum intensity of which is at the origin of the cross axis 9. In order to achieve the threshold 値 with the laser beam described above, -23- 200305293 must focus the laser beam. The decomposition threshold 値 is not exceeded at the center of the radiation, while the energy density is too small for material decomposition in the fringe region. In the radiation of the mesh form of the semiconductor layer shown in Fig. 6a, the almost constant intensity distribution (as shown in Fig. 4) cannot be achieved. The change in the intensity of the entire radiation profile and especially the obvious maximum intensity at the center of the radiation will cause a lot of maximum and minimum intensity on the semiconductor layer. The intensity curve 1 3 obtained by integrating the entire radiation time along the line C-C shown in Fig. 6a is shown in Fig. 6c. Changes in the intensity curve 13 will cause non-uniform decomposition of the material, especially at the minimum point of the intensity distribution. The solution threshold is not exceeded. The semiconductor material remains unchanged at those locations where the energy density required for material decomposition does not reach. Since material decomposition occurs around these locations and a gas (e.g., 'nitrogen') may be emitted when a nitride compound semiconductor is used, a localized high pressure is formed, thereby allowing particles to be discharged from the substrate. These particles can adhere to the position of the undecomposed semiconductor material, leaving the substrate residue on the separated semiconductor layer. · In order to bend the radiation profile forward, the radiation intensity can be further increased in the traditional outer shape. However, it must withstand the risk of damage to the semiconductor layer due to overheating at the location with the highest strength. Fig. 5 is a third embodiment of the present invention. The difference from Figs. 1 and 2 is that the laser beam is mapped on the semiconductor layer 2 to form a strip-shaped radiation surface 19 having a longitudinal dimension a and a lateral dimension b, where a is much larger than b. A corresponding radiation surface in the excimer laser 11 can be formed, for example, by a suitable mask lens 12. The longitudinal dimension a is preferably larger than the corresponding dimension of the semiconductor layer 2 -24-200305293, so that the semiconductor layer 2 is completely illuminated in this direction. The decrease in intensity in the side region 18 of the radiation profile does not appear in the '' separation method ', because the side region 18 is located outside the semiconductor layer 2. The semiconductor layer 2 must be moved during irradiation in the direction of the horizontal and vertical dimensions b, so that the entire semiconductor layer 2 is uniformly irradiated. In pulse lasers with sufficiently short pulse widths (typically in the nanosecond range), the individual areas of the stripe on the semiconductor layer 2 can be sequentially illuminated, because the semiconductor layer 2 continues to The pulses move between the pulses and are irradiated in response to such movements instantly. The description of the present invention based on the embodiments is of course not a limitation of the present invention. On the contrary, the respective appearances of the embodiments of the present invention can be widely freely combined. Brief Description of the Drawings Figures 1a to 1e are diagrams of a first embodiment of the method of the present invention, which includes 5 intermediate steps. Figures 2a and 2b are diagrams illustrating two forms of the first embodiment of the method of the present invention. < The radiation shape of the laser beam in the method shown in Figs. 3a, 3b and Fig. 2a. The intensity distribution in the method shown in Fig. 4 and Fig. 2a. Fig. 5 is a diagram of a third embodiment of the present invention. Figures 6a to 6c are diagrams of a method when using the Gaussian intensity distribution. Figure 7. Illustration of crack formation in the carrier. FIG. 8 is an illustration of crack formation in a semiconductor layer. -25- 200305293 Identical components are indicated by the same reference symbols in these drawings. The description of the main part of the symbol 1,12 substrate 2,1 4 semiconductor layer 3 contact metal layer 4 carrier 5 flux 6 laser beam 7 radiation profile 8 Sub-area 9 Cross axis 13 Intensity curve 1 7, 1 7a, 1 7b Central area 1 8, 18a, 18b Side area 19 Radiation surface -26

Claims (1)

200305293 拾、申請專利範圍 1. 一種半導體組件之製造方法,其半導體層(2)藉由雷射束 (6)之照射而由基板(1)分離,其特徵爲:雷射束(6)具有 一種空間中是高台形式之輻射外形(7 )。 2. —種半導體組件之製造方法,其半導體層(2)藉由雷射束 (6)之照射而由基板(1)分離,其特徵爲:雷射束(6)由準 分子雷射所產生。 3 .如申請專利範圍第1或2項之製造方法,其中準分子雷 射含有一種稀有氣體-鹵素-化合物,特別是XeF、XeBr 、XeCl、KrCl或KrF,作爲雷射活性劑。 4 .如申請專利範圍第2或3項之製造方法,其中雷射束(6) 具有一空間中是高台形式之輻射外形(7)。 5 .如申請專利範圍第1至4項中任一項之製造方法,其中 雷射束(6)具有一空間中是矩形或梯形之輻射外形。 6 .如申請專利範圍第1至5項中任一項之製造方法,其中 雷射束(6 )由一種脈波式操作之雷射所產生。 7 .如申請專利範圍第1至6項中任一項之製造方法,其中 雷射束(6)之波長介於200nm及400nm之間。 8 ·如申請專利範圍第1至7項中任一項之製造方法,其中 雷射束(6)集中在半導體層(2)上,使已照射之區域內部 中該由雷射束(6)所產生之能量密度介於i〇〇mj/cm2及 1000mJ/cm2’ 特別是在 i50mJ/cm2 及 800mJ/cm2 之間。 9 ·如申請專利範圍第1至8項中任一項之製造方法,其中 半導體層(2)之多個子區(8)依序被照射。 200305293 1 0 ·如申請專利範圍第9項之製造方法,其中各子區(8)以 全平面方式配置,使已照射之半導體層(2)之主要部份 在時間上累積而產生一種空間上幾乎是定値之強度分 佈(1 〇)。 1 1 ·如申請專利範圍第1至1 0項中任一項之製造方法’其 中雷射束(6)在半導體層(2)之位置上具有一縱向尺寸(a) 及橫向尺寸(b)之輻射面,縱向尺寸(a)較橫向尺寸(b)大 很多,半導體層(2)在沿著橫向尺寸(b)之方向照射時相 對於雷射束(6 )而移動。 1 2 ·如申請專利範圍第1至1 1項中任一項之製造方法,其 中基板(1)對雷射束(6)而言至少一部份可透過且半導體 層(2)經由基板(1)而被照射。 13. —種半導體組件之製造方法,其半導體層(2)藉由雷射 束(6)之照射而由基板(1)分離,其特徵爲:在由基板(1) 分離之前該半導體層(2)以遠離基板(1)之此側施加(較佳 是焊接)在載體(4)上。 14. 如申請專利範圍第13項之製造方法,其中雷射束(6) 被脈波化。 1 5 .如申請專利範圍第1 3或1 4項之製造方法,其中依據雷 射脈波之輻射外形及/或脈波長度以及半導體層之熱膨 脹係數aHL及基板之熱膨脹係數as來選取載體之熱膨脹 係數aT,以便在製程中使基板、半導體層及載體之間之 應力降低。 1 6 .如申請專利範圍第1 5項之製造方法,其中選取載體之 -28- 200305293 熱膨脹係數aT與半導體層之熱膨脹係數aH ι之差使小於 aT與基板之熱膨脹係數as之差。 1 7 .如申請專利範圍第1 5或1 6項之製造方法,其中載體之 熱膨脹係數aT與基板之熱膨脹係數as之差是45 %或更 少,較佳是4 0 %或更少。 1 8 .如申請專利範圍第1 5至1 7項中任一項之製造方法,其 中載體之熱膨脹係數aT與半導體層之熱膨脹係數aHlj之 差是3 5 %或更少,較佳是2 5 °/。或更少。 1 9 .如申請專利範圍第1 5至1 8項中任一項之製造方法,其 中載體之熱膨脹係數介於4.3*1(Γ6Κ^及5.940^1^1之 間,較佳是介於4 · 6 * 1 (Γ 6 K」及5 · 3 Μ 0 _6 K」之間。 2 0 .如申請專利範圍第1 3至1 9項中任一項之製造方法,其 中載體(4)含有砷化鎵、矽、銅、鐵、鎳及/或鈷。 2 1 .如申請專利範圍第1 3至2 0項中任一項之製造方法,其 中載體含有鉬。 2 2 .如申請專利範圍第1 3至2 1項中任一項之製造方法,其 中載體含有鐵-鎳-鈷-合金。 2 3 .如申請專利範圍第1 3至2 2項中任一項之製造方法,其 中載體含有鎢。 2 4 .如申請專利範圍第1 3至2 3項中任一項之製造方法,其 中載體含有鍺(Ge)。 2 5 .如申請專利範圍第1 4至2 4項中任一項之製造方法,其 中爲了使半導體層由基板中分開,雷射脈波之脈波長度 須選擇成較大,特別是大於1 5 n s。 -29- 200305293 2 6 .如申請專利範圍第1 5至2 5項中任一項之製造方法’其 中載體之熱膨脹係數aT與半導體層之熱膨脹係數aHL之 差是3 5 %或更多,就半導體層由基板分開而言須選取脈 波長度較短之雷射脈波’特別是脈波長度小於1 5 n s者。 2 7 .如申請專利範圍第1 3至2 6項中任一項之製造方法,其 中半導體層(2)藉由焊劑(其含有金及/或錫或鈀及/或銦) 而焊接在載體(4 )上。 2 8 .如申請專利範圍第1 3至2 7項中任一項之製造方法,其 中在半導體層(2)與載體(4)連接之前在半導體層(2)之遠 離基板(1 )之此側上施加一種金屬層。 2 9 .如申請專利範圍第2 8項之製造方法,其中該金屬層含 有金及/或鉑。 3 0 .如申請專利範圍第1至2 9項中任一項之製造方法,其 中半導體層(2)具有多個子(sub)層。 3 1 .如申請專利範圍第1至3 0項中任一項之製造方法,其 中半導體層(2)或其至少一個子層含有氮化物化合物半 導體。 3 2 ·如申請專利範圍第3 1項之製造方法,其中氮化物化合 物半導體是第三及/或第五族之元素所形成之氮化物化 合物。 3 3 .如申請專利範圍第3 1或3 2項之製造方法,其中半導體 層(2)或至少一個子層含有 InxAlyGa^x.yN、〇$x$l、〇5ySl 且 x + ySl,特別是 GaN、AlGaN、InGaN、AlInGaN、AIN 或 I nN o -30- 200305293 3 4 .如申請專利範圍第1至3 3項中任一項之製造方法,其 中基板(1 )含有矽、碳化矽或氧化鋁,特別是藍寶石。 3 5 .如申請專利範圍第1 3至3 4項中任一項之製造方法,其 中半導體層(2 )藉由申請專利範圍第1至1 2項中任一項 之方法而由基板(1)分開。 3 6 .如申請專利範圍第1至2 3項中任一項之製造方法,其 中半導體層(2)藉由磊晶法而施加在基板(1)上。 3 7 .如申請專利範圍第1至3 6項中任一項之製造方法,其 中半導體層(2)之厚度小於或等於50μιη。 3 8 .如申請專利範圍第1至3 7項中任一項之製造方法,其 中半導體組件是薄層組件,基板之至少一部份在半導體 層已生長之後由半導體層中去除。 3 9 .如申請專利範圍第1至3 8項中任一項之製造方法,其 中半導體組件是光電組件,特別是輻射產生用之組件, 例如發光二極體200305293 Patent application scope 1. A method for manufacturing a semiconductor device, wherein a semiconductor layer (2) is separated from a substrate (1) by irradiation of a laser beam (6), and is characterized in that the laser beam (6) has One type of space is a radiation profile in the form of a plateau (7). 2. —A method for manufacturing a semiconductor device, wherein a semiconductor layer (2) is separated from a substrate (1) by irradiation of a laser beam (6), and is characterized in that the laser beam (6) is emitted by an excimer laser produce. 3. The manufacturing method according to item 1 or 2 of the patent application scope, wherein the excimer laser contains a rare gas-halogen-compound, especially XeF, XeBr, XeCl, KrCl or KrF as a laser active agent. 4. The manufacturing method according to item 2 or 3 of the scope of patent application, wherein the laser beam (6) has a radiation profile (7) in the form of a platform in a space. 5. The manufacturing method according to any one of claims 1 to 4, wherein the laser beam (6) has a rectangular or trapezoidal radiation profile in a space. 6. The manufacturing method according to any one of claims 1 to 5, wherein the laser beam (6) is generated by a pulse-operated laser. 7. The manufacturing method according to any one of claims 1 to 6, wherein the wavelength of the laser beam (6) is between 200 nm and 400 nm. 8 · The manufacturing method according to any one of claims 1 to 7, wherein the laser beam (6) is concentrated on the semiconductor layer (2), so that the laser beam (6) should be inside the illuminated area. The energy density produced is between 100mJ / cm2 and 1000mJ / cm2 ', especially between i50mJ / cm2 and 800mJ / cm2. 9. The manufacturing method according to any one of claims 1 to 8, wherein a plurality of sub-regions (8) of the semiconductor layer (2) are sequentially irradiated. 200305293 1 0 · The manufacturing method according to item 9 of the scope of patent application, in which each sub-region (8) is arranged in a full-plane manner, so that the main part of the irradiated semiconductor layer (2) accumulates in time to generate a kind of space Almost constant intensity distribution (10). 1 1 · The manufacturing method according to any one of claims 1 to 10 in the scope of patent application, wherein the laser beam (6) has a longitudinal dimension (a) and a lateral dimension (b) at the position of the semiconductor layer (2) The longitudinal dimension (a) of the radiation surface is much larger than the lateral dimension (b). The semiconductor layer (2) moves relative to the laser beam (6) when illuminated in the direction of the lateral dimension (b). 1 2 · The manufacturing method according to any one of claims 1 to 11 in which the substrate (1) is transparent to the laser beam (6) and the semiconductor layer (2) passes through the substrate ( 1) while being irradiated. 13. A method for manufacturing a semiconductor device, wherein a semiconductor layer (2) is separated from a substrate (1) by irradiation of a laser beam (6), and the semiconductor layer (2) is characterized in that the semiconductor layer (2) is separated before being separated by the substrate (1) ( 2) Apply (preferably solder) to the carrier (4) on this side away from the substrate (1). 14. The manufacturing method according to item 13 of the patent application, wherein the laser beam (6) is pulsed. 15. The manufacturing method according to item 13 or 14 of the scope of patent application, wherein the carrier is selected according to the radiation profile and / or pulse length of the laser pulse wave and the thermal expansion coefficient aHL of the semiconductor layer and the thermal expansion coefficient as of the substrate. Coefficient of thermal expansion aT in order to reduce the stress between the substrate, the semiconductor layer and the carrier during the manufacturing process. 16. The manufacturing method according to item 15 of the scope of patent application, wherein the difference between the thermal expansion coefficient aT of the carrier and the thermal expansion coefficient aH ι of the semiconductor layer is selected to be smaller than the difference between the thermal expansion coefficient as of aT and the substrate. 17. The manufacturing method according to item 15 or 16 of the scope of patent application, wherein the difference between the thermal expansion coefficient aT of the carrier and the thermal expansion coefficient as of the substrate is 45% or less, preferably 40% or less. 18. The manufacturing method according to any one of claims 15 to 17 in the scope of patent application, wherein the difference between the thermal expansion coefficient aT of the carrier and the thermal expansion coefficient aHlj of the semiconductor layer is 35% or less, preferably 2 5 ° /. Or less. 19. The manufacturing method according to any one of items 15 to 18 in the scope of patent application, wherein the thermal expansion coefficient of the carrier is between 4.3 * 1 (Γ6Κ ^ and 5.940 ^ 1 ^ 1, preferably between 4 · 6 * 1 (Γ 6 K ″ and 5 · 3 Μ 0 _ 6 K ″. 2 0. The manufacturing method according to any one of claims 13 to 19 in the patent application scope, wherein the carrier (4) contains arsenic Gallium, silicon, copper, iron, nickel, and / or cobalt. 2 1. The manufacturing method according to any one of claims 13 to 20 in the scope of patent application, wherein the carrier contains molybdenum. 2 2. The manufacturing method according to any one of items 13 to 21, wherein the carrier contains an iron-nickel-cobalt-alloy. 2 3. The manufacturing method according to any one of claims 13 to 22, wherein the carrier contains Tungsten. 2 4. The manufacturing method according to any one of claims 13 to 23, wherein the carrier contains germanium (Ge). 2 5. Such as any one of claims 14 to 24, In the manufacturing method, in order to separate the semiconductor layer from the substrate, the pulse length of the laser pulse must be selected to be larger, especially greater than 15 ns. -29- 200305293 2 6. The manufacturing method according to any one of items 15 to 25, wherein the difference between the thermal expansion coefficient aT of the carrier and the thermal expansion coefficient aHL of the semiconductor layer is 35% or more, and a pulse must be selected for the separation of the semiconductor layer from the substrate. Laser pulses with shorter wave lengths, especially those with pulse lengths less than 15 ns. 2 7. The manufacturing method according to any one of claims 13 to 26 in the patent application scope, wherein the semiconductor layer (2) is borrowed Soldering on the carrier (4) with a flux (which contains gold and / or tin or palladium and / or indium). 2 8. The manufacturing method according to any one of claims 13 to 27, wherein Before the semiconductor layer (2) is connected to the carrier (4), a metal layer is applied on the side of the semiconductor layer (2) away from the substrate (1). 2 9. The manufacturing method according to item 28 of the scope of patent application, wherein The metal layer contains gold and / or platinum. 30. The manufacturing method according to any one of claims 1 to 29, wherein the semiconductor layer (2) has a plurality of sub-layers. 3 1. If a patent is applied The manufacturing method of any one of items 1 to 30, wherein the semiconductor layer (2) or at least one of its sublayers There are nitride compound semiconductors. 3 2 · The manufacturing method according to item 31 of the scope of patent application, wherein the nitride compound semiconductor is a nitride compound formed by elements of the third and / or fifth group. 3 3. The manufacturing method of the item 31 or 32, wherein the semiconductor layer (2) or at least one sublayer contains InxAlyGa ^ x.yN, 〇 $ x $ l, 〇5ySl, and x + ySl, especially GaN, AlGaN, InGaN , AlInGaN, AIN, or I nN o -30- 200305293 3 4. The manufacturing method according to any one of claims 1 to 33, wherein the substrate (1) contains silicon, silicon carbide or alumina, especially sapphire . 35. The manufacturing method according to any one of the claims 13 to 34, wherein the semiconductor layer (2) is produced by the substrate (1) by the method according to any one of the claims 1 to 12, )separate. 36. The manufacturing method according to any one of claims 1 to 23, wherein the semiconductor layer (2) is applied on the substrate (1) by an epitaxial method. 37. The manufacturing method according to any one of claims 1 to 36, wherein the thickness of the semiconductor layer (2) is less than or equal to 50 μm. 38. The manufacturing method according to any one of claims 1 to 37, wherein the semiconductor device is a thin-layer device, and at least a part of the substrate is removed from the semiconductor layer after the semiconductor layer has grown. 39. The manufacturing method according to any one of claims 1 to 38, wherein the semiconductor component is a photovoltaic component, especially a component for radiation generation, such as a light emitting diode
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI226139B (en) 2002-01-31 2005-01-01 Osram Opto Semiconductors Gmbh Method to manufacture a semiconductor-component
US6841802B2 (en) 2002-06-26 2005-01-11 Oriol, Inc. Thin film light emitting diode
CN100595937C (en) 2002-08-01 2010-03-24 日亚化学工业株式会社 Semiconductor light emitting device and light emitting device
KR20110010839A (en) * 2003-01-31 2011-02-07 오스람 옵토 세미컨덕터스 게엠베하 Thin-film semiconductor component and production method for said component
KR101247727B1 (en) 2003-01-31 2013-03-26 오스람 옵토 세미컨덕터스 게엠베하 Method for producing a semiconductor component
US8368092B2 (en) * 2004-01-26 2013-02-05 Osram Opto Semiconductors Gmbh Thin film LED comprising a current-dispersing structure
US7202141B2 (en) * 2004-03-29 2007-04-10 J.P. Sercel Associates, Inc. Method of separating layers of material
JP4653804B2 (en) * 2004-04-29 2011-03-16 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Light emitting semiconductor chip manufacturing method and semiconductor chip
KR100595884B1 (en) * 2004-05-18 2006-07-03 엘지전자 주식회사 Method for manufacturing semiconductor device of Nitride chemical
JP4906256B2 (en) * 2004-11-10 2012-03-28 株式会社沖データ Manufacturing method of semiconductor composite device
US7341878B2 (en) * 2005-03-14 2008-03-11 Philips Lumileds Lighting Company, Llc Wavelength-converted semiconductor light emitting device
DE102005025416A1 (en) * 2005-06-02 2006-12-14 Osram Opto Semiconductors Gmbh Luminescence diode chip with a contact structure
DE102005055293A1 (en) * 2005-08-05 2007-02-15 Osram Opto Semiconductors Gmbh Method for producing semiconductor chips and thin-film semiconductor chip
DE102005047152A1 (en) * 2005-09-30 2007-04-12 Osram Opto Semiconductors Gmbh Epitaxial substrate, process for its preparation and method for producing a semiconductor chip
DE102007004303A1 (en) 2006-08-04 2008-02-07 Osram Opto Semiconductors Gmbh Thin-film semiconductor device and device composite
DE102007004304A1 (en) 2007-01-29 2008-07-31 Osram Opto Semiconductors Gmbh Thin-film light emitting diode chip, has layer stack made of primary radiation surfaces lying opposite to each other so that thin-film light emitting diode chip has two primary radiation directions
JP2009099675A (en) * 2007-10-15 2009-05-07 Showa Denko Kk Method of manufacturing light emitting diode, light emitting diode, and lamp
DE102008050573A1 (en) 2008-10-06 2010-04-08 Osram Opto Semiconductors Gmbh Method for producing an optoelectronic semiconductor component and optoelectronic semiconductor component
CN101740331B (en) * 2008-11-07 2012-01-25 东莞市中镓半导体科技有限公司 Method for nondestructively peeling GaN and sapphire substrate by solid laser
CN101879657B (en) * 2009-05-08 2016-06-29 东莞市中镓半导体科技有限公司 Solid laser lift equipment and stripping means
JP2010278338A (en) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd Sos substrate low in defect density in proximity of interface
JP2010278337A (en) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd Sos substrate reduced in surface defect density
US9669613B2 (en) 2010-12-07 2017-06-06 Ipg Photonics Corporation Laser lift off systems and methods that overlap irradiation zones to provide multiple pulses of laser irradiation per location at an interface between layers to be separated
CN102714150B (en) 2009-12-07 2016-01-20 Ipg微系统有限公司 Laser lift-off system and method
DE102009057566A1 (en) 2009-12-09 2011-06-16 Osram Opto Semiconductors Gmbh Apparatus for a laser lift-off method and laser lift-off method
WO2011069242A1 (en) * 2009-12-09 2011-06-16 Cooledge Lighting Inc. Semiconductor dice transfer-enabling apparatus and method for manufacturing transfer-enabling apparatus
US20110151588A1 (en) * 2009-12-17 2011-06-23 Cooledge Lighting, Inc. Method and magnetic transfer stamp for transferring semiconductor dice using magnetic transfer printing techniques
US8334152B2 (en) * 2009-12-18 2012-12-18 Cooledge Lighting, Inc. Method of manufacturing transferable elements incorporating radiation enabled lift off for allowing transfer from host substrate
JP2012015150A (en) * 2010-06-29 2012-01-19 Ushio Inc Laser lift-off method and laser lift-off system
CN101964385B (en) * 2010-10-28 2012-08-29 映瑞光电科技(上海)有限公司 Light emitting diode and making method thereof
JP5752933B2 (en) 2010-12-17 2015-07-22 株式会社ディスコ Processing method of optical device wafer
JP5878292B2 (en) 2010-12-24 2016-03-08 株式会社ディスコ Processing method of optical device wafer
JP5603812B2 (en) 2011-03-11 2014-10-08 スタンレー電気株式会社 Manufacturing method of semiconductor device
JP5612516B2 (en) 2011-03-11 2014-10-22 スタンレー電気株式会社 Manufacturing method of semiconductor device
JP5658604B2 (en) 2011-03-22 2015-01-28 スタンレー電気株式会社 Manufacturing method of semiconductor light emitting device
FR2977069B1 (en) 2011-06-23 2014-02-07 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE USING TEMPORARY COLLAGE
JP5823749B2 (en) 2011-07-11 2015-11-25 株式会社ディスコ Method for dividing optical device substrate
JP5878330B2 (en) 2011-10-18 2016-03-08 株式会社ディスコ Laser beam output setting method and laser processing apparatus
JP5912442B2 (en) 2011-11-17 2016-04-27 スタンレー電気株式会社 Semiconductor light emitting device and method for manufacturing semiconductor light emitting device
JP5860272B2 (en) 2011-11-24 2016-02-16 株式会社ディスコ Processing method of optical device wafer
US9490193B2 (en) 2011-12-01 2016-11-08 Infineon Technologies Ag Electronic device with multi-layer contact
JP5879131B2 (en) * 2012-01-11 2016-03-08 株式会社ディスコ Substrate peeling method
JP5988644B2 (en) * 2012-03-27 2016-09-07 株式会社ディスコ Processing method of optical device wafer
JP2014055091A (en) * 2012-09-13 2014-03-27 Osaka Univ Method for producing group iii-v compound crystal, method for producing seed crystals formed substrate, group iii-v compound crystal, semiconductor device, group iii-v compound crystal producing apparatus, seed crystals formed substrate producing apparatus
CN104756245B (en) * 2012-10-26 2017-09-22 Rfhic公司 The semiconductor devices and its manufacture method of reliability and working life with raising
JP6101084B2 (en) 2013-01-17 2017-03-22 株式会社ディスコ Separation device
DE102013100711B4 (en) 2013-01-24 2021-07-01 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Process for the production of a large number of optoelectronic components
US10319789B2 (en) 2016-08-12 2019-06-11 Osram Opto Semiconductors Gmbh Method for producing an optoelectronic component and an optoelectronic component
DE102018101569A1 (en) 2018-01-24 2019-07-25 Osram Opto Semiconductors Gmbh SURFACE-EMITTING SEMICONDUCTOR LASER CHIP
TWI678748B (en) * 2018-10-18 2019-12-01 大陸商蘇州工業園區雨竹半導體有限公司 Method for separating test sample from wafer substrate
KR102174928B1 (en) * 2019-02-01 2020-11-05 레이저쎌 주식회사 Multi-beam laser de-bonding equipment and method thereof
JP7199307B2 (en) * 2019-05-24 2023-01-05 株式会社ディスコ Relocation method

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US4120706A (en) * 1977-09-16 1978-10-17 Harris Corporation Heteroepitaxial deposition of gap on silicon substrates
JPS592171B2 (en) 1979-06-11 1984-01-17 工業技術院長 Heat treatment method using light
US4752668A (en) 1986-04-28 1988-06-21 Rosenfield Michael G System for laser removal of excess material from a semiconductor wafer
US4749840A (en) 1986-05-16 1988-06-07 Image Micro Systems, Inc. Intense laser irradiation using reflective optics
JP2908818B2 (en) * 1989-09-18 1999-06-21 株式会社日立製作所 Method for manufacturing semiconductor device
US5326424A (en) 1989-12-06 1994-07-05 General Motors Corporation Cubic boron nitride phosphide films
US5300756A (en) 1991-10-22 1994-04-05 General Scanning, Inc. Method for severing integrated-circuit connection paths by a phase-plate-adjusted laser beam
JP3237888B2 (en) 1992-01-31 2001-12-10 キヤノン株式会社 Semiconductor substrate and method of manufacturing the same
DE4324318C1 (en) 1993-07-20 1995-01-12 Siemens Ag Method for series connection of an integrated thin-film solar cell arrangement
US6958093B2 (en) * 1994-01-27 2005-10-25 Cree, Inc. Free-standing (Al, Ga, In)N and parting method for forming same
JP3269251B2 (en) 1994-03-31 2002-03-25 株式会社デンソー Manufacturing method of stacked semiconductor device
US5787104A (en) * 1995-01-19 1998-07-28 Matsushita Electric Industrial Co., Ltd. Semiconductor light emitting element and method for fabricating the same
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5674758A (en) 1995-06-06 1997-10-07 Regents Of The University Of California Silicon on insulator achieved using electrochemical etching
US5625202A (en) 1995-06-08 1997-04-29 University Of Central Florida Modified wurtzite structure oxide compounds as substrates for III-V nitride compound semiconductor epitaxial thin film growth
DE19546443A1 (en) 1995-12-13 1997-06-19 Deutsche Telekom Ag Combination of optical or electro-optical waveguiding structures
EP1758169A3 (en) * 1996-08-27 2007-05-23 Seiko Epson Corporation Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same
US5828088A (en) 1996-09-05 1998-10-27 Astropower, Inc. Semiconductor device structures incorporating "buried" mirrors and/or "buried" metal electrodes
DE19640594B4 (en) * 1996-10-01 2016-08-04 Osram Gmbh module
DE19706279A1 (en) 1997-02-18 1998-08-20 Siemens Ag Laser device
US5838870A (en) 1997-02-28 1998-11-17 The United States Of America As Represented By The Secretary Of The Air Force Nanometer-scale silicon-on-insulator photonic componets
JPH10326884A (en) 1997-03-26 1998-12-08 Canon Inc Semiconductor substrate, its manufacture and its composite member
DE69826053T2 (en) 1997-03-26 2005-09-29 Canon K.K. Semiconductor substrate and method for its production
US5998291A (en) 1997-04-07 1999-12-07 Raytheon Company Attachment method for assembly of high density multiple interconnect structures
JPH10335567A (en) * 1997-05-30 1998-12-18 Mitsubishi Electric Corp Semiconductor integrated-circuit device
US6071795A (en) * 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
US6380097B1 (en) * 1998-05-11 2002-04-30 The United States Of America As Represented By The Secretary Of The Air Force Method for obtaining a sulfur-passivated semiconductor surface
DE19821544A1 (en) 1998-05-14 1999-12-16 Jenoptik Jena Gmbh Diode laser component with heat sink providing less thermal expansion stress
US6331208B1 (en) * 1998-05-15 2001-12-18 Canon Kabushiki Kaisha Process for producing solar cell, process for producing thin-film semiconductor, process for separating thin-film semiconductor, and process for forming semiconductor
US6136141A (en) * 1998-06-10 2000-10-24 Sky Solar L.L.C. Method and apparatus for the fabrication of lightweight semiconductor devices
US6504180B1 (en) 1998-07-28 2003-01-07 Imec Vzw And Vrije Universiteit Method of manufacturing surface textured high-efficiency radiating devices and devices obtained therefrom
US6169298B1 (en) 1998-08-10 2001-01-02 Kingmax Technology Inc. Semiconductor light emitting device with conductive window layer
JP2000174350A (en) 1998-12-10 2000-06-23 Toshiba Corp Optical semiconductor module
US6744800B1 (en) 1998-12-30 2004-06-01 Xerox Corporation Method and structure for nitride based laser diode arrays on an insulating substrate
JP2000196197A (en) * 1998-12-30 2000-07-14 Xerox Corp Structure of nitride laser diode where growth substrate is eliminated and method for manufacturing nitride diode array structure
US6280523B1 (en) * 1999-02-05 2001-08-28 Lumileds Lighting, U.S., Llc Thickness tailoring of wafer bonded AlxGayInzN structures by laser melting
US6320206B1 (en) 1999-02-05 2001-11-20 Lumileds Lighting, U.S., Llc Light emitting devices having wafer bonded aluminum gallium indium nitride structures and mirror stacks
JP2001015798A (en) 1999-06-29 2001-01-19 Toshiba Corp Semiconductor light emitting device
KR100660310B1 (en) 1999-07-30 2006-12-22 닛폰 이타가라스 가부시키가이샤 Method of dicing semiconductor wafer into chips, and structure of groove formed in dicing area
US6287882B1 (en) 1999-10-04 2001-09-11 Visual Photonics Epitaxy Co., Ltd. Light emitting diode with a metal-coated reflective permanent substrate and the method for manufacturing the same
JP3893874B2 (en) 1999-12-21 2007-03-14 日亜化学工業株式会社 Manufacturing method of nitride semiconductor light emitting device
DE10051465A1 (en) * 2000-10-17 2002-05-02 Osram Opto Semiconductors Gmbh Method for producing a GaN-based semiconductor component
US6562648B1 (en) * 2000-08-23 2003-05-13 Xerox Corporation Structure and method for separation and transfer of semiconductor thin films onto dissimilar substrate materials
DE10056645B4 (en) 2000-11-09 2007-03-08 Azzurro Semiconductors Ag Process for the preparation of crack-free, planar group-III-N, group III-V-N and metal-nitrogen device structures on Si substrates by epitaxial methods
US6864158B2 (en) 2001-01-29 2005-03-08 Matsushita Electric Industrial Co., Ltd. Method of manufacturing nitride semiconductor substrate
US6589857B2 (en) * 2001-03-23 2003-07-08 Matsushita Electric Industrial Co., Ltd. Manufacturing method of semiconductor film
JP2003007616A (en) 2001-03-23 2003-01-10 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor film
US6723165B2 (en) * 2001-04-13 2004-04-20 Matsushita Electric Industrial Co., Ltd. Method for fabricating Group III nitride semiconductor substrate
US6902098B2 (en) 2001-04-23 2005-06-07 Shipley Company, L.L.C. Solder pads and method of making a solder pad
JP4524953B2 (en) 2001-05-18 2010-08-18 パナソニック株式会社 Method for manufacturing nitride semiconductor substrate and method for manufacturing nitride semiconductor device
JP2002343717A (en) 2001-05-18 2002-11-29 Matsushita Electric Ind Co Ltd Method for producing semiconductor crystal
US6814832B2 (en) * 2001-07-24 2004-11-09 Seiko Epson Corporation Method for transferring element, method for producing element, integrated circuit, circuit board, electro-optical device, IC card, and electronic appliance
DE10203795B4 (en) 2002-01-31 2021-12-09 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Method for manufacturing a semiconductor component
DE10303978A1 (en) 2002-01-31 2003-11-27 Osram Opto Semiconductors Gmbh Semiconductor component used as a light emitting diode, especially an illuminating diode or laser diode, comprises a thin film semiconductor body arranged on a support containing germanium
TWI226139B (en) 2002-01-31 2005-01-01 Osram Opto Semiconductors Gmbh Method to manufacture a semiconductor-component
US8294172B2 (en) 2002-04-09 2012-10-23 Lg Electronics Inc. Method of fabricating vertical devices using a metal support film
KR100504178B1 (en) 2003-01-22 2005-07-27 엘지전자 주식회사 Light emitting diode and method of manufacturing the same
JP4986406B2 (en) * 2005-03-31 2012-07-25 住友電工デバイス・イノベーション株式会社 Manufacturing method of semiconductor device

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