TW200305076A - Methods and apparatus for forming linked list queue using chunk-based structure - Google Patents

Methods and apparatus for forming linked list queue using chunk-based structure Download PDF

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Publication number
TW200305076A
TW200305076A TW091135045A TW91135045A TW200305076A TW 200305076 A TW200305076 A TW 200305076A TW 091135045 A TW091135045 A TW 091135045A TW 91135045 A TW91135045 A TW 91135045A TW 200305076 A TW200305076 A TW 200305076A
Authority
TW
Taiwan
Prior art keywords
block
memory
list
queue
queue structure
Prior art date
Application number
TW091135045A
Other languages
English (en)
Chinese (zh)
Inventor
Jian-Guo Chen
David E Clune
Hanan Z Moller
David P Sonnier
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Publication of TW200305076A publication Critical patent/TW200305076A/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9015—Buffering arrangements for supporting a linked list
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/064—Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
TW091135045A 2001-12-21 2002-12-03 Methods and apparatus for forming linked list queue using chunk-based structure TW200305076A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/029,680 US6754795B2 (en) 2001-12-21 2001-12-21 Methods and apparatus for forming linked list queue using chunk-based structure

Publications (1)

Publication Number Publication Date
TW200305076A true TW200305076A (en) 2003-10-16

Family

ID=21850308

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091135045A TW200305076A (en) 2001-12-21 2002-12-03 Methods and apparatus for forming linked list queue using chunk-based structure

Country Status (5)

Country Link
US (1) US6754795B2 (enExample)
EP (1) EP1321863A3 (enExample)
JP (1) JP2003228515A (enExample)
KR (1) KR100958507B1 (enExample)
TW (1) TW200305076A (enExample)

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US7487505B2 (en) * 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
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US7610451B2 (en) * 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US6892278B2 (en) * 2002-03-05 2005-05-10 Sun Microsystems, Inc. Method and apparatus for efficiently implementing a last-in first-out buffer
DE10215719A1 (de) * 2002-04-10 2003-10-30 Philips Intellectual Property Datenspeicher
US7337275B2 (en) * 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US6907508B2 (en) * 2003-02-26 2005-06-14 Emulex Design & Manufacturing Corporation Structure and method for managing available memory resources
US7035988B1 (en) * 2003-03-17 2006-04-25 Network Equipment Technologies, Inc. Hardware implementation of an N-way dynamic linked list
US7213099B2 (en) 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
US7702627B2 (en) 2004-06-22 2010-04-20 Oracle International Corporation Efficient interaction among cost-based transformations
CN100440854C (zh) * 2004-06-25 2008-12-03 中国科学院计算技术研究所 一种网络处理器的数据包接收接口部件及其存储管理方法
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US8271093B2 (en) 2004-09-17 2012-09-18 Cardiac Pacemakers, Inc. Systems and methods for deriving relative physiologic measurements using a backend computing system
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US7756573B2 (en) * 2006-09-05 2010-07-13 Cardiac Pacemakers, Inc. Implantable medical device diagnostic data acquisition and storage
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CN104125176A (zh) * 2013-04-25 2014-10-29 联发科技股份有限公司 封包处理方法以及封包处理装置
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US12493432B2 (en) 2017-05-31 2025-12-09 Fmad Engineering (Sng) Pte Ltd. High speed data packet flow processing with offload
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WO2016202158A1 (zh) * 2015-06-15 2016-12-22 深圳市中兴微电子技术有限公司 一种报文传输方法、装置及计算机可读存储介质
CN106330741A (zh) * 2015-06-15 2017-01-11 深圳市中兴微电子技术有限公司 一种报文传输方法和装置
CN106330741B (zh) * 2015-06-15 2020-04-24 深圳市中兴微电子技术有限公司 一种报文传输方法和装置

Also Published As

Publication number Publication date
KR100958507B1 (ko) 2010-05-17
JP2003228515A (ja) 2003-08-15
US6754795B2 (en) 2004-06-22
EP1321863A2 (en) 2003-06-25
US20030120879A1 (en) 2003-06-26
EP1321863A3 (en) 2003-07-02
KR20030053030A (ko) 2003-06-27

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