TW200303674A - Method empolyed by a base station for transferring data and base station/user equipment having hybrid parallel/serial bus interface - Google Patents

Abstract

A hybrid serial/parallel bus interface method for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Description

200303674 ⑴ 玖, description of the invention (the description of the invention should state: the technical field, prior art, content, embodiments, and drawings of the invention belong to the invention) Technical Field The present invention relates to the transfer of bus data. In particular, the present invention is to reduce the number of lines for transmitting bus data. Prior art

Figure 1 shows an example of a bus for transmitting data. FIG. 1 is an explanatory diagram of receiving and transmitting gain controllers (GC) 30 and 32, and a GC controller 38 for a wireless communication system. A communication station, such as a base station or user equipment, transmits (TX) and receives (RX) signals. In order to control the gain of these signals, falling within the operating range of other receiving / transmitting components, the GC 30 and 32 will adjust the gain on the RX and TX signals.

To control the gain parameters of the GC 30, 32, a GC controller 38 is used. That is, as shown in FIG. 1, the GC controller 38 uses a power control bus, such as 16 line buses 34 and 36 to send the TX 36 and RX 34 signal gain values, as if each is eight lines. . Although the power control bus lines 34 and 36 can be used to allow fast data transmission, this will require many pins on the GC 30, 32 and the GC controller 38, or an integrated circuit like a dedicated integrated circuit (ASIC) (1C) Many connections between GC 30, 32 and GC controller 38. Increasing the number of pins will require additional board space and wiring. Adding 1C connections will take up precious 1C space. A large number of pins or connections may increase the cost of the bus depending on the implementation. Therefore, it is desirable to have other data transmission methods. Summary of the Invention 200303674 Description of the Invention Continue to buy a block of data (2)

A hybrid parallel / serial bus interface with a demultiplexing device. The data block demultiplexing device has an input, which is configured to receive a data block and demultiplex the data block into a plurality of fine blocks. For each block, a parallel-to-column converter converts the block into serial data. One line can transmit serial data of each small block. A serial-to-parallel converter converts the serial data of each block to recover the block. The data block reconstruction device can merge the restored fine blocks into the data block. A base station (or a user equipment) has a gain control controller. The gain control controller generates a data block having n bits representing a gain value. A data block demultiplexing device has an input, which is configured to receive the data block and demultiplex the data block into a plurality of fine blocks. Each fine block has a plurality of bits. For each fine block, a parallel-to-serial converter can convert the fine-block to serial data. One line transmits the fine-block serial data, and a serial-to-parallel converter can convert the fine-block serial data To restore the fine piece. A data block reconstruction device may merge the restored fine blocks into the data block. A gain controller receives the data block and uses the gain value of the data block to adjust its gain. Embodiment FIG. 2 is a block diagram of a hybrid parallel / serial bus interface, and FIG. 3 is a flowchart of data transmission operation of the hybrid parallel / serial bus interface. A block of data is passed across the interface from node 1 50 to node 2 52 (54). A data block demultiplexing device 40 receives the block and demultiplexes it into i fine blocks to facilitate transmission on i data transmission lines 44 (56). The value i is based on the trade-off between the number of connections and the transmission speed. One decision i (3) (3) 200303674

The way to value is to first determine a 俵 ... ,, Bu Xin: Dagger-J delay r B〃. The maximum allowable return on the appropriate child data block. Based on this maximum delay, eight small tons & a U. determine the minimum number of springs needed to transmit the block. Utilizing the minimum number of energies, love A 4 π, I spoon line 'The line used to transmit data is selected as at least the minimum I ^ 逭. The line 44 may be a pin, and its related connection on a tun board or an IC connection ^ yr ^. ^ T. One way to solve the problem of multiplexing into fine blocks is to cut the block into ~ Ling You 尤 4 Today, λ is taken to be the smallest significant block. As illustrated in Figure 4, on two lines, one solution is more ^ ^ ^ — an eight-bit block, which will be built into a four-bit block by Xi Xi. The most significant V _. ^,,, Block, and one Four-bit smallest significant chunk. The other way is to i-gage the region, and -a spans i fine blocks. One bit of this block will become the first bit of each bit. The next i bits will be intersected into the second bits ^ and i ′ of each i fine block, and so on until the last i bits. In order to illustrate t ice shown in Fig. 5, also one eight-bit block on the two lines, one bit will be mapped to the second bit of the first bit of the thin, one of the tail. Yuan Bei is mapped to the first bit of block 2. # 一 曰 〃. The third bit will be mapped to the second bit of block 1, so continue moxibustion ’until the last bit is mapped to the last bit of block 2. Each fine block will be sent to the corresponding (58) of the parallel-to-serial (P / S) converter 42, which will be dragged from parallel bits to serial bits and serialized on the line Sequential transmission (60). On the opposite side of each strip will be a series-to-parallel (S / P) converter 46. Each s / ρ converter 46 converts the transmitted serial data into its original fines (62). The i-th restored fine block is processed by a data block reconstruction device 48 to reconstruct the original data block (μ). On the other hand, two-way method will use 丨 connections to transfer data in two-way mode, as shown in Figure 6. The information can be transmitted in two directions, or the order (4) 200303674 mm: m: The information is transmitted in one direction and the confirmation signal is returned in the other direction. For example, the data block demultiplexing and reconstruction device 66 will receive the data block transmitted from the node 150 to the section 2 52. The demultiplexing and book stubbing will stop the person reconstruction device 66 from decomposing the corresponding counterpart of line 44. At node 2 52, another group of multiplexing MUX / DEMUX 75 will connect line 44 To a set of s / p converters 72. The set of w converters 72 will convert the received serial data of each block into the original transmitted block. The received block will be demultiplexed and reconstructed by a data block The device% is reconstructed into the original data block and output as the received data block. It is made into fine blocks. The i P / S converter 68 will convert each fine block into serial data.-Group multiplexer ( MUX) / Dqing x 71 connects each p / s converter 68 to each block that is transmitted from node 2 52 to 5 解. The data block demultiplexing and money | set 76 will receive a data block. The The blocks will be demultiplexed into fine blocks and sent to a set of p / s converters 74. The P / S converter 74 will convert the fine blocks into a serial format for cross-over丨 line 44 transmission. The MUX / DEMUX 75 of the node 2 group will couple these P / s converters 74 to the 丨 line 44 and the MUX / DEMUX 71 of the node 1 group will couple the line 44 to 1 S / P converter 7〇 The s / p converters 70 convert the transmitted data into its original fine blocks. The data block demultiplexing and reconstruction device 66 reconstructs the shell material blocks from the received fine ghosts to output the received data. Block. Since eight data will be transmitted in a single direction at a time, this implementation can operate in a half-duplex mode. 0 A simple implementation diagram of a solid parent switching circuit. This node has a 1 p / s converter. Fortunately, the output will be input to a three-state buffer. The buffer M8 has another spoke 'This will be coupled to a voltage indicating a high state. The buffer (5) 200303674 ---_ the output of the punch 78 The serial data is transmitted to a node 2 tri-state buffer 84 through a line 85. A resistor 86 is coupled between the line 85 and the ground. The node 2 buffer 84 passes the serial data to a node 2 S / P converter 74. Similarly, the serial output from this node 2 P / S converter 74 will be rotated into a tri-state buffer 72. The buffer 72 also has another coupling to a High voltage input. The serial output of the buffer 82 is transmitted to the tri-state buffer 80 of node 1 through line 85. The node 1 The puncher 80 will pass the serial data to a node 1 S / P converter 70. In another implementation, the 'part i line 44 can transmit data in one direction' and the other i lines 44 Data can be transmitted in the other direction. At node 1 50, a data block will be received for transmission to node 2 52. According to the data throughput rate required by the block and the traffic demand in the other direction, 疋 ' Here, j blocks will be used to transmit the block, where the value of j is between 1 and i. The block will be divided into j fine blocks, and the number of "p / s converters 68" will be used. To convert it into j sets of serial data. The corresponding j node 2 S / P converters 72 are different from the node 2 data blocks and the reconstruction device 76 restores the data blocks. In the opposite direction, up to i_j or k lines are used to transfer the data block. In a preferred implementation of a bi-directional bus for a gain control bus, a gain control value is sent in one direction and a confirmation signal is sent back. Alternatively, a gain control value is sent in one direction, and a gain control device status signal is sent in the other direction. A hybrid parallel / serial interface is implemented in a synchronous system and can be described as shown in FIG. Here, a synchronous clock will be used to synchronize various types. -10- 200303674 _ Talk about the performance of buying points, will send (6)

Timing of components. Bits used to represent the beginning of the data block transfer operation. That is, as shown in Figure 8, each line will be at its normal zero level. A start bit is then sent to indicate the start of the block transfer operation. In this example, all lines will send a start bit, but it is only necessary to send a start bit on one line. If the start bit is sent on any line, such as a value of 1, the receiving node will clearly start the block data transmission operation. Here, each filial piety block will be sent through its corresponding line. After transmitting the various pieces, the line returns to their normal state, as if they were all low.

In other implementations, the start bit is also used as the indicator of the function to be executed. This implementation can be illustrated in Figure 9. As shown in FIG. 10, if the first bit of any connection is 1, the receiving node will know the block data to be transmitted. That is, as shown in the table implemented by the GC controller in FIG. 11, three start bit combinations are used: 01, 10, and 11.00 to indicate that no start bit has been sent. Each combination represents a function. In this example, 01 indicates that a relative reduction function should be performed, such as reducing the data block value by one. 10 indicates that a relative increase function should be performed, such as increasing the value of the data block by 1. 11 means that an absolute value function should be executed, and the block will maintain the same value at this time. To increase the number of available functions, additional bits can be used, for example, 2 start bit maps per line can be reached to seven (7) term functions, or n start bit maps of i lines can be reached in + 1-l functions. The processing device 86 executes a function on the received data block as described in the start bit. In another implementation shown in Fig. 12, the start bit indicates a destination device. That is, as shown in FIG. 13, this is an implementation of two destination devices / two lines. The combination of start bits will be associated with the destination device for the transmitted data block-11-200303674 (7) 丨 赖 88- 92. Shows device 1; shows device 2 'and 11 shows device 3. After receiving the start bit of the data block reconstruction device 48, the reconstructed block will be sent to the corresponding devices 88-92. To increase the number of potential destination devices, additional start bits can be utilized. For n starting bits on each of the i lines, we select up to in + 1-1 devices.

That is, as shown in FIG. 14, the start bit can be used to represent both the function and the destination device. Figure 14 shows a three-wire system with two devices like 疋 RX and TX GC. Using the start bit on each line, three functions of the two devices are plotted in the figure. In this example, the start bit of line 1 represents the target device, "0" is device 1, and "1" is device 2. Bits 2 and 3 represent the function being executed. "11" represents an absolute value function; "1 0" represents a relatively increasing function; and "0 1" represents a relatively decreasing function. All three start bits are zero, meaning "000", which will be a normal non-data transfer state, and "⑼1" is not used here. Additional bits can be used to add-add more function bites. For n starting bits on each of the i lines, 1 i function / device combinations can be selected for production.

Fig. 15 is a system block diagram showing the start bit of both the function and the destination device. The recovered fine blocks are received by the data block reconstruction device. According to the received start bit, the processing device 86 executes the function, and sends the processed block to the destination device 88_9, that is, as shown in the flowchart of FIG. 16, the table is related to the function The / destination π closing start bit is added to each of the fine blocks (94). Here, it will be sent out through this i line, plus some small pieces (96). Using the start bit, the block will be executed on the data block, and the data block will be sent to the appropriate destination or both (98). -12- 200303674

To increase the throughput in the synchronization system, both positive (double) and negative (single) edges of the clock are used to transmit block data. One implementation is shown in Figure 17. Negative material £ ^ Demultiplexing device 1⑼ Receives the data block and demultiplexes it into two (double and single) groups of i fine blocks. Here, the data of each group of i fine blocks is transmitted to i P / s devices 102 and 104 of each group. That is, as shown in FIG. 17, a single P / S device 102 of the _ group will have i p / s devices, which will have its clock signal inverted by the inverter 118. Therefore, the inverted clock signal will be delayed by half a clock period relative to the system clock. A group of Μχχ 106 will be selected between the group of dual p / s devices ι04 and the group of single P / s devices ι02 at twice the clock rate. The resulting data sent over each connection will be twice the clock rate. At the other end of each connection is a corresponding DEMUX 108. These DEMUX 108 sequentially couple each line 44 to a dual in and single 110 buffer at a double clock rate. Each buffer 112, 110 receives a corresponding double and unit cell, and holds the value for a rounded clock cycle. A pair of 116 and single 114 S / P devices will recover the double and single fine blocks. A data block reconstruction device 122 reconstructs the data block from each transmitted fine block. Figure 18 illustrates data transfer operations performed on a system line using the positive and negative clock edges. The figure shows dual data and single data to be transmitted on line 1. The oblique wedge portion indicates the negative clock edge within the merged signal, while the non- oblique wedge portion indicates the positive one. That is, as shown, the data transfer rate is doubled. Figure 19 is a preferred implementation of a hybrid parallel interface for a GC controller 38 and a GC 124. A block of data, such as 16-bit GC control 200303674 (9) The food cocoon seems to be poor :; data (8-bit RX and 8-bit τχ) will be transmitted from the GC controller 38 to a batch Material block demultiplexing device 40. The data block is demultiplexed into two blocks, like two 8-bit blocks. A start bit is added to each of the pieces. It ’s like 9 bits for each piece. Here, two P / S converters 42 are used to transmit the two fine blocks on two lines. When s / p converter 46 detects

When the start bit is 7C, the received fine block is converted to a parallel format. The data block reconstruction device reconstructs the original 16 bits to control the gain of gc 124. For example, a function is expressed at the beginning, as shown in Fig. Η, the AG. This function will be executed on the received block before adjusting the gain. Figure 20 is another preferred implementation of a hybrid parallel / serial bus converter. This system is located between the GC controller 38 and -RXGC30 and TXGC32.

Use three (3) lines. The GC controller 38 sends a data block to the gc 30, 32 according to the appropriate & gain value and start bit, that is, as shown in FIG. If the start bit according to Fig. 14 is indeed used, the device urxgc30 and the device 2 are TX GC 32. The data block demultiplexing device 40 demultiplexes the f block into three fine blocks for transmission through these three lines. With three P / S converters 42 and three S / P converters 46, each fine block is transmitted in series on each line and converted into the original fine block. The read data block reconstruction device 48 reconstructs the original data block and performs the functions described in the start bit, such as relative increase, relative decrease, and absolute value. The obtained data will be sent to RX or TX GC 30, 32 as described in the start bit. Schematic description Figure 1 is a schematic illustration of the RX and TX GC and GC controllers. Figure 2 is a block diagram of a hybrid parallel / serial bus interface. -14-200303674 (10) Statement of continued purchase 1 Figure 3 is a flow chart of data block transfer using a hybrid parallel / serial bus interface. Figure 4 illustrates a demultiplexing operation that transforms a block into the most significant and smallest significant fine blocks. FIG. 5 illustrates demultiplexing a block using data interleaving. Figure 6 is a block diagram of a bi-directional hybrid parallel / serial bus interface. FIG. 7 is a schematic diagram of a bidirectional line implementation.

FIG. 8 is a timing chart of a start bit. Figure 9 is a block diagram of a hybrid parallel / serial bus interface with function controllability. FIG. 10 is a timing diagram of the start bit of a hybrid parallel / serial bus interface with function controllability. FIG. 11 is a list of implementations of start bits of each function. Figure 12 is a block diagram of the destination control hybrid parallel / serial bus interface. FIG. 13 shows a start bit implementation list of each destination.

FIG. 14 shows a start bit implementation list of each destination / function. Figure 15 is a block diagram of the destination / function control hybrid parallel / serial bus interface. FIG. 16 is a flowchart showing the start bit of each destination / function. Figure 17 is a block diagram of a mixed parallel / serial bus interface area with positive and negative clock edges. Fig. 18 is a timing chart of a mixed parallel / column bus interface with positive and negative clock edges. Figure 19 is a block diagram of a 2-wire GC / GC controller bus. -15- 200303674 Description of Invention Continued (11) Figure 20 is a 3-wire GC / GC controller bus block diagram. Symbol description 30 Receive gain controller 32 Transmit gain controller 34 Line bus 36 Line bus Row 38 GC controller 40 Data block demultiplexing device 42 Parallel to serial (ρ / s) converter 44 Data transmission line 46 Serial to parallel (S / P) converter 48 Data block reconstruction device 50 Node 1 52 Node 2 66 Data Block Demultiplexing and Reconstruction Device 68 Parallel-to-Serial (P / S) Converter 70 Serial-to-Parallel (S / P) Converter 72 Serial-to-Parallel (S / P) Converter 74 Parallel to Simultaneous (p / s) converter 76 Data block demultiplexing and reconstruction device 78 Buffer 80 Buffer 82 Buffer 84 Buffer -16- 200303674 (12) 85 Line 86 Resistor 88 Destination device 90 Destination device 92 Destination device 100 Data block demultiplexing device 102 Single P / S device 104 Double P / S device 106 Multiplexer 108 Demultiplexer 110 Buffer 112 Buffer 114 Single P / S device 116 Dual P / S device 122 Data block reconstruction device 124 Gain control Controlling the Township: ¾ ”Condensing Total :: ¾ Village Bullying Silicon Micro-to-Do :::« Micro-Excited * Invention Description Results Buying 槪 :: Calling the Silk Inspection Machine i: S Luling Suxian is Completed ί; total bell bus:

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Claims (1)

200303674 Patent application scope 1. A method for transmitting data by a base station, including: providing a data block; demultiplexing the data block into a plurality of fine blocks, each fine block having a plurality of bits For each fine block: convert the fine block into application data; provide a line and transmit the fine block serial data on the line; convert the fine block serial data into parallel data, and restore the fine block ; And merge the restoration pieces into the data block. 2. The method of item 1 in the scope of patent application, wherein the number of bits in the data block is N, the number of lines is i, and l < i < N. 3. As in the method of the first patent application, the number of bits in a fine block is four and the number of lines is two. 4. A method used by a base station to transmit a data block through an interface connecting a first node to a second node, wherein the method includes: demultiplexing the data block into m groups of n bits; A start bit is added to these m groups, and these m start bits can collectively represent a specific mathematical function or destination; on individual lines, each of the m groups is transmitted from the first node; The two nodes receive the m groups transmitted; and use the received m groups according to the m start bits. 200303674 Miscellaneous pages: 5. As in the method of applying for the fourth item of the patent scope, at least one of these m start bits will be 1 state, and when the interface does not transmit data, all individual lines will be 0 state . 6. The method according to item 4 of the patent application, wherein these m start bits represent the start of a data transfer operation. 7. The method of claim 4 in which the m starting bits collectively represent a specific mathematical function rather than a destination. 8. The method according to item 4 of the patent application range, wherein the m start bits collectively represent a function including a relative increase, a relative decrease, and an absolute value function. 9. The method of claim 4 in which the m starting bits collectively represent a specific destination rather than a mathematical function. 10. If the method of the scope of the patent application is applied for, the m starting bits collectively represent a RX and TX gain controller, 11. If the method of the scope of the patent application is applied for the fourth project, the m starting bits Metasets represent a specific mathematical function and a specific destination. 12. — A method used by a base station to determine the number of i bus connections required to transmit block data on a bus. Each block of the block data has N bits. This method Including: determining the maximum delay that can be tolerated for the transmission of such data blocks; determining the maximum number of connections required to transmit the data blocks according to the maximum delay; and determining the value of i, where i The minimum number of wires required. 13. If the method of claim 12 is applied, the i bus connection 200303674 will correspond to i pins on a chip. 14. The method of claim 13 in the scope of patent application, wherein the l < i < N. 15. —A method used by the base station, including: generating a data block by a gain control (GC) controller, the data block having n bits representing a gain value; The data block is transferred from the GC controller to a GC, where l < i <n; Receiving the data block at the GC; and using the gain value of the data block to adjust the GC gain. 16. The method according to item 15 of the scope of patent application, further comprising: before transmitting the data, demultiplexing the data block into a plurality of thin blocks, each of which is a different line on the i line Uploading; and after receiving the data block, combining the fine blocks into the data block. 17. The method according to item 16 of the patent application, in which the appended to each sub-block is the first bit. 18. The method of claim 17 in which the start bit can represent a mathematical function. 19. The method of claim 15 in which the mathematical function expressed by the start bit includes a relative increase, a relative decrease, and an absolute value function. 20. The method of claim 15 in which the GC includes a RX GC and a TX GC, and the start bits indicate that the block needs to be sent to the RX GC or TX GC. 21. —A kind of user equipment, which includes: 200303674 Special Affairs Specialist: Miscellaneous Xiangxiang Leaked Seven * V ί · *, τ ·· * " 'X ·? F, ff ^ ^ ff * .'-' v A gain control controller to generate a n-bit data block representing a gain value; a data block demultiplexing device having an input, configured to receive the data block, and Demultiplex the data block into a plurality of fine blocks, each of which has a plurality of bits; for each fine block: A parallel-to-serial converter to convert the fine blocks into serial data; a line to transmit the fine-serial data; and a serial-to-parallel converter to convert the fine-serial data to restore the Fine block; and a data block reconstruction device to reconstruct the restored fine block into the data block; and a gain controller to receive the data block and use the gain value of the data block to adjust the GC Gain. — 22. For the user equipment of the scope of application for patent No. 21, the number of bits in a data block is N, the number of lines is i, and l < i < N. 23. For the user equipment in the scope of patent application No. 21, the number of bits in a sub-block is four and the number of lines is two. 24. For the user equipment in the scope of application for patent No. 21, those added to each detail are the first bits. 25. A user equipment, comprising: a gain control controller to generate a data block of n bits representing a gain value; a data block demultiplexing device having an input and configured Set to 200303674 r Please win the special beach: buy:, Laoshan-'V ', 々,: ..., receive the data block, and demultiplex the data block into a plurality of fine blocks 9 each fine block has a complex number Bits; for each fine block: a parallel-to-column converter to convert each fine block into serial data; a line to transmit the fine-block serial data; and a serial-to-parallel converter to convert The fine block serial data does not restore the fine block; and A data block reconstruction device to reconstruct the recovered fine block into the data block and selectively guide the data block to a RX gain controller or a TX gain controller; and the RX gain controller and The TX gain controller is set to receive the data block, and adjust the gain by using the gain value of the received data block. 26. For the user equipment in the scope of application for the patent No. 25, the number of bits in a data block is N, the number of lines is i, and l < i < N. 27. For the user equipment in the scope of application for patent No. 25, the number of bits in a sub-block is four and the number of lines is two. 28. If the user equipment of the scope of application for patent No. 25, wherein the appended to each fine block is the first bit, the data block reconstruction device can selectively guide according to a value of the first bit The data block. 29. A base station comprising: a gain control controller to generate a data block having n bits representing a gain value; a data block demultiplexing device having an input and configured by setting Apply as 200303674: Please transfer to Fan Tan Ji Gongrang _ let Zhong Yi _________ face 1__ receive the data block 5 and demultiplex the data block into multiple fine blocks, each of which has multiple bits For each block: a parallel-to-column converter to convert each block into rate data; a line 5 to transmit the block contention data; and a string-to-parallel converter to convert the cell Block_row data: restore the fine block; and A data block reconstruction device 5 combines the restored fine blocks into the data block; and a gain controller to receive the data block and adjust the gain of the received data block using the gain value of the received data block. 30. For the base station in the scope of patent application No. 29, the number of bits in a data block is N, the number of lines is i, and l < i < N. 31. For the base station in the scope of patent application No. 29, in which the number of bits in a fine block is four 'and the number of lines is two. 32. If the base station in the scope of patent application No. 29 is applied, the one added to each sub-block is the first bit. 33. A base station comprising: a gain control controller to generate a data block having n bits representing a gain value; a data block demultiplexing device having an input and configured by setting To receive the data block, and demultiplex the data block into a plurality of fine blocks, each of which has a plurality of bits; for each of the fine blocks: 200303674 A converter to convert each fine block into serial data; a line to transmit the fine block kiosk data; and a serial-to-parallel converter to convert the fine block application data to restore the fine block; and a data The block reconstruction device 5 combines the restored fine blocks into the data block, and selectively guides the data block to a RX gain controller or a TX gain controller; and the RX gain controller and the TX gain The controller is set to receive the data block and adjust the gain of the received data block using the gain value of the data block. 34. For the base station in the scope of application for item 33, the number of bits in a data block is N, the number of lines is i, and l < i < N. 35. For a base station in the scope of application for item 33, the number of bits in a sub-block is four and the number of lines is two.