SU972949A1 - Device for searching for signal extreme values - Google Patents

Abstract

A DEVICE FOR SEARCHING FOR SIGNAL EXTREMUES, containing a comparison unit, maximum register, minimum register, memory block, pulse generator and two-digit shift register, the balance block output connected to the second input of the comparison block, the output block of the comparator is connected to the first inputs of the block the memory and with the inputs of the shift register, the output of the pulse generator is connected to the second input of the memory block, characterized in that, in order to expand the functionality of the device, two keys are entered into it , a digital-to-analog converter and a control unit, which consists of the first, second and third decoders, a key management trigger, a clock and pulse distributor, a clock generator, a mode changing unit, a trigger pulse counter, the outputs of the shift register are connected to the inputs of the first, second and the third decoder, and the outputs of the comparison unit are connected to the inputs of the second and third decoders, the first and second outputs distribute ALL OVER I 1 ;; "NO ;; d SUBLIO; g. / l L clock pulses are connected respectively to the first and second clock inputs of the shift register, the third output of the clock distributor is connected to the input of the first decoder and the single input of the key control trigger, the fourth output of the clock distributor is connected to the inputs of the second and third decoders and the zero input of the key management trigger, the fifth output of the clock distributor is connected to the input of the mode changing unit, the installation input of the trigger The keys are connected to the installation output of the change block (L of the operation modes, the output of the clock generator is connected to the inputs of the clock distributor and the mode changing block, the first control output of the mode changing block is connected to the input of the second decoder, the second to control The functions of the output of the unit for changing the operating modes are connected to the corresponding input of the distributor Tacto CD li SO, pulses; trigger pulses, the first output of which is connected to the input of the second decoder, and the second output - with the V inputs of the second and third decoders, the input of the first key is connected to the input source, the outputs of the first and second keys are connected to the first input of the comparator, the control input of the first key connected to the zero output of the trigger control (management keys, controlling

Description

97

the second key is connected to the single output of the key management trigger, the input of the second key is connected to the output of a digital analog converter, the control input of which is connected to the third clock of the clock distributor, and the information input to the information outputs of the memory block and registers of the maxigum and minimum, information the inputs of the maximum and M11 minimum registers are connected to the information output of the memory block, the information outputs of the memory block and the maximum registers and. the minimum is connected to the information output of the device; the control inputs for issuing the maximum and minimum register codes are connected to the first and second outputs of the first descrambler, respectively; the inputs of the maximum and mini-hum register registers are connected to the first and second outputs of the second decoder, respectively, the control input; Start

the memory unit is connected to the output of the starting pulses of the operating mode changing unit, the control input of the output of the memory block code is connected to the fourth output of the clock distributor, the outputs of the shift register are connected to the inputs of the third decoder, the Ready output of the memory block code is connected to the corresponding input of the block operating mode changes, the installation inputs of the memory unit, the shift register, the D / A converter, the maximum register and the minimum register are connected to the setup output b eye changes modes of operation, the input code blocks tire changing operation modes is connected to the input bus codebook modes of operation of the entire device, the output bus of the third code decoder control unit is connected to the sign output line code characteristics of the entire device.

The invention relates to digital measurement technology and analog-digital computing, and is intended to search for local and global extremes as well as the smallest and largest signal values.

A device for determining the extremes of a signal is known, which contains a delay line, keys5 a pulse generator, pulse shapers, a coincidence circuit, and serves to determine the magnitude and position of the extremes.

A disadvantage of this device is that it can only determine a local extremum.

The closest technical solution to the present invention is a device comprising a comparison unit, a maximum register, a minimum register, a memory unit, a pulse generator and a two-bit shift register, with the balancing output of the comparator unit connected to the second input of the comparison unit with the first inputs of the memory unit, and with the inputs of the shift register, the output of the pulse generator

connected to the second input of the memory unit.

In order to expand the functionality of the device, two keys, a digital-to-analog converter and a control unit, which consists of the first, second and third decoders, a key management trigger, the distributor, are entered into it.

clock pulses, clock pulse generator, operation mode change block, start imo counter

pulses, the balancing output of the memory unit is connected to the second input of the comparison unit, the output of the comparison unit is connected to the first input of the memory unit and the input of the shift register, the output of the pulse generator is connected to the second input of the memory unit, the outputs of the shift register are connected to the inputs of the first. first, second and third decoders, and the outputs of the comparison unit are connected to the inputs of the second and third decoders, the first and second outputs of the clock distributor are connected respectively to the first and second clock inputs of the shift register, the third output of the clock distributor is connected to the input of the first decoder and the single - . the control trigger input: keys, the fourth output of the clock distributor is connected to the inputs of the second and third decoders and the zero input of the key control trigger, the fifth output of the clock distributor connects to the input of the change unit. mode of operation, the installation input of the key management trigger is connected to the installation output of the operation mode change unit, the clock pulse output is connected to the clock distributor and the change retreat unit, the control mode output terminal is connected to the second decoder input, the second control the output of the mode changing unit is connected to the corresponding input of the clock distributor, the output of the starting pulses of the mode changing unit is connected to The first output of the TopoFO is connected to the input of the second decoder, and the second output is connected to the inputs of the second and third decoders, the input of the first key is connected to the input source, the outputs of the first and second keys are connected to the first input of the comparator The first key input is connected, with the zero output of the key management trigger, the control input of the second key is connected to the single output of the key management trigger, the input of the second key is connected to the digital-to-analog output. The emitter, the control input of which is connected to the third output of the clock distributor, and the information input to the information outputs of the memory block and the maximum and minimum registers, the information inputs of the maximum and minimum registers are connected to the information output of the memory block, the information outputs of the memory block and the registers of the maximum and minimum are connected to the information output of the device, the inputs of the manager issuing the code of the register maxi; the maximum and minimum are connected to the first and second outputs of the first decoder, respectively; the control inputs by entering the maximum and minimum registers code are connected to the first and BTOPLIM outputs of the second decoder, respectively; the control input of the memory unit is connected to the output of the mode changing unit; mov operation, the control input of the permission of the issuance of the code of the memory block is connected to the fourth output of the clock distributor, the outputs of the shift register are connected to the inputs of the third decoder, the output Ready code of the memory block is connected to the corresponding input of the change-mode circuit, setting inputs, the memory block ti, shift register, digital-to-analog converter, maximum and minimum registers are connected to the installation output of the operating mode changing unit, the input code bus of the operating mode changing unit oedinena the input code bus operation mode of the entire device, the output bus of the third code decoder control unit connected to the bus sign code output characteristics of the entire device.  The structural scheme of the proposed device is shown in the drawing.  It consists of a comparison block 1 (analog signals), a memory block 2, a two-bit shift register 3, a pulse generator 4, two analog switches 5 and 6, a control block 7, a digital-to-analog converter 8, a low-ground register 9, and a minimum register 10.  Unit 7 control consists of the first decoder 11. 1, the second decoder 11.2, the third decoder 11.3, the key management trigger 12, the clock distributor 13, the clock generator 14, the starting pulse counter 15, the operating mode changing unit 16, the input of the first key 5 is connected to the input source Uj , the output of the first key 5 is connected to the output of the second key bis first by the input of the comparator unit 1, the second input of the comparator unit I is connected to an equilibrium output of the memory unit 2.  The output of the comparison unit 1 is connected to the first input of the memory 2, to the input of the shift register 3, to the inputs of the second decoder 11.2 and the third decoder P. H block 7 control,.  The output of the pulse generator 4 is connected to the second input of the memory block 2.  The outputs of the register 3 shift connected with the inputs of the first decoder 1 1, 1, the second decoder 11. 2 and the third decoder 11. 3  The information output of the memory block 2 is co & miien with the information output of the device 17 and with the information inputs of the digital-to-analog converter 8, the register 9 of the maximum and the register 10.  minimum.  Information outputs of the register 9 maxiguma and register 10 mi; The terminals are connected to the information inputs of the digital-to-analog converter 8 and to the information output 17 of the entire device.  The output of the digital-to-analog converter 8 is connected to the input of the second key 6.  The first output 18 and the second output 19 of the distributor 13 clock pulses are connected to the first and second clock inputs of the shift register 3, the third output 20 of the distributor 13 clock pulses are connected to the single input of the key control trigger 12, the input of the first decoder 11. 1 and control input 20 entering the code of the digital-to-analog converter 8.  The fourth output 21 of the clock distributor 13 is connected to the zero input of the key control trigger 12 to the inputs of the second and third decoder 11. 2 and 11. 3, to the control input 21 of the permission to issue the code of the memory block 2.  The fifth output of the clock distributor 13 is connected to the input of the operation mode changing unit 16.  The generator output 14 clock pulses connected to the first input. distributor 1 clock pulses and to the input of the block. 16 changes in operation mode. The installation input of the key control trigger 12 is connected to the stan- eral output of the unit 16, the first control output of which is connected to the second decoder.  P. 2, and the second control output is connected to the corresponding input of the distributor 13.  The output of the starting pulses of the block 16 is connected to the counting input of the counter 15 starting pulses, the first output of which is connected to the input of the second decoder 11. 2, and the second output - to the inputs of the second and third decoders 11. 2 and 11. 3  The control inputs for issuing the register code of maximum 9 and minimum 10 are associated with.  the first 22 and second 23 outputs 98 of the first decoder 11. one.  The control inputs by entering the code of the registers of maximum 9 and minimum 10 are connected to the first 24 and second 25 outputs of the second decoder 11. 2  The control input 26 of the first key 5 is connected to the zero output of the key management trigger 12, and the control input 27 of the second key 6 is connected to the single output of the trigger 12.  The setup output 28 of the operation mode changing unit 16 is connected to the installation inputs of the memory unit 2, the shift register 3, the digital-to-analog converter 8, the registers of maximum 9 and minimum 10.  The output 29 of the readiness code of the memory block 2 is connected to the corresponding input of the operation mode changing unit 16.  The output 30 of the starting pulses of the block 16 is connected to the corresponding input of the block 2 of the memory.  Input code bus 31 of block 16 is connected to the input of the entire device.  The information outputs of block 2 of memory, registers of maximum 9 and minimum 10 are connected to the information output bus 17 of the entire device.  Output bus 32, feature code of the third decoder 11. 3 is connected to the output bus of the feature code of the entire device.  The proposed device can operate in the modes of searching for the smallest and largest values and the search for global extremes.  In the Search for the smallest and largest values of the device operates as follows. ° After the mode code for operation 31 is received from installation output 28 of block 16, the mode of operation is changed to installation inputs 28 of memory block 2, shift register 3, digital-to-analog converter 8, maximum 9 and minimum 10 registers, key management trigger 12 receives the initial setting signal.  In this case, the trigger 12 is set in such a position that the signal from its zero output closes the first analog key 5, and the signal. from its single output 21 it opens the second analog; 1 key 6 ,, the input signal Uj, via an analog key 5, connects to the input of the unit 1 comparing analog signals.  Output 30 of block 16 for changing the operation mode to input 30 of memory block 2 receives the first Start signal. This signal is used to automatically compensate the input signal Uy.  The first Start signal also arrives at the counting input, a chute of 15 trigger pulses, and then at the first output of the counter 15, a resolving potential arrives at the input of the second decoder 11. 2, After the completion of the autocompensation, the balance signal Unp is set at the analog output of the memory unit 2. equal to the precision of the autocompensation of the input signal. , and) (, from the output 29 of the memory block 2, the code readiness signal is fed to the input of the operation mode changing unit 16. After a certain period of time, determined by a code arriving at input 31 of block 16, from the second output of block 16, a potential arrives at the corresponding input of the distributor 13 clock pulses, which allows the pulses of the generator 14 clock pulses to pass to the distributor 13.  After the first pulse arrives from the clock generator 14, a signal appears at the first input of the clock distributor 13, at the first output 18 of the distributor 13, after the second pulse appears, a signal appears at the second output 19 of the distributor 13 and so on. d.  According to the signal from the first output 18 of the distributor 13 in the register 3 shift information from the trigger for the first time, the row is transferred to the trigger of the second.  bit  At this point in time, the input analog signal is equal to the value Uyi, which through the first analog switch 5 is fed to one input of the analog signal comparison unit 1.  At the second input of unit 1 of comparison, the counterbalancing signal Uyp is supplied.  At the output of the comparator unit 1, there is a digital signal, which is determined by the increment sign D i, jCsigti U j. ) between analog signals Ux ,. and uyf).  If Uxj Uyp (signAU. ), then at the output of the comparison block 1, if Vy, Uj. p (sign4U j 0), then at the output of the comparison block O.  According to the signal from the output 19 of the distributor, 13 clock pulses from the output of the block 1 of comparison, the value of sigiuSUj is entered into the trigger of the first bit.  According to the signal from the output 20 of the distributor, 13 clocks of information from the register 9 of the maximum or from; register 10 minimum is entered in the register of the digital-to-analog converter 8.  On the same signal trigger. 12, the key management is pushed over the single input.  At the same time, the first analog switch 5 is disconnected, and the second analog switch 6 is closed, and the analog signal from the output of the digital-to-analog converter 8, corresponding to the code of the highest signal value or the code of the smallest value of the signal stored in the registers of maximum 9 or 1 of 10, is compared in comparison block 1 analog signals with a Uyp signal.  At the output of block 1, a digital signal is set, which does not depend on the value of the incrementing sign (signAU, u. , n) with DSP and USP signals.  If Uu ,, (signAU4Hj, 0), at the output of the comparison block G, if Ua, c. . , p, (signAU, p), at the output of the comparison block O.   On the following signal from the output 21 of the distributor, 13 clock pulses in the registers of maximum 9 and minimum 10 enter the value of the KX code, respectively.  corresponding to the analog signal Uj {, i.  The key manager flip-flop 12 is thrown over the zero input, the outputs of the flip-flop 26 and 27 act on the control inputs of the keys 5 and 6, and the analog key 5 of the sahbiKaeTCH, and the analog key 6 opens.  The next fifth signal from the output of the distributor 13 clock pulses is fed to the input of the change block 16, the operating mode, from the output 30 of which to the input of the memory block 2 receives the second Start pulse.  This signal is the process of autocompensation of the input signal Uj (,.  The second Start signal also arrives at the input of the counter 15 trigger pulses, after which the first potential appears on its first output, and on the second, it permits saving for the next subsequent device operation time and arriving at the corresponding inputs of the second and third decoders 11. 2 and P. H.  After the end of the autocompensation, the analog output of the memory 2 is set to balance the signal U, jp equal to the accuracy of the autocompensation discretion of the input signal, Zu.  , from the output 29 of the block 2 of memory, the code readiness signal is fed to the input of the block 16 for changing the operation mode.  After a certain time interval, defined by a code at input 31 of block 16, from the second output of block 16 to the corresponding input of the distributor 13 clock pulses / potential is received, which allows pulses of the generator 14 pulses to pass to the distributor 13 According to the signal from the first output 18 of the distributor 13 in the shift register 3, the value stored in the trigger of the first bit is transferred to the trigger of the second bit.  At this time, the input analog signal is equal to the value U, which through the first analog switch 5 is fed to one input of the analog signal comparison unit 1.  The second input of block 1 receives the balancing signal Uyp ,,.  At the output of comparator 1, there is a digital signal, which is determined by the value of sign / lUjj. By the signal from the output 19 of the distributor 13 clock pulses from the output of the comparator 1, the value of siguAU j is entered into the first-bit trigger.  If in shift triggers 3, the value of the analogue is stored in the signal UK, is on the increasing input signal, and if O, then on the descending signal.  If in the first half of the first half is stored, then and, is the maximum t 11I of the signal, and if in the first discharge of G, O, then Uy is the second in the second U, the minimum of the signal.  The signal from the output 20 distribution. File 13 at the output 22 of the first decoder 11. 1, a enable pulse appears whereby information from the maximum register 9 is transferred to the register of the digital-to-analog converter 8, if code 11 or 01 is stored in the shift register 3 If the code 00 or 10 is in the shift register 3, then the register of the digital-analog converter 8 is transferred information from the register of minimum 10; According to the same signal, information from registers 9 and 10 is fed to output 17 of the entire device, and the trigger 12 for controlling the keys is transferred over a single input.  At the same time, the analog key 5 is disconnected, and the second analog key 6 is closed and the analog signal from the output 912 of the digital-to-analogue transform 8, corresponding to the code of the highest MAX signal value or the code of the smallest signal GAL stored 11x, respectively, in the registers of maximum 9 or minimum 10 is compared on the block.  1 compares analog signals with a Uijp-signal.  If the output of block 1 is set to a digital signal, which depends on the value of signAUgyj, If a register from the register of maximum 9 and,) p was recorded in the register of digital-to-analog converter B, then the signal from the output 21 of the distributor 13 clock pulses of the permission pulse from the output 24 of the second decoder P. 2 is not, and in the register of maximum 9 the code value remains. , which was in it earlier, if, then, to the register of maximum 9, the signal from the output 21 of the distributor 13 receives from the output 24 of the second decoder the permission to enter the KX code from the output of the 2-ty block.  The same code goes to output 17 of the entire device.  The output of the signal 25 also allows the output of the feature code to output 26, If the register of the digital-to-analog converter 8 recorded the code from the minimum register 10, then the signal from output 21 in the minimum register 10 contains the code that was in it.  It is, because the resolution signal is from the output 25 of the second 1G decoder. 2 does not arrive. -If a signal is output from output 25 of the second decoder 11.2, allowing the code KXj to be written, from memory block 2 to the minimum register 10, Key control trigger 12 is thrown over a zero input, and analog key 5 closes, and analog key 6 opens .  The next fifth signal from the output of the clock distributor 13 is fed to the input of the operation mode changing unit 16, from output 30 of which the third pulse Start is sent to the input of memory 2, This signal is used to automatically compensate the input signal Uj,.  In the future, the device works in the same way as when a second Start signal is received.  Thus, in the register of maximum 9 and register of minimum 10, the codes of the largest and smallest values of the input signal, which j and the digital code of each value of the input signal, accumulate at output 17 of the entire device, are accumulated. properties.  The Global Extremum Search mode differs from the described mode by the conditions under which information is entered into the registers of maximum 9 and minimum 10.  From the first output of the change mode unit 16, a potential arrives at the input of the second decoder 11.2, according to which the signals at the outputs 24 or 25 appear only after 9, the local maximum codes appear.  01 or local minimum 10 at the output of register 3 shift.  The codes КХ f ,, jj or from the output of block 2 of memory for the first time are entered into the registers of maximum 9 and minimum 10.  In the subsequent block 1 comparison of analog signals, the values of Icr are compared with, corresponding to the local and global maxima or the local and global minima.  The invention makes it possible to determine the largest and smallest signal values, as well as global extremum values at a given time interval.

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Claims (1)

A DEVICE FOR SEARCHING EXTREMUMS OF A SIGNAL, comprising a comparison unit, a maximum register, a minimum register, a memory unit, a pulse generator, and a two-bit shift register, wherein a balancing output of the memory unit is connected to the second input of the comparison unit, the outputs of the comparison unit are connected to the first inputs of the memory unit and to the inputs the shift register, the output of the pulse generator is connected to the second input of the memory unit, characterized in that, in order to expand the functionality of the device, two keys are inserted into it, digital the analog converter and the control unit, which consists of the first, second and third 'decoders, a key control trigger, a clock distributor, a clock generator, a unit for changing operating modes, a start pulse counter, and the outputs of the shift register are connected to the inputs of the first, second and third decoders, and the outputs of the comparison unit are connected to the inputs of the second and third decoders, · the first and second outputs of the distributor2 For clock pulses are connected respectively to the first and Orom · synchronizing inputs of the shift register, the third output of the clock distributor is connected to the input of the first decoder and a single input of the key trigger, the fourth output of the clock distributor is connected to the inputs of the second and third decoders and to the zero input of the key trigger, the fifth output of the clock distributor is connected with the input of the unit for changing operating modes, the installation input of the key management trigger is connected to the installation output of the unit for changing modes p Works, the output of the clock generator is connected to the inputs of the clock distributor and the • unit for changing operating modes, the first control output of the unit for changing operating modes is connected. with the input of the second decoder, the second control output of the unit for changing operating modes is connected to the corresponding input of the clock distributor. pulses, the output of the start pulses of the unit for changing operating modes is connected to the counting input of the start pulse counter, the first output of which is connected to the input of the second decoder, and the second output is connected to the inputs of the second and third decoders, the input of the first key is connected to the input signal source, the outputs of the first and the second keys are connected to the first input of the comparison unit, the control input of the first key is connected to the zero output of the key management trigger, the control input SU „972949 of the second key is connected to the single output of the key management trigger, the input of the second key is connected to the output of the digital-to-analog converter, the control input of which is connected to the third output of the clock distributor, and the information input is connected to the information outputs of the memory block and maximum registers and (minimum, the information inputs of the maximum and minimum registers are connected to the information output of the memory block, the information outputs of the memory block and the maximum registers and. | minimum are connected to the information onnomu output device issuing control inputs of the maximum and minimum code registers are connected to first and second outputs of the first deshifratr- 2 pa, respectively, control inputs entering the maximum and minimum registers code associated with the first and second outputs of the second decoder, respectively, a control input, the storage unit ⁴ Start connected to the output of the starting pulses of the unit for changing operating modes, the control input of the permit for issuing the code of the memory block is connected to the fourth output of the clock distributor, shift outputs th register coupled to a third input of the decoder, you are a ready _to move the storage unit connected to the code 'corresponding input unit changes modes of operation, adjusting the inputs of the storage unit, a shift register, a digital to analog converter, the maximum and minimum register output connected to the mounting unit changes modes , the input code bus of the operating mode change unit is connected to the input code bus of the operation modes of the whole device, the output code bus of the third decoder's control unit It is connected to the output bus of the feature code for the entire device.