SU970665A2 - Pulse delay device - Google Patents

Description

(54) PULSE DELAY DEVICE

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The invention relates to a pulse technique and can be used in devices for discrete information processing.

By bus 687596 a pulse delay device is known that contains a clock generator with its first inputs connected to it, an inverter, a counting trigger, a reversible counter and a multi-pass valve, the valve outputs are connected to the summing and subtracting inputs of a reversible counter, respectively, the outputs of the latter are connected to the outputs of the multi-input valve, the output of which is connected to the installation time of the counting trigger, another input of the first valve is connected in parallel to the input terminal and through the inverter to the control input Odam counting trigger, non-inverting output of which is connected to the second input of another valve.

A disadvantage of the known device is the impossibility of obtaining a sequence of periodically repeated cix pulses, the duration of which is equal to the duration of the input (master) pulse.

In devices for discrete processing of information, it often appears that one needs to learn about a sequence of periodically repeating pulses, the duration of which is equal to the duration of a single reference pulse.

The purpose of the invention is to expand the functionality of the device.

The goal is achieved by the fact that a pulse delay device containing a clock generator with its first

15 valve inputs, an inverter, a counting trigger, a reversible counter and a multi-input valve, the valve outputs are connected respectively to the summing and subtracting inputs of a reverse counter, the last inputs are connected to the outputs of a multi-input valve, whose input is connected to the installation input of the counting trigger, another input of the first valve 25 is parallel to the ground terminal to the input terminal and through the inverter to the control inputs of the counting trigger, the non-inverting output of which is connected to the second input of another valve,

30 introduced an additional item OR,

the third and fourth valves, the delay element, the second reversible counter, the second multi-input valve and the second counting trigger, the control inputs of which are connected to the inverting output of the first counting trigger, and its non-inverting output is connected to the input of the delay element and the second input of the third valve, the first input of which connected to the output of the clock generator, and the output to the subtractive input of the second reversible counter, the outputs of which are connected to the inputs of the second multi-input valve connected to the output The new input of the second counting trigger, the summing input of the second reversing counter is connected to the subtractive input of the first reversing counter, and the output of the delay element is connected to the BTopojviy input of the third valve, the first input of which is connected to the control bus, and the output is connected to the second input of the Element1 OR, output which is connected to the parallel-connected inputs of the first fan and the inverter, and the first input is connected to the input bus,

Figure 1 shows the functional diagram of the device; 2 and 3 are timing diagrams explaining its operation.

The device contains a tactical generator 1, the output of which is connected to the first inputs of the first valve 2 and the second valve 3. Parallel to the second input of the first valve 2, the input of the inverter 4 is connected. The outputs of the first and second valves 2 and 3 are connected via series-connected first reversing counter 5 and the first multi-input valve 6 to the installation input of the first counting trigger 7, the non-inverting input of the connected 1O with the output bus 8 and the VTO1Zh1M input of the second valve 3, and the inverting output connected to the control inputs of the countable trigger 9, the non-inverting output of which is connected directly to the input of the third branch U and through a successively connected delay element 11 and the fourth valve 12, another input connected to the control, or another 13 qo6edinen with bus 15 input signals, while the output of the third valve 10 is connected to the subtractive input of the second reversible counter 16, the output of which is connected to the inputs of the second multi-input valve 17.

The device works in two modes. In the first mode (Fig. 2) device

The device provides a delay of pulses of random duration for their duration. In the second mode (Fig. 3), the device forms a sequence of periodically repeated pulses due to the continuous circulation of a single pulse of random duration in the pulse delay device closed in a ring. In the delay mode, pulses of random duration for their duration.

The device works as follows.

At the initial moment, the first 5 and second 16 13 counters, as well as the first 7 and second 9 counting triggers are in the zero state. When the input pulse (Fig. 2a) arrives at the device input bus 15 and a low level signal (Fig. 2b), the OR element and the first valve 2 are opened on the device control bus 13, connecting the output of the clock generator 1 to the summing input of the first 5 reversing counter. The up / down counter 5 counts in the forward direction the pulses arriving at its input up to the end of the input pulse. At the end of the input pulse, the first 2 valve closes, disconnecting the summing input of the first 5 reversing counter from the clock generator 1. In the reversing counter 5, a number is recorded that is proportional to the duration of the input pulse. The high level signal (Fig. 2c), appearing at the end of the input pulse at the output of the inverter 4, affects the information inputs of the first 7 counting flip-flop, with the result that the leading edge of the output pulse is formed at the non-inverting output of this flip-flop (Fig. 2 d ). The output pulse opens the second valve 3, connects the output of the clock generator 1 with the subtractive input of the first 5 reversing counter. The reversible counter 5 starts counting in the opposite direction before zeroing. When the reversing counter 5 is zeroed, the high level signal appears on the output of the first multi-input valve 6 (Fig. 2g which sets the first 7 counting trigger to the zero state, thereby forming the trailing edge of the output pulse (Fig. 2 d). This closes the second 3 valve, disconnecting the subtracting input of the first 5 reversible counter from the clock generator 1. As a result, a pulse is removed from the output bus 8 of the device (figure 2) delayed relative to the input (figure 2 a) for a time equal to its duration.

In the continuous circulation mode of a single pulse of random duration, the device operates as follows.

When the input pulse (Fig. 3a) arrives at the device input bus 15 and a high level signal (Fig. 3 b), the first 2 valve opens on the control bus 13 of the device, connecting the output of the clock generator 1 to the summing input of the first 5 reversible counter. The reversing counter 5 counts in the forward direction the pulses arriving at its input up to the end of the input pulse. At the end of the input pulse, the first 2 valve closes, disconnecting the summing input of the first 5 reversing counter from the clock generator 1. In the reversing counter 5, a number is recorded that is proportional to the duration of the input pulse. The high level signal (Fig. 3c), appearing at the end of the input pulse at the output of inverter 4, does not affect the control inputs of the first 7 counting trigger, with the result that the leading edge of the first output pulse is formed at the non-inverting output of this trigger (Fig. W e); The output pulse opens the second 3 valve, connects the output of the clock generator 1 to the subtracting input of the first 5 reversing counter and the summing input of the second 16 reversing counter. Reversible counter 5 counts in the opposite direction and reversible counter 16 counts in the forward direction,

The 8 moment of zeroing the first 5 reversible counter in the second 16 reversing counter will be recorded a number proportional to the duration of the first output pulse, the duration of which is equal to the duration of the input pulse.

By resetting the first 5 reversible counter at the output of the first multi-input valve 6, a high level signal is received (FIG. 3 d), which sets the first 7 counting trigger to the zero state, thereby forming the trailing edge of the first output pulse (FIG. 2 d). This closes the second 3 valve, disconnecting the subtracting input of the first 5 reversing counter and the summing input 10 of the reversing counter from the clock generator 1.

The high level signal that appears after the end of the first output Go of the pulse at the inverting output of the first 7 counting trigger affects the control inputs of the second

9 counting trigger, resulting in a non-inverting output of this trigger

high signal level The output signal from the non-inverting output of the second 9 counting trigger opens the third 10 gate I, connecting the output of the clock generator 1 to the subtractive input of the second 16 reversing counter. The reversible counter 16 begins counting in the opposite direction before zeroing. When resetting the reversible counter 16 at the output

0 of the second multi-input valve 17, a high level signal appears, which sets the second 9 counting trigger to the zero state, thereby forming the trailing edge of the signal at the output of the second 9 counting trigger, delayed relative to the {first output pulse of the device for a time equal to duration.

Signal with non-inverter output

0 of the second 9 counting trigger via delay element 11, the open fourth 12 valve and the OR 14 element opens the first 2 valve, connecting you, the clock generator 1 to the cyMNmpy5 to the first input of the first 5 reversing counter. Next, the device operates in accordance with the above algorithm, forming on the output bus 8 a second, third, etc. impulses

0 (fig.Z d), the duration of which is equal to the duration of a single input pulse / FIG. A). Termination of the formation of a sequence of pulses is provided by removing the high level signal from the control bus 13,

five

Thus, the introduction in the proposed device of the pulse delay of the second reversible counter of the second multi-input valve, the second counting trigger, two valves,

0 of the OR element, the delay element, and the new connections, which ensure the interaction of all the units of the device, expands the functional capabilities of the pulse delay device by forming a sequence of periodically repeated pulses at the device output, the duration of which is equal to the duration of a single input pulse.

The formation of this sequence of pulses is ensured by the continuous circulation of a single pulse of random

5 duration in the device delay pulses, closed in a ring. The proposed device allows you to easily change the period of the appearance of the output pulses, without changing

0 clock frequency. The period of occurrence of output pulses in the device depends only on the duration of the input single pulse circulating in the device of the pulse delay.

Fort-tula of the invention. The device is a delay of pulses according to the author. No. 687596, which means that, in order to expand its functionality, an additional OR element, a third and a fourth valve, a delay element, a second reversing counter, a second multi-input valve and a second counting trigger, were introduced into it, The control inputs of which are connected to the inverting output of the first counting trigger, and its non-inertigogue output is connected to the input of the delay element and the second input of the third valve, the first input of which is connected to the output of the clock generator, and the output to the subtractive input

The second reversible counter, the outputs of which are connected to the inputs of the SECOND multi-input valve connected to the installation input of the second counting trigger, the summing input of the second reversal counter connected to the subtracting input of the first reversing counter, and the output of the delay element connected to the second input of the third valve, the first input of which connected to the control bus, and the output is connected to the second input of the OR element, the output of which is connected to the inputs of the first valve and in parallel connected in parallel ertora, a first input coupled to the input bus.

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Claims (1)

Claim Pulse delay device for auto II 687596, cast it leaner with the fact that, in order to expand the functionality, an additional OR element, a third and fourth gate, a delay element, a second reversible counter, a second multi-input valve and a second counting trigger, the control inputs of which are connected to the inverting one, are introduced into it the output of the first counting trigger, and its non-inverting output is connected to the input of the delay element and the second input of the third gate, the first input of which is connected to the output of the clock generator, and the output to the subtracting input of the second roar a dividing counter, the output of which is connected to the inputs of the second multi-input valve, connected by the output to the installation input of the second counting trigger, where the summing input of the second reversing counter is connected to the subtracting input of the first reversing counter, and the output of the element behind, θ of the holder is connected to the second input of the third valve, the first input connected to the control bus, and an output connected to a second input of OR gate whose output is connected to the parallel connected inputs of the first gate ¹⁵ and an inverter, and n rvy input connected to the input bus. (past Fig. 2