SU951314A1 - Program debugging device - Google Patents

Description

The invention relates to computing technology and can be used in automated debugging of programs of specialized digital control systems in real time.

A device for debugging programs is known comprising an on-line memory, a number register, an address register, an exchange register, a tape drive, a perforator and a keyboard unit 1,

The disadvantage of this device is the low speed of debugging programs.

The closest to the invention to the technical essence is a device for debugging programs, containing an operational memory OP (DSS), connected by information input and output with the first output and input of the receiving and issuing numbers and commands, the second output of which is an information output device the address generation unit connected by the output with the address input of the OP, and the first input with the address device, the control unit whose first and third inputs are command inputs and

the output is connected to the input of the accession OP 2.

The disadvantage of this device is that it does not allow debugging of the main program during its execution, since it requires stopping the main program for the duration of its correction. And it does not allow: to debug programs when you turn on real hardware in the simulation loop. for stopping the program being debugged leads to additional delays and distorts the modeling process.

The purpose of the invention is to reduce the debugging time of programs when working in real time.

This goal is achieved in that the device containing the memory block, the first number register, the first address register, the control block containing the pulse generator, the OR element, two AND elements, the first input and the output of the first number register are connected to the first output and input the memory unit, the second input of which is connected to the output of the first address register, the first input B. of which is the first address input of the device, the second output of the first number register is the first information output of the device, the third input of the memory block is Connected to the first output of the pulse generator, whose input is connected to the output of the OR element, the first and second inputs of which are connected respectively to the outputs of the first and second And elements, the first input of the first And element is the first input of the device inversion commands, the first input of the second And element is the second input of the device reversal commands is entered in the second register of the number, the second address register, the channel priority connection block containing two AND-NOT elements, two D-flip-flops, two AND elements, two impulse drivers, the first inputs and outputs of the second number register are connected respectively to the second output and the fourth input of the memory unit, the fifth input of which is connected to the output of the second address register, the first input of which is the second address input of the devices, the second input and the output of the second number register are respectively the information input and the second information output of the device, the third input of the second number register and the second input of the second address register are combined and connected to the output of the third element Nick to the input of the first form pulse generator and is the device control output, the second inputs of the first register of the number and the first address register are combined and connected to the Q-output of the first D-flip-flop and to the input of the second driver, the output of which is combined with the output of the first driver of the pulses and connected to the third input of the block control, the second output of which is connected to the C-inputs of the first and second triggers, the S-inputs of which are connected respectively to the outputs of the first and second elements AND-NOT, the first inputs of which are combined and connected to the output of the fourth And, the first input of which is combined with the first input of the third element AND and connected to the .Q output of the first trigger, the D input of which is connected to the second input of the first AND element and is the first input of the device requests, the second inputs of the third and fourth And elements are connected respectively to the Q and Q outputs of the second trigger, the D input of which is combined with the second input of the second AND-NOT element and is the second input of the device requests.

Figure 1 shows the functional diagram of the device; in Fig. 2, the control unit, the circuit in Fig. 3, the priority connection unit, the circuit,

Diagram of the device (Fig. 1) including register number 1, address register 2, memory block 3, control block 4, channel 5 priority connection, address register 6, number register 7, information outputs 8, 9 and input 10, address inputs 11 and 12, inputs 13 and 14 of the access command, inputs 15 and 16 of the request for access to the memory block, control output 17, elements 18 and 19 AND, element OR 20, pulse generator 21, elements 22 and 23 AND-NOT, D -triggers 24 and 25, the elements 26 and 27 And, formers 28 and 29 pulses. The device works in conjunction with a digital computer and a specialized computing device (VCA A specialized computing device is, in particular, a digital control part of the control system (onboard digital computer). It implements a program for processing the initial information and generates control signals to the control object, and also performs other functions.

Before the start of debugging, the main and service programs through registers 1 and 2 are entered into the PD. The debugging of the main program is carried out with the help of a utility program, which is intended to correct the program sections or individual commands and operands of the main program. There are two access channels in the device in the device: the VCA channel of the main program of the program and the DVR channel of the service npprpaMf j. The channel is connected to the OP by block 5 according to the priority principle as follows. In the case of channel fetch operations, requests are received for access to the PD. Channel of VCA has priority on access to memory in relation to channel of digital computers, i.e. while simultaneously receiving requests from the VCA and the digital computer, unit 5 connects the main program channel to the memory. The utility channel is waiting for a connection to the OD until the main program channel clears its request. This happens at the completion of the VCA of the sampling cycle from Psi-1 and the beginning of the operations of the execution cycle. According to the signal of the end of the sampling cycle from the memory, block 5 connects the utility program channel to the PD and the digital computer begins performing sampling operations from the PD. Upon the next request from the VCA, unit 5, waiting for the signal to end the memory cycle, disconnects the utility program channel and reconnects to the main program OP. During the execution of the main program in the operations of sampling the number or command from the OP on

control input 16 from the VCA receives a request for access to IT. At address input 12, register 6 is supplied with the address of the matching OP cell, and at input 14, the address command is sent to the block. The signal from the end of the memory cycle, coming from the second output of block 4 to the third input of block 5, in the latter, the enable signals coming from its first output to registers 6 and 7, and the control coming from the third output of block 5 to the third input of block 4 The enable signals connect registers 6 and 7 to the first address input and the information input and output of the auxiliary signal. The control signals open the first input of block 4, and the access command from input 14 goes to block 4. With this command, the control unit generates control signals OP for reading information from the first output of block 4 to the control input of memory block 3. The information read from the PD is output through register 7 to information output 9 of the device.

When executing the utility program during read or write operations in the PD from the digital computer, the input to the device 15 receives a request for access to the memory. It is waiting until the end of the sampling cycle of the OP performed by the VCA. Upon completion of the VCA sampling cycle, it removes the request signal arriving at the first input of unit 5. And the signal from the end of the memory cycle sent from the second output of block 4 to the third input of block 5, the latter generates resolution signals from its second output to registers 1 and 2 and control output 17 of the device. At the same time, the third output of block 5 receives a signal that opens the second input of block 4. When a signal appears at output 17, the digital computer sends a command to the device's input 13 and the address of the OD cell to input 11. The control command in the block 4 generates an OP control signals for reading when recording information sent from the first output of the CU to the control input of the OP. The address from the output of the register 2 is fed to the second address input of the unit 3. The readable information from the second information output of the OP via the first input and the second output of the register 1 is output to the output 8 of the device. When recording information from input 10 of the device through the second input and the first output of register 1, it arrives at the second information input of block 3. When receiving requests for access to the memory from the digital computer and the VCA or only the request from the VCA, the control signal (FOR) coming from the block 5 to the third input of block 4, passes through the AND 19 element the signal of circulation from the VCA,

to the input of block 4 (figure 2). This signal through the element 20 OR starts the generator 21 pulses (GI). The generated pulses from the first output of block 4 enter the random access memory (OP) and control the read and write processes. The second output of block 4 receives the end of memory cycle signal. When receiving a request from the digital computer for access to the memory (and no request from the VCA), the control signal (SG), which arrives at the third input of block 4, allows the signal from the second input of block 4 to pass through the I 18 element. access signal from

5 digital computers, which, in a manner similar to the specified sequence, form the control signals OD and the signal End of Memory Cycle. Block 5 is designed for priority connection kana

0 catch digital computers and VCA through the registers of the address and number to the RAM. The VCA channel takes precedence over the DVR channel.

With the simultaneous receipt of requests for access to the PD from the digital computer (input

5 15) and VCA (input 16) by the signal of the end of the previous memory cycle, coming from block 4, in block 5, the load enable signal of the registers PA1 and P41, serving the VCA, is generated. Simultaneously with the permission signal from the third output of the BPC, block 4 receives a control signal (FOR). The request from the DVR is pending until

5 remove request signal from VCA. Thus, the request from the digital computer is serviced if the request from the VCA is removed and the signal is received. The memory cycle ends from block 4. At the same time, a signal is output from the second output of block 5 allowing the loading of the PA2 and P42 registers and also arriving at the output 17 of the device. From the third output of block 5, the signal ZV comes out. Upon receipt of a response to an access request

5 in the OP from the output 17 of the digital computer device sends a command to access input 13 and the address of the memory cell to input 11.

Parallel execution of main and utility programs allows

0 to debug the main program during its operation. Consequently, the device makes it possible to debug programs when simulating with real equipment.

5 automatic and semi-automatic control systems in real time.

60

Claims (2)

Invention Formula Device for debugging software "1m", containing a memory block, first number register, first address register, 65 control unit, containing pulse generator OR element, two AND elements, with the first input and output of the first number register connected to the first output and input of the memory block TI, the second input of which is connected to the output of the first address register, the first input of which is with the first address input of the device, the second output of the first number register is the first information output of the device, the third input of the memory unit is connected to the first the output of the pulse generator, the input of which is connected to the output of the OR element, the first and second inputs of which. connected, respectively, to the outputs of the first and second elements AND, the first input of the first element I is the first input of the device access commands, the first input of the second element I is the second input of the commands of the device address, the first and the second that, in order to reduce the debugging time of programs when working in real time, a second number register is entered into it, the second address register, the priority connection block of channels, containing two IS-NOT elements, two D-flip-flops, two elements And, two pulse drivers, and ep stems input and output of the second register are respectively connected to the second output and the fourth input of the memory, a fifth input connected to the output of the second address register, a first input of which is an address vhodsm a second device, the second input and the output of the second D. The gist numbers are respectively the information input and the second information output of the device. the third input of the second number register and the second input of the second register, adJeca, are combined and connected to the output of the third element Nick to the input of the first pulse shaper and is the device control output, the second inputs of the first number register and the first address register are combined and connected to the Q output of the first D- the trigger and to the input of the second driver, the output of which is combined with the output of the first pulse driver and connected to the third input of the control unit, the second output of which is connected to the C inputs of the first and second trigger ov, 5-inputs of which are connected respectively to the outputs of the first and second elements AND-NOT, the first inputs of which are combined and connected to the output of the fourth element And, the first input of which is combined with the first input of the third element And connected to the q-output of the first trigger t is the input of which is connected to the second input of the first NAND element and is the first input of the device requests, the second inputs of the third and fourth AND elements are connected respectively to the O and Q outputs of the second trigger, the D input of which is combined with the second input second uh ementa AND-NO element and is vtorvlm input device requests. Sources of information taken into account in the examination 1. USSR author's certificate № BSOZA, class G About F 11/28, 1978. 2. Authors certificate of the USSR 690482, cl. G On f 11/28, 1979 (prototype).