SU942018A1 - Device for forming command with hardware arrangement of cyclic program - Google Patents

Description

3-94 cyclic programs containing an address memory block, the address input of which is the first address input of the device, the sector number counter, the first control input of which is connected to the 6JloKa control output of the address memory, and the first output output from the control output the input block of the address memory, the block of the buffer command block, the memory block of the significance bits, the block of the memory of the wait bits, whose address inputs are connected to the second address input of the device, the information input of the block of the command buffer memory is informational

device input, first switch, read counter, first, second bit outputs of which are connected to the first input of the first switch and to the first read inputs of memory 2 of the significance and wait bits respectively, the next sector register, destination address register, the first information inputs of which are connected with the second bit output 25 of the sector number counter, the second information inputs of the next sector register and the destination address register, and the second input of the first switch are connected to the information the output output of the address memory block, the bit output of the next sector register is connected to the third input of the first switch, the output of which is connected to the read input of the block of the command buffer memory and to the information input of the read counter, and the bit output of the register of the destination address is connected to the second read inputs blocks of memory of bits of significance and expectation and with the output of the destination address of the device, the first, second, third and fourth command registers whose information inputs are connected to the first output of the block buffer command memory, command unpacking node, each information input of which is connected to a bit output of the corresponding command register, a command significance trigger block, whose zero input is connected to a block output output of the command buffer memory block, a reset input of the command significance trigger block is connected to zero command output unpacking command words. and the output is connected to the input of significance

command word decompression node, the first ILU element, the output of which is the indicator output, the device output of the device is connected to the output of the command word decompression node, the first comparison circuit, the output of which is the first control output of the device, the second command index register, the bit output of which is connected with the first input of the first comparison circuit, the second switch, the output of which is an index output of the device and connected to the second information input of the first command index register, is a bit output which is connected to the second inputs of the command index adder, summing words, the output of this decoder is connected to the control input of the first comparison circuit, the second input of the decrypt, the first input of the OR element is connected to the output of the memory block of the wait bits, the second input of the first OR element and the unit the input block of the trigger of the command significance is connected to the output of the memory block of the significance bit, the decoder of the command length, the first register of the command index, the adder of the command index, the first input of which is connected to the output of the decoder of the command length The output is connected to the first information input of the first register of the command index, the transition index adder, the first input of which, the input of the length decoder of the command and the command of the transition index, the first comparison circuit and the control input of the command unpacking node, the third and fourth command index registers , the bit outputs of which are connected to the first and second inputs of the second switch, respectively, the first index buffer register, which caused the cycle, the second index buffer register, the command decoder, the second, tr, are entered. th and fourth comparison circuits, the second OR element, the first address register, the first buffer register, the second address register, the third buffer index register, the address buffer register, the third address register, the information inputs of the first index buffer register and the second index buffer register are connected to the bit output of the first command index register, the bit outputs of these registers are connected to the information inputs of the second and third command index registers, respectively, the first input of the command decoder In addition, the command commander unpacking unit unnumbered output is connected to the output of the second comparison circuit and the second control output of the device, the first inputs of the third and fourth comparison circuits are connected to the second discharge output of the sector number, the inputs of the second OR element are connected to the outputs. Third and fourth comparison circuits, the output of the second element OR is connected with. the second control input of the sector number counter, the buffer out register bit output is connected to the fourth input of the first switch, the first output address register bit output is connected to the fifth input of the first switch and the second input of the third comparison circuit, the information input of the second address register is connected to the first input the second comparison circuit, with the first information input of the first address register, with the information input of the buffer register, and with the second bit output of the read counter, the first 11 information input of the the second index buffer register is index; the second information input of the third buffer index register is connected to the output of the transition index adder; the bit output of the third index buffer register is connected to the information input of the fourth command index register, to the third input of the second switch, and the index input of the block address memory and with the second information input of the first address register, the first information input of the address buffer register is connected to the bit output of the second register The address path, the second information input of the buffer register of the address is connected to the bit output of the first command index register, the information input of the third address register is connected to the bit output of the buffer address register, the bit output of the third address register is connected to the second inputs of the second and fourth comparison circuits. Figure 1 presents the scheme of the proposed device; Fig.2 is a block diagram of a command unpacking node; FIG. 3 is a block diagram of the primary switching control node; FIG. 4 is a diagram of a site for generating significance; Fig. 5 is a schematic of the nulling control node. The first comparison circuit 1, the second switch 2, the second command index register 3, the third command index register 4, the fourth command index register 5, the first index buffer register 6, the second index buffer register 7, the third buffer index register 8, command decoder 9, second comparison circuit 10, transition index adder 11, command length decoder 12, command word unpacking node 13, command index adder AND, first command register 15, second. 16 command registers, third register 1 / commands, fourth command register 18, command significance trigger block 19, first element OR 20, first command index register 21, third address register 22, buffer address register 23, second address register 2k, buffer block 25 memory of commands, block 2b of memory of bits of significance, block 27) of wait bits, first switch 28, read counter 29, destination address 30 register, buffer register 31, first address register 32, next sector register 33, third comparison circuit 3 , fourth comparison circuit 35, second element LEE 36, the counter 37 sector number, a block address memory 38, first control output 39, second control output 40 ,. index input 1, command output 42 ,. indicator output 43, index output 44, information input 45, second address input 46 of the device, output 47 of the destination address, first address input 48 of the device. The block diagram of the command word decompression node (FIG. 2) contains the primary switching control node 49, the switch 50, the significance generation node 51, command word zeroing control node 52. The primary switching control block diagram of the switching node (FIG. 3) contains the element OR 53, the element NOT 54, the element And 55, the element OR 56, the element NOT 57. The diagram of the node generating the significance (figure 4) contains the element OR 58, the group of elements AND 59, two. The decoder is 60 and 61, the element And b2, the elements HE 63 and 64 , elements OR b5 and 66, group of elements And 67, group of elements And 68, element And 9, flip-flop 70, an OR gate 71, AND gates 72 and 73, NOT 74 e.pement.

The zeroing control node diagram (figure 5) contains a group of elements OR 75 a group of elements AND 7b, elements NOT 77, 78 and 79, trigger 80.

The device works as follows.

User programs and the operating system are a set of procedures organized into segments of arbitrary length. The required information is accessed via control-descriptor tables. In the general case, the descriptor contains the base — the address of the beginning of a segment of a certain procedure, and, the quantity, the width that determines the size of the segment. Elec's position; The information within the segment is determined by its displacement relative to the base, the so-called. by index.

Each command segment of the corresponding procedure is logically divided into sectors of 1b words. Recent sectors may be incomplete. Block 25, which is part of the device, is -25 On with a sector-type memory, also logically divided into equal sectors by 16 words and contains 32 sectors. Any RAM memory section can be located in any sector of block 25. The correspondence between sectors 38 on the operational and buffer memory is set using block 38. The cells of the 38 NPSF SNF block from base-index pairs of registers so that each pair stores the segment base, the information of which is located in the corresponding sector of block 25i and the index is the sector offset relative to the base. . Swapping in Formations from memory to buffer are produced in blocks of four words. The availability of the required information in block 25 is determined by indicators of the significance of the registers of block 38, block 26 and block 27. The significance of block 38 means that the corresponding sector of block 25 is allocated for the placement of information in it, the segment base of which, as well as the sector index of this information, are stored in corresponding to the cell of block 33. Blocks 26 and 27 are direct-addressed, the number of their cells is equal to the number of sectors of block 25. Each cell of 26 and 27 stores four bits each, whose positions correspond to the numbers of blocks in the sector. A unit in some kind of de block 26 means

the occupancy of the corresponding block 25. The unit in the discharge of block 27 means that a request has been issued to the corresponding block in the operational memory.

The registers of block 38 and sectors of block 25 are assigned to counter 37.

On the linear sections of the program, commands are called from the operational memory of block 25 with some advance

in relation to the level of command decryption. The base command segment through the address input 48 of the device, and the index of the required information through the index input 1 of the device and

the buffer register 8 is fed to the base and index inputs of the block 38, where they are compared simultaneously with all pairs of the base-index registers. The state of the indicator output unit 38

Claims (2)

indicates whether a comparison with one of the base-index pairs occurred or not.  If there is no comparison, then the counter is 37, ko. The second stores the number of the sector to be replaced, transfers it to the register 30.  another input of register 30 is received bits, meaning the block number in the sector, from the output of block 38.  The address thus composed arrives at output 7 of the destination address of the device and, together with the executive address, participates in the generation of a request to the main memory.  In the future, the destination address will accompany the information recalled from the RAM as the entry address in block 25.  After issuing a request, the cells at blocks 26 and 27, except for the bit, are zeroed into the address stored on register 30.  corresponding to the called block, which is set to one.  Next, the state at the base and index inputs of the block 38 is written into the corresponding base-index register pair by the output of the counter 37, after which the counter 37 changes its value by one.  If there is a comparison with one of the base-index pairs, then the code from the output of block 38 goes to register 30.  The contents of this register is the address at which the corresponding bits of significance and expectation are received from blocks 26 and 27, which go to I; the first element OR 20.  The presence of bits of significance or expectation, as indicated by the value of indicator output 3, causes an interruption of the request to the RAM.  The absence of significance and expectation bits leads to the reading of information from the main memory, in this case, as. the destination address uses the contents of register 30, zero and one are written to the corresponding bits of blocks 26 and 27, respectively.  Creating the necessary reserve of commands for decryption eliminates gaps in the stream of commands associated with waiting for information on linear sections of the program.  The four words of the block, called from the RAM, are received through the information input 45 sequentially one after the other, with each word accompanied by the destination address received via the address input 46, the Address input 46 is also connected to the address inputs of blocks 26 and 27, therefore together with writing the last word of the block, in block 25, the corresponding bit of block 26 is written down one, and in the bit of block 27, zero is written.  The reading from block 25 is performed on the control counter 29, One of the outputs of the counter 29 is connected via switch 28 to the input of the read address from block 25, and the other to the read inputs of blocks 2b and 27.  After the next word is read from block 25, the value of counter 29 is increased by one.  When all the words of a certain sector of block 25 are read to decryption, the part of counter 29, meaning the sector number, is updated from register 33 through the switch.  The code on the register 33 comes from the output of the counter 37 or from the output of the block 38 when pre-reading the zero block of the sector.  Thus, the sector in which the continuation of the program is located is always known in advance.  The words read from block 25 through. step alternately on registers 15, 16 or 17, 18, Both pairs of command registers 15, 16 and 17, 1B are equivalent, the selection of a pair for receiving command words changes when branching is performed. Simultaneously with reading the command word from block 25 from block 26, the corresponding the bit and block 19 of the flip-flops are set to the position meaning that the corresponding registers 15-18 are occupied, the output of which is connected to the node 13.  The word length in block 25, registers 15-18, 1810 is eight bytes.  The commands are a tightly packed byte array, the length of the commands is variable and a multiple of a byte.  The node 13 allocates five bytes from the decoded pair of registers 15-18 so that the code (the operations of the selected command turn out to be pressed to the left.  The number of the left (byte relative to the base of the command segment is determined by the register 21, Register 21 controls the decompression of registers 15-18 and generates a stream of commands at command output 42. density one team per cycle on the linear sections of the program.  The decoder 12, after analyzing the operation code, generates an increment value that needs to be summed on the adder 14 with the register 21 in order to proceed to unpacking the next command.  After complete decryption of one of the registers 15, 1b or 17, 18, node 13 changes its state to block 19 of flip-flops, which leads to reading the next control word from block 25 to one of the released registers 15-18.  Branching commands in which the proposed device is involved can be divided into three types: 1) BP type commands - unconditional transfer, 2) UE type commands - conditional transfer, 3) QC type commands - end of cycle.  The format of branch commands includes the operation code and the transition delta — a value that determines how many commands (in bytes) from the decrypted branch command are needed for the program.  The left bit of the transition delta is sign and indicates the direction of branching (forward or backward through the program).  On BP commands, unconditional transfer of control occurs, the UE commands are typical of the cdmsh and conditional transition, the CC commands use the so-called index word.  The index word contains three values: the current index, the increment step, and the limit.  The CC commands check if the current Limit index does not exceed and, if the answer is satisfactory, modify the current index by the increment step and transfer control to the command at the forwarding address.  Yes, as specified in the KC team.  If those-.  The kusch index has reached the limit, control is transferred to the next team.  CC commands are conveniently used for organizing cycles of the type FOR A STEP B DO C CYCLE D, UE commands for organizing conditional operators and cycles of the type FOR A UNTIL A CYCLE D.  When a branch command at the output of node 13 appears on the adder 11, the transition index is formed and received on the buffer register 8.  The output of the buffer register 8 is connected to the index input of the block 38 and, together with the base of the current procedures, arriving at the address input 8, forms the address of the buffer memory.  Next is the analysis of the presence. required information in block 25 and reading it, if the result of the analysis is positive, to the corresponding register assigned for branching.  With commands like BP or KC, a change in the pair of registers 15 1b or 17, 18 occurs, not only on pumping information from block 25, but also on decoding.  When the UE command, the change of the pair of registers 15, 16 or 17, 18 occurs only on swap.  The old value of counter 29 is stored in buffer register 31 at the time of swapping.  two words of teams on a new branch.  This old sign of the read pointer will be required to continue swapping the command words to fail until the transition condition is determined, for which the address from counter 29 goes to buffer register 31 and the address from buffer register 31 goes through switch 28, counter 29 and thus before the branch condition is clarified, conditional decoding of commands in the direction of the wire is carried out continuously. l  If the transition condition is met, the decoded comanr is canceled, the register pair 15, 16, or 17, 18 is changed by decryption, and the address from the buffer register 31 is again sent through the switch 28 to the counter 29 ". Thus, the device starts decoding the commands in the direction on the transition.  In the normal mode, the appearance of a branch command at command output 2 leads to a discontinuity in the flow of deciphered commands, the minimum time of which is determined by the access time through block 38 to block 25.  The execution of cyclic program sections is characterized by multiple.  We repeat the set of commands that form the body of the loop.  A command that closes a loop is usually a branch instruction that analyzes the condition of the end of a loop.  Such a command (CC or UE) is called the instruction that caused the cycle.  When a CC or UE type branch command is decrypted with a negative transition delta, it is assumed that a cycle is organized.  In this case, until the transition condition is clarified, the transition index is stored in the buffer register 8, and the index of the branch instruction itself is stored in the buffer register 6, and the index of the command following the branch instruction is stored in buffer register 7.  In addition, the buffer address 23 stores the address of the word in block 25 containing the branch command.  Minor bits, meaning the word number in the sector, come from register 21, and aging, meaning sector number, register output 24, the contents of which is updated from counter 29 when the decryption moves to the new sector.  If the analysis of the branch condition reveals that it is necessary to complete the transition, information is copied from the buffer registers 6.7, 8 and 23 to the registers-3, 5 and 22, respectively (o.  In addition, after setting the branch address to counter 29, 32 five bits, indicating the sector number, from the counter 29, and bits indicating the word number in the sector, from the register 8, are transferred to the register.  In this case, the device switches to the Cycle mode, which includes the comparison circuits 1, 10, 3 and 35.  In the Cycle mode, the commands are re-executed, starting with the first cycle command, before the command that caused the cycle.  When reading the word from block 25, which contains the command that caused the cycle, the comparison circuit 10 is triggered, which is characterized by the appearance of a signal at the second control output 40 and triggers the following actions.  The contents of register 32 are transmitted to counter 29 through switch 28. Simultaneously with changing the value of trigger 19, when reading the last word of the cycle, the output of comparison circuit 10 causes a change in decoder 9, m. e.  if you encrypt the corresponding word, it will be known that this word contains the command that caused the cycle.  The paging direction of command words from 6rio to ka 25 is changed, the first cycle commands are sent to a new pair of registers 15, 16 or 17. 18 against the background of the decoding of commands from the old pair.  Thus, by the time the command that caused the cycle is decoded, the first commands of the cycle will be read from block 25 and ready to be decoded.  The moment of decryption of the command that caused the cycle is set by the first comparison circuit 1, which is characterized by the generation of a control signal at the first control output 39 and causes the following actions.  The output of register 5 through the second switch 2 is applied to register 21.  The direction of decryption of commands is changed, node 13 switches to a new pair of registers 15, 16, or 17, 18, where the first commands of the cycle are already stored.  Thus, at the same time, after the command of the branch that caused the cycle was decrypted, the command of the branch (output 2 without interruption) is received.  Before the transition conditions are clarified, conditional decoding of the first commands of the cycle is performed.  If you consider that a transition to the beginning of the cycle was necessary, the conditional commands are transferred to normal ones.  If as a result of the analysis of the transition condition it turned out that it is necessary to exit: from the cycle, conditionally decoded commands are canceled, the Cycle mode is removed, the output of register 4 through switch 2 is fed to register 21 and to index output C to change the program command counter.  The command counter will start swapping command words from block 25 (installation of counter 29 will occur via index input 41, buffer register 8, block 38 and switch 28) starting with the word that contains the program continuation after the cycle.  In the Cycle mode, the sectors containing commands of the beginning and end of the cyclic program are protected from substitution. The sector that needs to be allocated for new information is selected by the counter 37.  The moment of comparison of counter 37 with regis; trams 32 or 22 is fixed by comparison circuits 34 and 35, respectively, whose outputs through the second element OR 36 enter counter 37 and cause it to increase by one. Consequently, the beginning and end of the cycle are always in block 25 that provides quick access to the required command information.  Formula of the Invention A device for generating commands with hardware organization of cyclic programs, comprising an address memory block whose address input is the first address input of the device, a sector number counter, the first control input of which is connected to the control output of the address memory block, the first bit output - with control input of address memory block, command buffer memory block, memory block of significance bits, memory block, wait time, address inputs of which are connected to the second address input of devices a, and the information input of the buffer command memory block is the information input of the device, the first switch, the read counter of the first, second bit outputs of which are connected to the first input of the first switch and the first read inputs of the memory blocks of the significance and wait bits, respectively, the register of the next the sector, the register of the destination address, the first informational inputs of which are connected to the SECOND antiscale output and the counter nomero-second informational inputs of the register of the regular sector and the register the destination address and the SECOND input of the first switch are connected to the information output of the address memory block, the bit output of the next sector register is connected to the third input of the first switch, the output of which is connected to the read inputs of the buffer memory block and the information counter of the read counter the output of the destination address register is connected to the second read inputs of the memory blocks and the significant and wait bits and the output of the device destination address, the first, second, third and fourth registers commands, informational inputs of which are connected to the first output of the block of the buffer memory of commands, the unpacking node coma. a lot of words. , each information input of which is connected to the bit output of the corresponding command register, command block-triggering triggers, the zero input of which is connected to the blocking output of the command buffer memory block, the reset input of the command significance trigger block, and the output of the command word unpacking block, and the output is connected to the input of the command word unpacking node, the first element OR, whose output is the indicator output of the device, the first input of the OR element is connected to the output of the block; the memory of the wait bits, the second input of the first OR element and the single input of the command significance trigger block are connected to the output of the memory block of significance bits, the instruction length decoder, the first command index register, the command index adder, the first input of which is connected to the output of the command length decoder, and the output is connected to the first information input of the first register, the command index, the transition index adder, the first input, the CRP, the command length decoder input, and. the command output of the device is connected to the output of the decompression node of the command words, the first comparison circuit whose output is the first controlling output of the device, the second command index register, the bit output of which is connected to the first input of the first comparison circuit, the second switch, EXIT. D which is the index output of the device AND is connected to the second information input of the command index register, the bit output of which is connected to the second inputs of the command index adder, transition index adder; the first comparison circuit and the control input of the command unpacking node, the third and fourth The index registers of the command, the bit outputs of which are connected to the first and second inputs of the second switch, respectively, are different in that, in order to improve speed, it contains the first buffer register The index, the second index buffer register, the first instruction decoder, second, third and fourth comparator circuit, a second OR element.  the first address register, the first buffer register, the second address register, the third index buffer register, 816 Forky address register, the third address register, the information inputs of the first index buffer register and the second index buffer register are connected to the bit output of the first command index register, the bit outputs of these registers are connected to the information inputs of the second and third registers of the command index, respectively, the first control panel of the command decoder is connected to the output of zeroing the unpacking command words, the output of this decoder is connected to the control input of the first comparison circuit, the second input of the command decoder is connected to the output of the second comparison circuit and the second control output of the device, the first inputs of the third and fourth comparison circuits are connected to the second bit output of the sector number counter, inputs the second element OR is connected to the outputs of the third and fourth comparison circuits, the output of the second element or is connected to the second control input of the sector number counter, the bit output of the buffer register is connected to By swiping the input of the first switch, the bit output of the first address register is connected to the fifth input of the first switch and to the second input of the third comparison circuit, the information input of the second address register is connected to the first input of the second comparison circuit, with the first information input of the first address register . the buffer register and the second bit output of the read counter, the first information input of the third index buffer register is the device index input, the second information input of the third index buffer register is connected. with the output of the transfer index adder, the bit output of the third buffer register of the index is connected to the information input of the fourth command index register, with the input of the second switch, with the index bypass of the address memory block and with the second information input of the first address register, the first information input of the buffer address register connected to the bit output of the second address register, the second information input of the buffer address register is connected to the bit output of the first command index register, information ny 17 .SkZQiB18 entry of the third register of the address of the Sources of Information, not with a bit output buffer-borne into account when examining address register, bit output1. US Patent And 3 90005, The third address register is connected. , 172.5, published 1970. with the second inputs of the second and fourth 2. US Patent If I am the schemes compare. 3JO, 172.5, 197 (prototype). -TO one W W 7ff l / fiWm u w I / g 7 I / W  A sh  r 1L f / k 0fff.J