SU868744A1 - Multiplexor channel - Google Patents

Description

(54) MULTIPLEX CHANNEL

one

The invention relates to computing technology, in particular, to orthanizing structures of multi-channel channels, and can be used for inputting information in digital computing systems.

Multiplex channels are known that contain the command word register, the address of the input command word, the modifier, addresses, request regaster, request selection circuitry, the external device number decoder, the command word address encoder, control circuitry, control bus transmission buses, and 1shf6r buses. The operation of such as 1vl occurs in parallel with the operation of the dectral processor and consists in receiving command words from the central processor and controlling the data exchange between the internal memory of an electronic digital computer (ESM) and a large number of external devices operating simultaneously. The command words selected from the internal memory of the digital computer are received into the device memory. The multiplex channel indicates the program interrupt indicator number.

the central processor at the end of the exchange, the counter of the number of exchanges and the memory area to be used during the exchange. After each single data exchange, a change is made to the number of exchanges and the current data address. Completing an I / O operation causes the CPU II program to interrupt.

The disadvantage of these channels is their

to low speed.

Claims (2)

Closest to the proposed technical entity is a multiplex channel that contains the processing unit of the central processor command, the input of which is connected to the first input of the channel, the communication register with the central processor, the first input of which is connected to the second input of the channel, and the second input to the first the output of the processing unit of the CPU command, the query storage register, the input of which is connected to the third channel input, and the output to the first input of the priority analysis unit, the second input of which is connected to the third output of the processing unit of the central processor command, the third input through the register permitting the implementation of requests and the address decoder of the external device — with the first output of the communication register with the central processor, and the output via the encoder of the external device — with the first output of the device, the first input of which is connected to the fourth input of the channel, and the first (the number of the indicator of interruption of the program of the central processor) and the second (the counter of the number of exchanges) exits to the inputs of the decoder of the ind number interrupt switch, the output of which is connected to the second output of the channel, the third one (the counter of data allocation addresses in the internal memory) and the fourth (the starting address places 11 data in the internal memory) the outputs of the control word register are fed to the inputs of the block to form the address of access internal memory, the output of which is connected to the third output of the channel, the fifth output of the command word register (control word) is fed to the input of the modification block. In this block, during each single data exchange, the state of the counters in the command word changes. From the output of the modification block, the comatz word enters the second input of the control word register, from the fifth output of which the control word goes to the fourth input of the data storage register, the first input of which is connected to the second channel input, the second input to the second output of the communication register the processor, and the third input - with the fifth input of the channel; the output of the storage register is 1C 1X connected to the input of the selector, the first, second and third outputs are connected to the fourth, fifth and sixth outputs of the device, respectively. The channel also contains a channel address memory switch, the first input of which is connected to the output of the external device address encoder, the second input — to the first output of the communications register with the central processor, and the output is connected to the seventh output of channel 2. In a known multiplex channel, KajtvJtoro processing the request for an external device to exchange information passes successively in the following stages: reading the command word corresponding to the most senior of the received requests from the device’s memory, exchanging information waiting for an external device, a senior who sent the request and said instruction word in the area of the internal memory of a digital computer, the modification instruction word and recording promodifitsirovash | koma1zdnogo th word in memory channel five. Service requests for external devices are organized sequentially; the service of each individual request begins after the service of the previous request has ended, and during the entire service time of one apros, the corresponding command word is entered in one command word register. This causes low bandwidth multiplex channel. The purpose of the invention is to increase the channel capacity. This goal is achieved by the fact that a multiplex channel containing a decryption unit of a central processing unit whose input is the first input of the channel; the communications register with the central processor, the first input of which is connected to the second input of the channel, and the second input - to the first output of the decoding module of the central processor command; the register of storing requests, the input of which is connected to the third input of the channel, and the output - to the first input of the priority block, the second input of which is connected to the second output of the decoding unit of the central processing unit, the third input through the register of the resolution for implementing queries and the address decoder of the external device - to the first output of the communication register from the center a processor, and the output is with the input of the encoder of the external device address, the first command word register, whose input is connected to the fourth channel input, and the output to the input of the modification block, the decoder number of the interrupt indicator, the output of which is connected to the first channel output, the address generation unit access to the internal memory, the output of which is connected to the second output of the channel, the data storage register, the first input of which is connected to the second input of the channel, the second input to the second output of the communication register with the central process a third input with a fifth channel input, and an output with a selector input, whose output group is a channel output group, a memory address address switch, the first input of which is connected to the output of an external device address encoder, the second input to the first the output of the communications register with the central processor, and the output with the third output of the device, the second and third registers of the control word, the first and second address registers of the external device and the switch, and the group of inputs of the second command register, are entered. The first word is connected to the group of outputs of the first command word register, the first group of outputs is connected to the group of inputs of the internal address memory address generation block, and the second rpyraia outputs is to the group of inputs of the third command word register, the first and second outputs of which are connected to the corresponding decoder inputs. the indicator number of the alarm, the output of the modification unit is connected to the fourth input of the data storage register, the input of the first register of the address of the external device is connected to the output of the address encoder of the external device TWA, and the output - with the input of the second register of the address outside the device, the first and second inputs of the switch are connected respectively to the outputs of the first and second address registers of the external device, and the output - with the fourth output of the device. FIG. 1 shows the block diagram of the proposed multiplex channel; in fig. 2 - command word structure. The multiplex channel (Fig. 1) contains inputs 1-5, outputs 6-9 and outputs 10, 11, and groups of channel outputs, block 13 for deciphering the CPU command with input 14. and outputs 15 and 16, register 17 for communication with the central processor with second and first inputs 18 and 19, second and first outputs 20 and 21, register 22 for storing queries with input 23 and output 24, priority block 25 with second, first and third inputs 26-28 and output 29, register 30 times implementation of requests with input 31 and output 32, the decoder 33 addresses of the external device with input 34 and output 35, the encoder 36 addresses of the external device with input 37 and output 38, the first register 39 of the address of the external device with input 40 and output 41, the second register 42 of the address of the external device with input 43 and output 44, switch 45 with inputs 46 and 47 and output 48, the first register 49 command words with input 50 and outputs 51-55 of the output group, the second register 56 of the control word with inputs 57-60 of the group of inputs and outputs 61 62 and 63, 64 of the first and second groups of outputs, the third register 65 of the control word with inputs 66 and 67 groups of inputs and outputs 68 and 69, the decoder 70 of the indicator number pre | to Shani inputs 71 and 72 and output 73, modification block 74 with input 75 and output 76, block 77 of forming the address for accessing the internal memory with inputs 78 and group of inputs and output 80, storage register 81 with the second, fourth, first and third inputs 82 -85 and output 86, selector 87 with input 88 and outputs 89-91 of the output group, switch 92 of memory access addresses with inputs 93 and 94 and output 95. The structure of the control word (Fig. 2) includes the following fields: the number 96 of the interrupt indicator of the central procedure program, when the exchange for this cr) completes the mandated word, the counter 97 of the number of exchanges that must be performed to complete the exchange, the counter 98 of the data placement addresses in the internal memory and the initial address 99 size of data in internal memory. The channel works as follows. The operation of the device is initiated by the command receiving the control word coming from the central processor to the input 14 of block 13. From output 15 to the register 17 it receives a signal to receive the control word, allowing the control word and the address of the external device from the central processor to be received in register 17 . Writing the control word to the memory is carried out as follows. The address of the external device, which is one-time, is the address of the host word in the memory, from the output 21 of the register 17 to the input 94 of the switch 92 and further to the channel memory. Following the transfer of the address to the memory, the control word is transmitted, which from the output 20 of the register 17 enters the input 82 of the register 81 and through the selector 87 to the output 12, from where it enters the channel. During the transmission of the control word from the central processor to the channel memory, operation of block 25 is blocked, for which blocking signals are received at input 26 of block 25 from output 16 of block 13. The presence in the memory of the channel of the control word for some external device is indicated by the corresponding discharge of the register 30, which is excited by signals sent to its input 31 from the output of the disfragrator 33. Implementation of requests from external devices for the exchange of information between any external device and internal memory The computer is carried out in the following sequence. Requests of external devices for data exchange are fed to input 23 of register 22. When there are signals to allow the implementation of requests coming from output 32 of register 30 to input 28 of unit 25, the latter selects a signal corresponding to the highest (zero) request. This signal goes to the encoder 36, from output 38 of which the address of the external device. At the same time, it is also the location address in the memory of the channel of the corresponding control word, and is fed to the input 93 of the switch 92, from output 95 of which to the channel memory. The command word read from this memory, corresponding to zero request, enters at input 4 into register 49. The control word from output 53 of register 49 enters block 74. At output 76 of the latter, new modified values of command word 97 and 98 and the remaining without changing the values of fields 96 and 99. From the output 76 of the block 74, the control word is fed to the input 83 of the register 81, from the output 86 of which through the selector 87 the command word enters & ampis to the output 12 to return to the channel memory at the address Coming from the encoder 36 through ommutator ztogo 92. Once the command word from register 49 is transferred to the register 56, the register 49 by releasing the control word corresponding to the next (first) request. Simultaneously with this transfer of the control word, the address of the external device that sent the zero transfer from the encoder 36 to the register 39 is also recorded. From the outputs 62 and 61 of the register 56, the fields 98 and 99 of the control word are necessary to form the current address to the internal memory. To zero request, go to block 77, from output 80 of which the generated address goes to output 7 of the device, and then to the internal memory of the digital computer In case of ec and it is necessary to record information in the internal memory of the electronic computer, to external devices from output 41 reg Istra 39 through the switch 45 receives the address of the external device, which identifies the external device involved in the exchange of information on the zero request. After that, fields 96 and 97 of the control word located on register 56, as well as the address of external devices on register 39 are transmitted respectively to registers 65 and 42, and corresponding registers from the first register 49 of control word and {thess an external device from the encoder 36 for forming the address for accessing the internal memory by the following (nepBONiy) request and identification of the external device that sent the request (in terms of writing data to the internal memory of the digital computer); Information exchange on a zero request is as follows. If the data is recorded in the internal memory, then the information from the external device goes to input 5, from where it goes to the input 85 of the rester 81 and then through the selector 87 to the output L, from which the insurer enters the internal memory of the computer, where data recording At the previously issued address from output 7. If the data is read from the internal memory of the digital computer, the read information from the internal memory goes to input 2 and then to input 84 of register 81 and then through selector 87 to output 10, from which - in the information bus external mouth and is used by an external device identified by the address coming from register 42 through switch 45 to output 9. Thus, the one-time data exchange A. on zero request is completed. In the case when the data exchange is completed completely and the state of the floor of the counter 97 of the number of exchanges is zero, the processor interrupt indicator numbers of the program are produced: the floor 96 and 97 of the control word from the register 65 are sent to the decoder 70 and then from code 16 to the central processor . Thus, the proposed multiplex channel allows an increase in the throughput capacity in a steady state according to the comparison curve of the known unal. This is due to the fact that in the proposed cough, simultaneously in the mode of overlapping the spilled stages, the servicing of requests for sheshnyh devices works on three command words, while at the same time, at one point in time, work is conducted on only one command word. Claims of the Invention A multiplex channel comprising the decoding decoding command of the ceschfshygo npoaeccof, the input of which is the first input of the channel, the communication register from the center of the oriental register, the first input of which is connected to the video input of the channel, and in the case of the connection with the output output of the network, and the connection of the network. pencetp is equal to a request whose input is joined with a TRFTH input to% -. and the input - with the first input of the block at (pi / gktov, the second input of which is connected to the second {output) output of the unit of the price processor command, the third input through the resolution register of the reaccation request (the address of the external device with the first : The output of the register of communication with the central processor, and the output - with the input of the external device encoder, the register of the KIND word, the input of which is connected to the fourth channel input, and the output - to the input of the modfshatsin unit, the decoder of the interrupt indicator number, the output is connected to the firstThe output of the kshal, the block of forms and the access to the internal memory, whose output is connected to the TV output channel, the data storage register, whose first input is connected to the BtoiMM channel input, the second input to the VTO1ShM output of the communication register with the central processor, the third an input with a 5 m channel input, and an output with a selector input, the output group of which is a channel output, address switch (rotation to memory, the first input of which is connected to the output of the external device address encoder, the second input to the output registerwith the central processor, and the output with the third output of the device, which is indicated by the fact that the second and third registers of the control word, the first and second registers of the external device and the switch, and the group of inputs of the second the command word register is connected to the output group of the first command word register, the first group of outputs to the group of inputs of the address generation block to the internal memory, and the second group of outputs to the group of inputs of the third register to Mandal words, the first and second outputs of which are connected to the corresponding inputs of the deactivator number of the priority indicator, the output of the modification block is connected to the fourth input of the data storage register, the input of the first address register of the external device is connected to the output of the external address encoder, and the output is connected to the second register address external device, the first and second input (switchboard connected respectively to the outputs of the first and second address registers of the external device, and the output - with the fourth output trszhstva. Sources of information taken into account in the examination 1.Kartsev M.A. Architecture of digital computers. M., Science, 1978, p. 265-267. 2. USSR author's certificate number 495659, cl. G 06 F 3/04, 1973 (prototype).