SU936409A1 - Constant lag device - Google Patents

Description

(5) DEVICE OF PERMANENT DELAY

I

This invention relates to automation and computing.

A device is known that contains a control unit, two reversible counters, a comparison unit, two valves, an inverter, a clock generator, a delay setting unit, and the output of the clock generator is connected to the counting inputs of the inserted reversible counters via the first valve, the output of the first of which is connected to the control input of the adjustable delay line and the additional output of the decoder, the output of the period measurement unit through the second valve is connected to the installation input of the second reversible counter, output One of which is connected to the input of the comparison unit, the second input of which is connected to the output of the delay setting unit, one output of the comparison unit is connected to the inputs of the counting direction of the reversible counters, the other output is with the control

the input of the first valve and an inverter with a control input of the second valve; one output of the control unit is connected to the control input of the second valve, and the other output is connected to the auxiliary input of the HUHtl element. However, this device is characterized by limited functionality.

It is also known a device containing a memory unit, a code comparison unit, a pulse series generator, a second valve and a reverse trigger, the first code comparison group being connected to the outputs of the second counter, second to the memory block outputs, the input of the pulse generator generator is connected to the input terminal of the device, the first Input IBTO of the left valve is connected to the output of the pulse train generator, its second input is connected to the output of the code comparison unit, and the output is connected to the counting input of the second counter, C - input

the reverse trigger is connected to the output of the electrical delay and the J-K-inputs to the compiler OjiOKa output, and the output of the reverse trigger is connected to ikotz - A control unit of the second counter -i of the storage unit, the input of the element g; 1 jar is connected to the output of the counter on one of the inputs of input trips .j whose second input is connected to an input device G 2,

However, this device is characterized by limited 1 mn functional i mibi MH of aa microcharacterization, consisting in an insufficient delay time / ck.

Closest to the present invention is a device containing a differentiated circuit, a front delay unit .; pulse generator, two vectors THJiHj, trigger trigger, reversible trigger, the summing input of which is connected to the output of the pulse generator 4) without vent, control unit whose input is connected to the source of the delayed and myloms, the subtracting input of the counter is connected to the pulse generator through the second} zeach-il, the control input of which is connected 5-5; 1en with the bullet output of the forming trigger, the outputs of the reverse counter of the counter through the decoder zero connection is connected with the single input of the trigger, to the Hyj-iesoNry input of which through the differentiating target and block ass The front is connected to a source of pulsed pulses, an additional valve, a trigger and an inverter, an additional gate input is connected to a source delaying AM pulses j and the output is connected to the control input of the first valve and to the differential switch inline, the output of which is connected to the inverter input, the inverter output The trigger is connected to the zero input dojLHHTejibHoro, the single (-) th input of which is connected to the output of the decoder zero, and the output to the control input of the additional trig controlled frequency divider, connected to the first, 1st signal input to the generator output control input counting pulses - to the exit and entry overflow MSB reBepcHBiioro counter reset input to the output deschifratora zero and the output - to the signal inputs of the first and second valves PP.

However, this device is characterized by inadequate fukdialnye opportunities, consisting in

limited class of transferred functional dependencies and deficiency {yu excerpt time,

The purpose of the invention is to increase the time delay and the expansion of the class of transferred functional dependencies,

The goal is achieved by the fact that two constant multipliers, two accumulating adders, an auxiliary magnitude determination unit and a combination adder are inserted into a constant delay device containing a clock pulse generator connected to the counting input of a pulse counter. The first input of the first multiplication unit is connected to the output of the pulse counter, and the second input is connected to the input of the device and the first input of the first iamopa5 storing bag. The output of the first multiplication unit is connected to the second accumulating adder outputs, the outputs of the first and second accumulating adders are connected to the inputs of the auxiliary quantities determination unit. The outputs of the auxiliary quantities determination unit are connected respectively to the inputs of the first and second storage DBs, the output of the first multiplication unit, the second the input of the second multiplication unit is connected to the output of the pulse counter 5; the output of the second multiplication unit is connected to the first input of the combinational adder, Ora input coupled to an output of the second storage unit, an output combination of the adder connected to the output device.

The drawing shows the functional electrical circuit of the proposed device of permanent delay.

The constant delay device contains a generator of I clock pulses, a pulse counter 2, the first 3 and second 4 multiplication blocks, the first 5 and second 6 accumulating adders, auxiliary value determination unit 7, the first 8 and second 9 memories, the combiner adder 10, and the input devices 1,

The proposed device works as follows.

From the output of the clock pulse generator 1, the pulse pulse 2 is fed to the pulse counter input. Synchronously with the clock pulses of the device input 11, the device receives P values of the input function. Thus, on the first accumulating adder 5, a value is formed equal to P

Cx

is-i

where xi i-oe is the value of the input function. On the second accumulating adder

a value is formed, C i-K .., Semi1 1

The values accumulated on the first and second accumulating adders go to the auxiliary unit 7 for determining auxiliary values, and the pulse counter, the first and second accumulating adders are set to the initial zero state. The accumulation process for subsequent function values is repeated. At the same time, the block for determining auxiliary values x 7 determines the auxiliary values a and b in accordance with the preceding half

total values of S K

mR VXu-l

l

according to the following formulas

a P, b P

and y

nix.Ct); p (p-1) ,.

 B.

  p (r); The resulting auxiliary values a and b are recorded in the first cells of the first and second storage devices, respectively. It should be noted that

 b)

P (p1i) P (PH) PIP-U

for specific values of P, can be predetermined and entered into the block for determining auxiliary values when setting up a constant delay device, which makes it easy to get auxiliary values a and b,

The recording in the first and second storage devices of post-value auxiliary values is as follows,

In the third stage of the calculations, the previously determined values of a and b from the first cells of the first and second memory devices are rewritten into the second cells, and the new values of a and b are recorded in the first. In the fourth stage of calculations, the previously obtained values of a and b from the second cells are rewritten in the third, and from the first to the second cells. In the first cells that were released, the newly obtained values of a and b are recorded. Thus, the process is repeated until all the K cells of the first and second storage devices are filled.

 the computation step obtained at the first computation stage, the values of auxiliary quantities. a and b. arrive at the first input of the second multiplication unit and the second input of the combinational adder, respectively.

In accordance with the above-mentioned connections, the output of the device will form a peak equal to P

0 (5: 1 and

U-1

I

THAT corresponds to the reproduction of the input values of the function with a delay t determined in accordance with the expression

f Y1-p-t,

where t is the period following the input values of the function entering the device input.

At the same time, the reproduction accuracy of the functional dependence is determined by the precision of the piecewise linear approximation.

Claims (3)

1. USSR author's certificate No. 683004, cl. H 03 K 5/13, 27.06.77. 2. USSR author's certificate No. 684730, cl. H03. K 5/13, 01.06.77. 3. USSR Authorship Certificate No. 699661, cl, Н03 К 5/13, 10.10.77 (. Prototype).