SU924710A2 - Program interrupting device - Google Patents

Description

The invention relates to computing technology and. can be used in digital computing systems.

According to the main author. St. No. 645158, there is a known device for interrupting programs, which contains a security register, the inputs of which are connected to a group of input buses, an encoder, an output OR element, whose output is connected to an interrupt bus, N interrupt channels, each of which contains an interrupt trigger, a control trigger, four elements AND and an OR element (and each external request bus of an external request bus group is connected respectively to the first one at the input of the first element AND of the simultaneous interruption channel, in each interrupt channel the output of the first element AND inn with the first input of the interrupt trigger, the output of the OR element of each previous interrupt channel is connected to the first input of the OR element and the first input of the second element AND the subsequent interruption channel, the output of the second element AND is connected to the first input of the third element AND and to the input of the encoder whose RELAYS tire output group

device, the first control trigger input of each interrupt channel is connected to the control of the same name

By a bus of a group of control buses and in each interrupt channel, the second input of the control trigger is connected to the output of the interruption trigger and the second input of the second element I, the third input of which is connected to the corresponding

10 by the input of the protection register and the first input of the fourth AND element, the output of which is connected to the second input of the OR element, the output of the control trigger is connected to the second input of the first element and to the second input of the fourth And element, the output of the third AND element is connected to the second input of the interrupt trigger, the second input of the third element And each channel

20 interrupts are connected to the response bus, the outputs of the second AND elements of each preemption channel are connected to the inputs of the output OR element.

The device provides servicing of external requests only with absolute priorities, i.e. the higher priority request terminates the lower priority request service, and then returns to the lower priority request service fj. However, the known device does not allow serving external requests with relative priorities, which limits the functionality of the known device. The purpose of the invention is to expand the scope of application by providing real-time operation. The goal is achieved by introducing a mode trigger, a second OR element and an AND element, the first input of which is connected to the output of the first IL element, the second input of the AND element connected to the control mode input of the device, the third input of the AND element connected to the synchronization input of the device, and its output is connected to the first input of the mode trigger, the second input of which is connected to the output of the second OR element, the inputs of the second OR element are connected to the group of control inputs of the device, the mode trigger output is connected to the first odes tre tego of AND and OR of the first channel interrupt. The drawing shows the layout of the program for interrupting programs. The device contains a register 1 for shields, an encoder 2, the first element OR 3, the trigger 4 modes, the element AND 5, second. This is an OR 6 element, channels / interrupts, each of which includes four AND 11 elements, an OR element 12, an interrupt trigger 13, and a control trigger 14. The drawing shows the following inputs and outputs: group 1 of the protection inputs, response input 16, group 17 of control inputs, group 18 of the external request inputs, interrupt input 19, output group 20, mode control input 21, synchronization input 22. When servicing external requests with absolute priorities, the device works as follows. The absolute priority operation mode is provided by the permissive output potential of the mode trigger 4, which is reset to the zero state when the device is turned on and set in one state is blocked by the inhibitory potential at the mode control input 21. In the initial state, the resolving potential from the outputs of the control triggers 14 is allowed to receive external requests. The signals of the external requests are received at the inputs 18 of the requests and, through the element 8, are detected by the interrupt triggers 13. The output potential from interrupt triggers are set to the corresponding 14 y trigger triggers, the output of which at the second inputs of the And 8 elements blocks the reception of the corresponding external request. The signals from the interrupt and control triggers are fed to the inputs of the And 9 and 10 elements, which highlight the request having the highest priority. The OR elements 12 provide for the end-to-end transmission of the interrupt inhibit signal from the highest priority level to the lowest. Request priorities are reduced from left to right in the order of the numbering of interrupt channels 7. Thus, the interrupt signal is generated only at the input of the AND 10 element of the interrupt channel 7 that is of the highest priority at the current time. This signal is fed to the input of the element OR 3, to the input of the encoder 2, and to the first input of the element 11 of the corresponding interrupt channel. At the output of the element OR 3, a control signal is generated, and at the output of the encoder 2, a transition command arriving at the digital computer. After receiving in the digital computer the transition command from it on input 16 of the answer to the second element I 11 of all channels, a signal is received. The request is received, which sets the interrupt trigger 13 of the channel currently running to zero. The control triggers 14 store external requests until they are fully executed and And 9 prohibits admission to a digital computer. lower priority external requests. The control triggers 14 are set to zero state at the end of the program caused by an external request, for which a control signal is issued from the digital computer via one of the buses of the group of control inputs 17 (each channel has its own control signal). Thus, at the second input of the element And 8 and the element And 9 a resolving potential is established, i.e. removed. blocking requests of the lowest priority level and the highest of them goes to the digital computer. The operation mode with relative priorities is provided by the permitting power at the input 21 of the mode control. After switching on the device, the trigger 4 of the mode is set to the zero state (the permitting potential at its output). The interrupt signal, issued from the device in the digital computer via the control bus 19, through the element 5, to the clock pulse received from the digital computer via the input 22, sets the trigger state 4, i.e. The interruption signals of all priority levels are prohibited for the VM. The trigger resets to zero state upon completion of the interrupt program by a signal from the corresponding input from the group of selector inputs 17 assembled on the element OR 6. The external request with the highest priority among all received by the device is received for execution in the digital computer and the device is again blocked to completing the service request.

The expansion of the functionality of the proposed device is achieved by providing service to external requests with relative priorities. The introduction of relative priorities leads to a decrease in the waiting time for requests with lower priorities while increasing the waiting time for requests with priorities.

In addition, on the whole, a number of control computer systems operating on a real time scale and controlling equipment with fast-running techiological processes, external requests with absolute priorities are unacceptable, since the control computer system must analyze the state of objects in a fixed time interval and in accordance with this state, give them control actions that are determined by those. the current state of the controlled process. If such systems use the discipline of servicing external requests with absolute priorities, a situation may arise when the program is interrupted after polling the equipment condition and control actions affecting the control objects will be transferred much later. The state of the equipment will change and the control output will not correspond to the current state of the controlled process.

The proposed device allows you to quickly change the discipline about serving external requests, i.e. in one mode of operation, the device can service requests with absolute priorities, and in the other with relative priorities. Mode switching can be performed by either a digital computer program, or an operator, or external devices of the system.

Claims (1)

1. Copyright certificate CCGP 645158, cl. G 06 F 9/46, 1976  40 (prototype).